Display panel and display device

Abstract

The utility model discloses a display panel which comprises a substrate, a plurality of sub-pixels arranged on the substrate, a plurality of data lines, a plurality of data outgoing lines, a plurality of electrostatic discharge circuits, at least one first voltage transmission line and at least one second voltage transmission line. The substrate comprises a display area and a first frame area located on one side of the display area in the first direction. The plurality of sub-pixels and the plurality of data lines are located in the display area. The plurality of data outgoing lines are located in the first frame area and are connected with the plurality of data lines. The plurality of electrostatic discharge circuits are located in the first frame area and are connected with the plurality of data outgoing lines. The first voltage transmission line and the second voltage transmission line are located in the first frame area and connected with the electrostatic discharge circuits. The first voltage transmission line and the second voltage transmission line are located on different conductive layers. According to the utility model, the anti-corrosion capability of the electrostatic discharge circuit can be improved.

Description

Technical Field

[0001] The utility model relates to but is not limited to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Organic light emitting diodes (OLED) and quantum dot light emitting diodes (QLED) are active light emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, lightness, flexibility and low cost. With the continuous development of display technology, display devices with OLED as the light emitting device and thin film transistors (TFT) for signal control have become the mainstream products in the current display field. Utility Model Content

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] In order to improve the corrosion resistance of the electrostatic discharge circuit, the embodiments of the present invention provide a display panel and a display device.

[0005] On the one hand, the present embodiment provides a display panel, comprising: a substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of data lead lines, a plurality of electrostatic discharge circuits, at least one first voltage transmission line, and at least one second voltage transmission line. The substrate comprises: a display area and a first frame area located on one side of the display area along a first direction. A plurality of sub-pixels are arranged on one side of the substrate and located in the display area. A plurality of data lines are located in the display area and configured to provide data signals to the plurality of sub-pixels. A plurality of data lead lines are located in the first frame area and connected to the plurality of data lines. A plurality of electrostatic discharge circuits are located in the first frame area and connected to the plurality of data lead lines. At least one first voltage transmission line is located in the first frame area and connected to the plurality of electrostatic discharge circuits and configured to provide a first voltage signal. At least one second voltage transmission line is located in the first frame area and connected to the plurality of electrostatic discharge circuits and configured to provide a second voltage signal, which is different from the first voltage signal. The at least one first voltage transmission line and the at least one second voltage transmission line are located in different conductive layers.

[0006] In some exemplary embodiments, the at least one first voltage transmission line is located on a side of the at least one second voltage transmission line away from the substrate; or, the at least one second voltage transmission line is located on a side of the at least one first voltage transmission line away from the substrate.

[0007] In some exemplary embodiments, the display panel includes at least: a first source-drain metal layer and a second source-drain metal layer disposed on the substrate; the second source-drain metal layer is located on a side of the first source-drain metal layer away from the substrate. The at least one first voltage transmission line is located in the first source-drain metal layer, and the at least one second voltage transmission line is located in the second source-drain metal layer; or the at least one second voltage transmission line is located in the first source-drain metal layer, and the at least one first voltage transmission line is located in the second source-drain metal layer.

[0008] In some exemplary embodiments, the display panel includes at least: a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer disposed on the substrate; the second source-drain metal layer is located on a side of the first source-drain metal layer away from the substrate, and the third source-drain metal layer is located on a side of the second source-drain metal layer away from the substrate. The at least one first voltage transmission line is located in the first source-drain metal layer or the second source-drain metal layer, and the at least one second voltage transmission line is located in the third source-drain metal layer; or the at least one second voltage transmission line is located in the first source-drain metal layer or the second source-drain metal layer, and the at least one first voltage transmission line is located in the third source-drain metal layer.

[0009] In some exemplary embodiments, the display panel includes at least: two first voltage transmission lines and one second voltage transmission line, the two first voltage transmission lines and the second voltage transmission line both extend along the second direction, the second voltage transmission line is located between the two first voltage transmission lines along the first direction; the second direction intersects the first direction. Alternatively, the display panel includes at least: two second voltage transmission lines and one first voltage transmission line, the two second voltage transmission lines and the first voltage transmission line both extend along the second direction, the first voltage transmission line is located between the two second voltage transmission lines along the first direction.

[0010] In some exemplary embodiments, the plurality of electrostatic discharge circuits are arranged in an array along the first direction and the second direction. The plurality of electrostatic discharge circuits are arranged in at least two rows along the first direction, and each row of electrostatic discharge circuits includes a plurality of electrostatic discharge circuits arranged along the second direction; the two rows of electrostatic discharge circuits are connected to the same first voltage transmission line or the same second voltage transmission line. The data lead-out line connected to the first row of electrostatic discharge circuits and the data lead-out line connected to the second row of electrostatic discharge circuits are located in different conductive layers.

[0011] In some exemplary embodiments, the electrostatic discharge circuit includes: a first transistor, a second transistor, a third transistor, and a fourth transistor. The first electrode of the first transistor is electrically connected to the second voltage transmission line, the gate and the second electrode of the first transistor are electrically connected to the first electrode of the second transistor, the gate and the second electrode of the second transistor are electrically connected to the first electrode of the third transistor and the data lead-out line, the gate and the second electrode of the third transistor are electrically connected to the first electrode of the fourth transistor, and the second electrode of the fourth transistor is electrically connected to the first voltage transmission line. The arrangement of the first transistor, the second transistor, the third transistor, and the fourth transistor of the first row electrostatic discharge circuit along the first direction is opposite to the arrangement of the first transistor, the second transistor, the third transistor, and the fourth transistor of the second row electrostatic discharge circuit along the first direction.

[0012] In some exemplary embodiments, the display panel further includes: an organic planar layer, a first inorganic insulating layer, and a touch inorganic insulating layer. The organic planar layer has an isolation groove surrounding the plurality of electrostatic discharge circuits in the first frame region. The first inorganic insulating layer is located on a side of the organic planar layer close to the substrate. The touch inorganic insulating layer is located on a side of the organic planar layer away from the substrate. The touch inorganic insulating layer contacts the first inorganic insulating layer through the isolation groove.

[0013] In some exemplary embodiments, the display panel further comprises: a touch protection layer. The touch protection layer is located on a side of the touch inorganic insulating layer away from the substrate. The orthographic projection of the touch protection layer on the substrate covers the orthographic projection of the plurality of electrostatic discharge circuits on the substrate.

[0014] In some exemplary embodiments, the display panel further includes: a touch protection layer and a metal covering layer. The touch protection layer is located on a side of the touch inorganic insulating layer away from the substrate, and the touch protection layer has a hollow area in the first frame area, and the orthographic projection of the hollow area on the substrate covers the orthographic projection of the multiple electrostatic discharge circuits on the substrate. The metal covering layer is located on a side of the touch protection layer away from the substrate, and the metal covering layer fills the hollow area.

[0015] In some exemplary embodiments, the first border area includes: a first sub-area, a bending area, and a second sub-area arranged in sequence along a first direction away from the display area; the multiple electrostatic release circuits, the at least one first voltage transmission line, and the at least one second voltage transmission line are located in the second sub-area.

[0016] On the other hand, this embodiment provides a display device, including the display panel as described above.

[0017] On the other hand, the present embodiment provides a display panel, comprising: a substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of data lead lines, a plurality of electrostatic discharge circuits, and an organic planar layer. The substrate comprises: a display area and a first frame area located on one side of the display area along a first direction. The first frame area comprises: a first sub-area, a bending area, and a second sub-area arranged in sequence along a first direction away from the display area. A plurality of sub-pixels are arranged on one side of the substrate and located in the display area. A plurality of data lines are located in the display area and are configured to provide data signals to the plurality of sub-pixels. A plurality of data lead lines are located in the first frame area and are connected to the plurality of data lines. A plurality of electrostatic discharge circuits are located in the first frame area and are connected to the plurality of data lead lines. The organic planar layer has an isolation groove surrounding the plurality of electrostatic discharge circuits in the second sub-area of ​​the first frame area.

[0018] In some exemplary embodiments, the display panel further includes: a first inorganic insulating layer and a touch inorganic insulating layer. The first inorganic insulating layer is located on a side of the organic planar layer close to the substrate; the touch inorganic insulating layer is located on a side of the organic planar layer away from the substrate; the touch inorganic insulating layer contacts the first inorganic insulating layer through the isolation groove.

[0019] In some exemplary embodiments, the display panel further includes: a touch protection layer and a metal covering layer. The touch protection layer is located on a side of the touch inorganic insulating layer away from the substrate, and the touch protection layer has a hollow area in the second sub-area of ​​the first frame area, and the orthographic projection of the hollow area on the substrate covers the orthographic projection of the multiple electrostatic discharge circuits on the substrate. The metal covering layer is located on a side of the touch protection layer away from the substrate, and the metal covering layer fills the hollow area.

[0020] The display panel provided in this embodiment can reduce the electric field strength between the first voltage transmission line and the second voltage transmission line by arranging the first voltage transmission line and the second voltage transmission line in different conductive layers, improve the water vapor corrosion situation, thereby reducing the electrochemical corrosion situation and improving the corrosion resistance of the electrostatic discharge circuit. Alternatively, by arranging isolation grooves around multiple electrostatic discharge circuits in the organic flat layer, water vapor isolation can be achieved, and the corrosion situation of the routing of the electrostatic discharge circuit can be improved, thereby improving the corrosion resistance of the electrostatic discharge circuit.

[0021] Other features and advantages of the utility model will be described in the following description, and partly become apparent from the description, or understood by implementing the utility model. The purpose and other advantages of the utility model can be realized and obtained through the structures particularly pointed out in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings are used to provide a further understanding of the technical solution of the utility model and constitute a part of the specification. Together with the embodiments of the utility model, they are used to explain the technical solution of the utility model and do not constitute a limitation on the technical solution of the utility model.

[0023] Figure 1 A schematic diagram of a display panel according to at least one embodiment of the present invention;

[0024] Figure 2 A schematic diagram of a first border area of ​​at least one embodiment of the utility model;

[0025] Figure 3A A partial cross-sectional schematic diagram of a display area of ​​at least one embodiment of the utility model;

[0026] Figure 3B is another partial cross-sectional schematic diagram of a display area of ​​at least one embodiment of the utility model;

[0027] Figure 3C is another partial cross-sectional schematic diagram of a display area of ​​at least one embodiment of the utility model;

[0028] Figure 3D is another partial cross-sectional schematic diagram of a display area of ​​at least one embodiment of the utility model;

[0029] Figure 4 A schematic diagram of local wiring in a first border area of ​​at least one embodiment of the utility model;

[0030] Figure 5 An equivalent circuit diagram of an electrostatic discharge circuit of at least one embodiment of the utility model;

[0031] Figure 6It is a partial plan view of the first border area of ​​at least one embodiment of the utility model;

[0032] Fig. 7A for Figure 6 A schematic diagram of a display panel after forming a first semiconductor layer;

[0033] Figure 7B for Figure 6 A schematic diagram of a display panel after a second gate metal layer is formed;

[0034] Figure 7C for Figure 6 A schematic diagram of a display panel after a first source-drain metal layer is formed;

[0035] Figure 8 for Figure 6 Schematic diagram of the local section along the QQ' direction;

[0036] Fig. 9 Another partial plan view of the first border region of at least one embodiment of the utility model;

[0037] Fig.10 for Fig. 9 A schematic diagram of a display panel after a first source-drain metal layer is formed;

[0038] Fig.11 for Fig. 9 Schematic diagram of the local section along the RR' direction;

[0039] Fig.12 Another partial plan view of the first border region of at least one embodiment of the utility model;

[0040] Fig.13 Another partial schematic diagram of the first border area of ​​at least one embodiment of the utility model;

[0041] Fig.14 for Fig.13 A partial enlarged schematic diagram of the middle area S1;

[0042] Fig.15 A partial cross-sectional schematic diagram of a first border region of at least one embodiment of the utility model;

[0043] Fig.16 Another partial cross-sectional schematic diagram of the first border region of at least one embodiment of the utility model;

[0044] Fig.17 Another partial cross-sectional schematic diagram of the first border region of at least one embodiment of the utility model;

[0045] Fig.18Another partial cross-sectional schematic diagram of the first border region of at least one embodiment of the utility model;

[0046] Fig.19 Another partial cross-sectional schematic diagram of the first border region of at least one embodiment of the utility model;

[0047] Fig. 20 Another partial cross-sectional schematic diagram of the first border region of at least one embodiment of the utility model;

[0048] Fig.21 Another partial cross-sectional schematic diagram of the first border region of at least one embodiment of the utility model;

[0049] Fig. 22 Another partial cross-sectional schematic diagram of the first border region of at least one embodiment of the utility model;

[0050] Fig.23 Another partial cross-sectional schematic diagram of the first border region of at least one embodiment of the utility model;

[0051] Fig.24 Another partial cross-sectional schematic diagram of the first border region of at least one embodiment of the utility model;

[0052] Fig.25 It is a schematic diagram of a display device according to at least one embodiment of the present invention. DETAILED DESCRIPTION

[0053] The embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. The embodiments can be implemented in a plurality of different forms. A person skilled in the art can easily understand the fact that the method and content can be transformed into other forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other arbitrarily.

[0054] In the drawings, the size of one or more components, the thickness of a layer, or an area is sometimes exaggerated for the sake of clarity. Therefore, one embodiment of the utility model is not necessarily limited to the size, and the shape and size of one or more components in the drawings do not reflect the true proportion. In addition, the drawings schematically show ideal examples, and one embodiment of the utility model is not limited to the shapes or values ​​shown in the drawings.

[0055] The ordinal numbers such as "first", "second", "third" and the like in this specification are provided to avoid confusion of constituent elements, rather than to limit the quantity. The "plurality" in this utility model means two or more.

[0056] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation on the present utility model. The positional relationship of the constituent elements is appropriately changed according to the orientation of the constituent elements being described. Therefore, it is not limited to the words and phrases described in the specification and can be appropriately replaced according to the circumstances.

[0057] In this specification, unless otherwise clearly stipulated and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, or an indirect connection through an intermediate piece, or the internal connection of two elements. Among them, "connection" may include "electrical connection", and "electrical connection" includes the situation where the constituent elements are connected together through an element with some electrical function. There is no special restriction on "elements with some electrical function" as long as the transmission of electrical signals between the connected constituent elements can be carried out. Examples of "elements with some electrical function" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with multiple functions. For ordinary technicians in this field, the meaning of the above terms in the utility model can be understood according to the situation.

[0058] In this specification, a transistor refers to an element including at least three terminals: a gate (gate electrode), a drain, and a source. A transistor has a channel region between a drain (drain electrode terminal, drain region, or drain electrode) and a source (source electrode terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, a channel region refers to a region where current mainly flows.

[0059] In this specification, the first electrode may be a drain electrode, the second electrode may be a source electrode, or the first electrode may be a source electrode, the second electrode may be a drain electrode. In addition, the gate electrode may also be referred to as a control electrode. In the case of using transistors with opposite polarities or in the case of a change in the direction of current during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged.

[0060] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0061] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate circles, approximate ellipses, approximate triangles, approximate rectangles, approximate trapezoids, approximate pentagons or approximate hexagons, etc. There may be some small deformations caused by tolerances, such as chamfers, arc edges and deformations.

[0062] In this specification, "approximately" and "substantially" mean that the limits are not strictly defined and the process and measurement errors are allowed. In the present utility model, "substantially the same" means that the values ​​differ by less than 10%.

[0063] In this specification, A extends along direction B means that A may include a main part and a secondary part connected to the main part, the main part is a line, line segment or strip-shaped body, the main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In this specification, "A extends along direction B" means "the main part of A extends along direction B".

[0064] In this specification, "A and B are of the same layer structure" means that A and B are formed simultaneously by the same patterning process. "The same layer" does not always mean that the thickness of the layer or the height of the layer is the same in the cross-sectional view. "The orthographic projection of A includes the orthographic projection of B" means that the orthographic projection of B falls within the orthographic projection range of A, or the orthographic projection of A covers the orthographic projection of B.

[0065] Figure 1 is a schematic diagram of a display panel of at least one embodiment of the present utility model. In some examples, such as Figure 1 As shown, the display panel may be a closed polygon including linear edges. The display panel may include: a display area AA and a frame area BB located around the display area AA. For example, the display area AA may include: a first display edge (lower display edge) and a second display edge (upper display edge) arranged relatively in a first direction D1, and a third display edge (left display edge) and a fourth display edge (right display edge) arranged relatively in a second direction D2. The first display edge and the second display edge may be linear edges parallel to each other, and the third display edge and the fourth display edge may be linear edges parallel to each other. Adjacent linear edges may be connected by curved edges (e.g., arcuate edges).

[0066] In some examples, such as Figure 1 As shown, the frame area BB may include: a first frame area B1 and a fourth frame area B4 located on both sides of the display area AA along the first direction D1, and a second frame area B2 and a third frame area B3 located on both sides of the display area AA along the second direction D2. The first frame area B1 may be connected to the first display edge, the second frame area B2 may be connected to the third display edge, the third frame area B3 may be connected to the fourth display edge, and the fourth frame area B4 may be connected to the second display edge. The first frame area B1 may be connected to the second frame area B2 and the third frame area B3, the third frame area B4 may be connected to the second frame area B2 and the third frame area B3, and the first frame area B1, the second frame area B2, the third frame area B3 and the fourth frame area B4 may be connected to surround the display area AA. For example, the first frame area B1 may also be referred to as the lower frame area of ​​the display panel, the second frame area B2 may also be referred to as the left frame area of ​​the display panel, the third frame area B3 may also be referred to as the right frame area of ​​the display panel, and the fourth frame area B4 may also be referred to as the upper frame area of ​​the display panel. However, this embodiment is not limited to this.

[0067] Figure 2 Schematic diagram of the first border area of ​​at least one embodiment of the utility model. In some examples, such as Figure 1 and Figure 2 As shown, the first frame area B1 may include: a first sub-area B11, a bending area B12, and a second sub-area B13 arranged in sequence along a side away from the display area AA in the first direction D1. The first sub-area B11 may also be referred to as a first fan-out area. The first sub-area B11 may be connected to the second frame area B2 and the third frame area B3, and connected to the display area AA. The bending area B12 may be connected between the first sub-area B11 and the second sub-area B13. The bending area B12 may be configured to bend the second sub-area B13 to the back of the display area AA.

[0068] In some examples, such as Figure 2 As shown, the second sub-area B13 of the first frame area B1 may include: a second fan-out area B131, a circuit setting area B132, a third fan-out area B133, a first signal access area B134, and a second signal access area B135, which are sequentially arranged in the first direction D1 along a direction away from the bending area B12. A plurality of data lead-out lines may be arranged in the first frame area B1, and the plurality of data lead-out lines may be electrically connected to the plurality of data lines in the display area in a one-to-one correspondence.

[0069] In some examples, the circuit setting area B132 may be provided with a plurality of electrostatic discharge circuits, and the plurality of electrostatic discharge circuits may be electrically connected to the plurality of data lead lines in a one-to-one correspondence. The plurality of electrostatic discharge circuits may be configured to prevent electrostatic damage to the display panel by eliminating static electricity. The circuit setting area B132 may also be provided with a plurality of test circuits, and the plurality of test circuits may be configured to provide test data signals to the data lines of the display area AA.

[0070] In some examples, the first signal access area B134 may be provided with a plurality of first contact pads, and the plurality of first contact pads may be configured to connect an integrated circuit (IC). The second signal access area B135 may be provided with a plurality of second contact pads, and the plurality of second contact pads may be configured to be bound and connected to an external flexible printed circuit (FPC). At least one first contact pad in the first signal access area B134 and at least one second contact pad in the second signal access area B135 may be connected by routing.

[0071] In some examples, such as Figure 1 As shown, the display area AA of the display panel may include at least: a plurality of sub-pixels PX, a plurality of gate lines GL, and a plurality of data lines DL. The plurality of gate lines GL may extend along the second direction D2 and be arranged along the first direction D1; the plurality of data lines DL may extend along the first direction D1 and be arranged along the second direction D2. The plurality of data lines DL may be electrically connected to the plurality of sub-pixels PX, and the plurality of data lines DL may be configured to provide data signals to the plurality of sub-pixels PX. The plurality of gate lines GL may be electrically connected to the plurality of sub-pixels PX, and the plurality of gate lines GL may be configured to provide pixel control signals to the plurality of sub-pixels PX. For example, the pixel control signal may include a scan signal, or may include a scan signal and a light emitting control signal, or may include a scan signal, a reset control signal, and a light emitting control signal.

[0072] In some examples, the second direction D2 may be an extension direction (e.g., a row direction) of the gate line GL in the display area AA; the first direction D1 may be an extension direction (e.g., a column direction) of the data line in the display area AA. The first direction D1 and the second direction D2 may intersect each other, for example, may be perpendicular to each other.

[0073] In some examples, a pixel unit of display area AA may include three sub-pixels, and the three sub-pixels may be a first sub-pixel emitting a first color light (e.g., red light), a second sub-pixel emitting a second color light (e.g., blue light), and a third sub-pixel emitting a third color light (e.g., green light). However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, and the four sub-pixels may be a sub-pixel emitting red light, a sub-pixel emitting green light, a sub-pixel emitting blue light, and a sub-pixel emitting white light. For another example, a pixel unit may include four sub-pixels, and the four sub-pixels may include a sub-pixel emitting red light, a sub-pixel emitting blue light, and two sub-pixels emitting green light.

[0074] In some examples, a sub-pixel may include: a pixel circuit and a light-emitting element electrically connected to the pixel circuit. The pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure. Wherein, T in the above circuit structure refers to a thin film transistor, C refers to a capacitor, the number before T represents the number of thin film transistors in the circuit, and the number before C represents the number of capacitors in the circuit. In some examples, the multiple transistors in the pixel circuit may include P-type transistors and N-type transistors. In other examples, the multiple transistors in the pixel circuit may be P-type transistors or may be N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product.

[0075] In some examples, the shape of the light-emitting element of the sub-pixel can be a rectangle, a rhombus, a pentagon, or a hexagon. When a pixel unit includes three sub-pixels, the light-emitting elements of the three sub-pixels can be arranged in parallel horizontally, vertically, or in a triangle; when a pixel unit includes four sub-pixels, the light-emitting elements of the four sub-pixels can be arranged in parallel horizontally, vertically, or in a square. However, this embodiment is not limited to this.

[0076] In some examples, the light-emitting element may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including: mini-LED or micro-LED), etc. For example, the light-emitting element may be an OLED, and the light-emitting element may emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel circuit. The color of the light emitted by the light-emitting element may be determined as required. In some examples, the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element may be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited to this.

[0077] Figure 3A It is a partial cross-sectional schematic diagram of a display area of ​​at least one embodiment of the present utility model. Figure 3A The structure of a sub-pixel in the display area is used as an example for illustration. In this example, the pixel circuit includes a low-temperature polysilicon thin film transistor and an oxide thin film transistor. The display panel of this example can integrate a touch structure, such as an integrated mutual capacitance touch structure, to form an FMLOC structure.

[0078] In some examples, such as Figure 3A As shown, in the direction perpendicular to the display panel, the display area of ​​the display panel may include at least: a substrate 10, and a circuit structure layer 12, a light emitting structure layer 13, a packaging structure layer 14 and a touch structure layer 15 sequentially arranged on the substrate 10. The circuit structure layer 12 may include at least: a pixel circuit of a plurality of sub-pixels, and the pixel circuit of each sub-pixel may include a plurality of transistors and at least one capacitor. The light emitting structure layer 13 may include at least: a light emitting element of a plurality of sub-pixels.

[0079] In some examples, Figure 3A In the figure, each sub-pixel includes a first type transistor 21, a second type transistor 22 and a capacitor 23. The first type transistor 21 may be a low temperature polysilicon thin film transistor, and the second type transistor 22 may be an oxide thin film transistor.

[0080] In some examples, the circuit structure layer 12 of the display area may include: a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source-drain metal layer, and a second source-drain metal layer, which are arranged on the substrate 10. A first insulating layer 101 may be arranged between the first semiconductor layer and the first gate metal layer, and a second insulating layer 102 may be arranged between the first gate metal layer and the second gate metal layer; a third insulating layer 103 may be arranged between the second gate metal layer and the second semiconductor layer; a fourth insulating layer 104 may be arranged between the second semiconductor layer and the third gate metal layer; a fifth insulating layer 105 may be arranged between the third gate metal layer and the first source-drain metal layer; a sixth insulating layer 106 (also referred to as a passivation layer) and a seventh insulating layer 107 (also referred to as a first planar layer) may be arranged between the first source-drain metal layer and the second source-drain metal layer, and the seventh insulating layer 107 may be located on a side of the sixth insulating layer 106 away from the substrate 10; and an eighth insulating layer 108 (also referred to as a second planar layer) may be arranged on a side of the second source-drain metal layer away from the substrate 10. Among them, the first insulating layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, the fifth insulating layer 105 and the sixth insulating layer 106 can be inorganic insulating layers, and the seventh insulating layer 107 and the eighth insulating layer 108 can be organic insulating layers. However, this embodiment is not limited to this. In other examples, a buffer layer can also be provided on the side of the first semiconductor layer close to the substrate, and the buffer layer can prevent harmful substances in the substrate from invading the interior of the display panel, and can also increase the adhesion of the film layer in the display panel on the substrate. In other examples, a bottom shading metal layer (BSM, Bottom Shielding Metal) can also be provided on the side of the buffer layer close to the substrate, and the bottom shading metal layer can be configured to at least partially cover the active layer of the transistor of the pixel circuit to avoid external light from affecting the performance of the transistor. In other examples, the sixth insulating layer can be omitted between the first source and drain metal layer and the second source and drain metal layer, and only the seventh insulating layer can be provided between the first source and drain metal layer and the second source and drain metal layer.

[0081] In some examples, such as Figure 3AAs shown, the first semiconductor layer in the display area may include at least: a first active layer 210 of a first type transistor 21. The first active layer 210 of the first type transistor 21 may include: a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first gate metal layer may include at least: a first gate 213 of the first type transistor 21, and a first plate 231 of the capacitor 23. The orthographic projection of the first gate 213 of the first type transistor 21 on the substrate 10 may cover the orthographic projection of the channel region 2100 of the first active layer 210 on the substrate 10. The second gate metal layer may include at least: a second plate 232 of the capacitor 23, and a third gate 224 of the second type transistor 22. The orthographic projections of the second plate 232 and the first plate 231 of the capacitor 23 on the substrate 10 may at least partially overlap, for example, the two may overlap. The second semiconductor layer may include at least: a second active layer 220 of the second type transistor 22. The third gate metal layer may include at least: a second gate 223 of the second type transistor 22. The orthographic projection of the second gate 223 of the second type transistor 22 on the substrate 10 may partially overlap with the orthographic projection of the second active layer 220 on the substrate 10. The orthographic projection of the third gate 224 of the second type transistor 22 on the substrate 10 may partially overlap with the orthographic projection of the second active layer 220 on the substrate 10. The third gate 224 may be the bottom gate of the second type transistor 22, and the second gate 223 may be the top gate of the second type transistor 22.

[0082] In some examples, such as Figure 3AAs shown, the first source-drain metal layer in the display area may include at least: a first source 211 and a first drain 212 of the first type transistor 21, and a second source 221 and a second drain 222 of the second type transistor 22. The fifth insulating layer 105 may be provided with a plurality of pixel vias (for example, including a first pixel via, a second pixel via, a third pixel via, and a fourth pixel via) in the display area. The fifth insulating layer 105, the fourth insulating layer 104, the third insulating layer 103, the second insulating layer 102, and the first insulating layer 101 in the first pixel via may be removed to expose at least a portion of the surface of the first region 2101 of the first active layer 210; the fifth insulating layer 105, the fourth insulating layer 104, the third insulating layer 103, the second insulating layer 102, and the first insulating layer 101 in the second pixel via may be removed to expose at least a portion of the surface of the second region 2102 of the first active layer 210. The fifth insulating layer 105, the fourth insulating layer 104 and the third insulating layer 103 in the third pixel via hole and the fourth pixel via hole can be removed to expose at least part of the surface of the two ends of the second active layer 220. The first source 211 of the first type transistor 21 can be electrically connected to the first area 2101 of the first active layer 210 through the first pixel via hole, and the first drain 212 can be electrically connected to the second area 2102 of the first active layer 210 through the second pixel via hole. The second source 221 of the second type transistor 22 can be electrically connected to one end of the second active layer 220 through the third pixel via hole, and the second drain 222 of the second type transistor 22 can be electrically connected to the other end of the second active layer 220 through the fourth pixel via hole. The second source-drain metal layer can include at least: a first switching electrode 241. The first switching electrode 241 can be electrically connected to the first drain 212 of the first type transistor 21 of the pixel circuit through the fifth pixel via hole opened in the sixth insulating layer 106 and the seventh insulating layer 107. In this example, the electrical connection between the pixel circuit and the light emitting element can be achieved through the first switching electrode 241 .

[0083] In some examples, the gate line of the display area may be located in the first gate metal layer and the third gate metal layer, the data line of the display area may be located in the second source-drain metal layer, and the first power line of the display area may be located in the second source-drain metal layer. This embodiment is not limited to this. In other examples, the circuit structure layer of the display area may further include: a third source-drain metal layer located on the side of the second source-drain metal layer away from the substrate.

[0084] In some examples, such as Figure 3AAs shown, the light emitting structure layer 13 may include: a pixel definition layer 134 and a plurality of light emitting elements. For example, each light emitting element may include: a stacked first electrode 131, an organic light emitting layer 132 and a second electrode 133. The first electrode 131 of the light emitting element may be an anode, and the first electrode 131 may be disposed on the eighth insulating layer 108, and electrically connected to the first transfer electrode 241 through the sixth pixel via hole provided in the eighth insulating layer 108. The pixel definition layer 134 is disposed on the first electrode 131 and the eighth insulating layer 108, and the pixel definition layer 134 may be provided with a plurality of pixel openings, and one pixel opening may expose at least part of the surface of a corresponding first electrode 131. At least part of the organic light emitting layer 132 may be disposed in one pixel opening and connected to the corresponding first electrode 131. The second electrode 133 may be disposed on the organic light emitting layer 132 and connected to the organic light emitting layer 132. The organic light emitting layer 132 may emit light of corresponding colors under the drive of the first electrode 131 and the second electrode 133.

[0085] In some examples, the organic light-emitting layer 132 of the light-emitting element may include a light-emitting layer (EML, Emitting Layer), and at least one of the following film layers: a hole injection layer (HIL, Hole Injection Layer), a hole transport layer (HTL, Hole Transport Layer), a hole blocking layer (HBL, Hole Block Layer), an electron blocking layer (EBL, Electron Block Layer), an electron injection layer (EIL, Electron Injection Layer), and an electron transport layer (ETL, Electron Transport Layer). Under the voltage drive of the first electrode 131 and the second electrode 133, the light-emitting characteristics of the organic material can be used to emit light according to the required grayscale.

[0086] In some examples, the light-emitting layers of light-emitting elements of different colors may be different. For example, the red light-emitting element includes a red light-emitting layer, the green light-emitting element includes a green light-emitting layer, and the blue light-emitting element includes a blue light-emitting layer. In order to reduce the process difficulty and improve the yield, the hole injection layer and the hole transport layer on one side of the light-emitting layer may use a common layer, and the electron injection layer and the electron transport layer on the other side of the light-emitting layer may use a common layer. In some examples, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer can be made by a single process (a single evaporation process or a single inkjet printing process), and isolation is achieved by means of a surface step difference of the formed film layer or by surface treatment. For example, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer corresponding to adjacent sub-pixels may be isolated. In some examples, the organic light-emitting layer can be formed by evaporation using a fine metal mask (FMM, FineMetal Mask) or an open mask (Open Mask), or by inkjet technology.

[0087] In some examples, such as Figure 3A As shown, the encapsulation structure layer 14 may include a first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143 stacked. Among them, the first encapsulation layer 141 and the third encapsulation layer 143 may be made of inorganic materials, such as silicon nitride, silicon oxide, silicon oxynitride, etc. The inorganic material has high density and can prevent the intrusion of water, oxygen, etc. The second encapsulation layer 142 may be arranged between the first encapsulation layer 141 and the third encapsulation layer 143 to ensure that external water vapor cannot enter the light-emitting element. The second encapsulation layer 142 may be made of organic materials, for example, it may be a polymer material containing a desiccant or a polymer material that can block water vapor, or it may be a polymer resin, etc. to flatten the surface of the display panel, and it may relieve the stress of the first encapsulation layer 141 and the third encapsulation layer 143, and it may also include a desiccant and other water-absorbing materials to absorb water, oxygen, and other substances that invade the interior. However, this embodiment is not limited to this. For example, the encapsulation structure layer may adopt a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0088] In some examples, the touch structure layer of the display area may include: a plurality of first touch electrodes, a plurality of first connecting portions, a plurality of second touch electrodes, and a plurality of second connecting portions. The plurality of first touch electrodes may be arranged in the same layer, and adjacent first touch electrodes may be connected via the first connecting portions. The plurality of second touch electrodes may be arranged in the same layer, and adjacent second touch electrodes may be connected via the second connecting portions.

[0089] In some examples, such as Figure 3AAs shown, in the direction perpendicular to the display panel, the touch structure layer 15 of the display area may include: a touch buffer layer (TBL) 150, a first touch conductive layer 151, a touch interlayer insulating layer (TLD) 153, a second touch conductive layer 152, and a touch protection layer (TOC) 154 arranged in sequence. Among them, the touch buffer layer 150 and the touch interlayer insulating layer 153 may be inorganic insulating layers, and the touch protection layer 154 may be an organic insulating layer. For example, the first touch conductive layer 151 may include a plurality of first touch electrodes, a plurality of second touch electrodes, and a plurality of first connecting portions. The first touch electrodes and the first connecting portions may be an integral structure connected to each other. The second touch conductive layer 152 may include a plurality of second connecting portions. The second connecting portions may be connected to the adjacent second touch electrodes through vias provided in the touch interlayer insulating layer 153. However, this embodiment is not limited to this. In other examples, the first touch conductive layer may include: a plurality of first touch electrodes, a plurality of second touch electrodes and a plurality of second connecting portions, and the second touch electrodes and the second connecting portions may be an integrated structure connected to each other; the second touch conductive layer may include a plurality of first connecting portions, and the first connecting portions may be connected to adjacent first touch electrodes through vias provided in the touch interlayer insulating layer. In some examples, the first touch electrode may be a drive (Tx) electrode, and the second touch electrode may be a sense (Rx) electrode. Alternatively, the first touch electrode may be a sense (Rx) electrode, and the second touch electrode may be a drive (Tx) electrode. This embodiment is not limited to this.

[0090] In some examples, the first touch electrode and the second touch electrode may have a rhombus shape, such as a regular rhombus, a horizontally long rhombus, or a vertically long rhombus. In other examples, the first touch electrode and the second touch electrode may have any one or more of a triangle, a square, a trapezoid, a parallelogram, a pentagon, a hexagon, and other polygons, which is not limited in the embodiments of the present utility model.

[0091] In some examples, the first touch electrode and the second touch electrode may be in the form of transparent conductive electrodes. In other examples, the first touch electrode and the second touch electrode may be in the form of a metal grid, the metal grid may be formed by interweaving a plurality of metal wires, the metal grid may include a plurality of grid patterns, and the grid pattern may be a polygon formed by a plurality of metal wires. The first touch electrode and the second touch electrode in the metal grid format have the advantages of low resistance, small thickness, and fast response speed.

[0092] Figure 3B FIG. 1 is another partial cross-sectional schematic diagram of a display area of ​​at least one embodiment of the present invention. Figure 3BAs shown, the circuit structure layer 12 of the display area may include: a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source-drain metal layer, a second source-drain metal layer and a third source-drain metal layer arranged on the substrate 10. An eighth insulating layer 108 may be arranged between the second source-drain metal layer and the third source-drain metal layer, and a ninth insulating layer 109 (also referred to as a third flat layer) may be arranged on the side of the third source-drain metal layer away from the substrate 10. The eighth insulating layer 108 and the ninth insulating layer 109 may both be organic insulating layers. The third source-drain metal layer may include at least: a second transfer electrode 242. The second transfer electrode 242 may be connected to the first transfer electrode 241 located in the second source-drain metal layer through a via hole opened in the eighth insulating layer 108. In this example, the electrical connection between the pixel circuit and the light-emitting element may be achieved through the first transfer electrode 241 and the second transfer electrode 242. For the remaining structure of the display area of ​​the display panel of this example, reference may be made to Figure 3A The description of the embodiment shown is therefore not repeated here.

[0093] Figure 3C Another partial cross-sectional schematic diagram of a display area of ​​at least one embodiment of the present invention. In some examples, the transistor types of multiple pixel transistors in the pixel circuit may be the same, for example, they may all be low-temperature polysilicon thin-film transistors. Figure 3C In the figure, a first type transistor 21 and a capacitor 23 included in each sub-pixel are taken as an example for illustration.

[0094] In some examples, such as Figure 3C As shown, the circuit structure layer 12 of the display area may include: a first semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer and a second source-drain metal layer arranged on the substrate 10. A first insulating layer 101 may be arranged between the first semiconductor layer and the first gate metal layer, a second insulating layer 102 may be arranged between the first gate metal layer and the second gate metal layer, a third insulating layer 103 may be arranged between the second gate metal layer and the first source-drain metal layer, a sixth insulating layer 106 and a seventh insulating layer 107 may be arranged between the first source-drain metal layer and the second source-drain metal layer, and an eighth insulating layer 108 may be arranged on the side of the second source-drain metal layer away from the substrate 10. The seventh insulating layer 107 and the eighth insulating layer 108 may be organic insulating layers, and the first insulating layer 101, the second insulating layer 102, the third insulating layer 103 and the sixth insulating layer 106 may be inorganic insulating layers. The remaining structures of the display area of ​​the display panel of this example may be referred to. Figure 3A The description of the embodiment shown is therefore not repeated here.

[0095] Figure 3D FIG. 1 is another partial cross-sectional schematic diagram of a display area of ​​at least one embodiment of the present invention. Figure 3DAs shown, the circuit structure layer 12 of the display area may include: a first semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a second source-drain metal layer and a third source-drain metal layer arranged on the substrate 10. An eighth insulating layer 108 may be arranged between the second source-drain metal layer and the third source-drain metal layer, and a ninth insulating layer 109 (also referred to as a third flat layer) may be arranged on the side of the third source-drain metal layer away from the substrate 10. The eighth insulating layer 108 and the ninth insulating layer 109 may both be organic insulating layers. The third source-drain metal layer may include at least: a second transfer electrode 242. The second transfer electrode 242 may be connected to the first transfer electrode 241 located in the second source-drain metal layer through a via hole opened in the eighth insulating layer 108. In this example, the electrical connection between the pixel circuit and the light-emitting element may be achieved through the first transfer electrode 241 and the second transfer electrode 242. For the remaining structure of the display area of ​​the display panel of this example, reference may be made to Figure 3C The description of the embodiment shown is therefore not repeated here.

[0096] Figure 4 The figure is a schematic diagram of local wiring in the first border area of ​​at least one embodiment of the utility model. Figure 4 The figure mainly illustrates the data lead-out lines in the first border area, and omits the illustration of the remaining wiring lines in the first border area.

[0097] In some examples, such as Figure 4 As shown, the data lead lines in the first frame area may include: a first data lead line 261 located in the first sub-area B11 and a second data lead line 262 located in the second sub-area. The multiple data lead lines in the first frame area can be electrically connected to the multiple data lines in the display area in a one-to-one correspondence. Among them, the multiple first data lead lines 261 in the first sub-area B11 can be configured to connect the multiple data lines DL in the display area AA in a fan-out routing manner. The multiple first data lead lines 261 can be electrically connected to the multiple data lines DL in a one-to-one correspondence. For example, the multiple first data lead lines 261 can be alternately arranged in the first gate metal layer and the second gate metal layer.

[0098] In some examples, the bending region B12 may be provided with a plurality of data bending connection lines 263. The plurality of data bending connection lines 263 may be electrically connected to the plurality of first data lead lines 261 in a one-to-one correspondence. For example, the plurality of data bending connection lines 263 may be located in the second source-drain metal layer. However, this embodiment is not limited to this. In other examples, the plurality of data bending connection lines in the bending region may be located in the first source-drain metal layer.

[0099] In some examples, a plurality of second data lead lines 262 may extend from the second fan-out area B131 to the third fan-out area B133. A plurality of second data lead lines 262 may be electrically connected to a plurality of data bend connection lines 263 in a one-to-one correspondence. For example, a plurality of second data lead lines 262 may be alternately arranged in the first gate metal layer and the second gate metal layer. A plurality of first data lead lines 261 and a plurality of second data lead lines 262 may be connected by a plurality of data bend connection lines 263. A plurality of second data lead lines 262 may be connected to a plurality of electrostatic discharge circuits in the circuit setting area B132, and extend to the first signal access area B134, and be connected to the first contact pad in the first signal access area B134. For example, a plurality of second data lead lines 262 may be electrically connected to a plurality of electrostatic discharge circuits in a one-to-one correspondence.

[0100] Figure 5 is an equivalent circuit diagram of an electrostatic discharge circuit of at least one embodiment of the present utility model. In some examples, such as Figure 5 As shown, at least one electrostatic discharge circuit is connected to a data lead line SL (for example, the second data lead line 262), and is configured to release the static electricity in the data lead line SL connected thereto. An electrostatic discharge circuit may include: a first transistor ST1, a second transistor ST2, a third transistor ST3, and a fourth transistor ST4. The first electrode of the first transistor ST1 is electrically connected to the second voltage transmission line VGL, the gate and the second electrode of the first transistor ST1 are electrically connected to the first electrode of the second transistor ST2, the gate and the second electrode of the second transistor ST2 are electrically connected to the data lead line SL corresponding to the electrostatic discharge circuit, the first electrode of the third transistor ST3 is electrically connected to the data lead line SL corresponding to the electrostatic discharge circuit, the gate and the second electrode of the third transistor ST3 are electrically connected to the first electrode of the fourth transistor ST4, and the gate and the second electrode of the fourth transistor ST4 are electrically connected to the first voltage transmission line VGH. The transistor types of the first transistor ST1, the second transistor ST2, the third transistor ST3, and the fourth transistor ST4 may be the same, for example, they may all be P-type transistors or N-type transistors.

[0101] In some examples, the first voltage transmission line VGH may be configured to transmit a first voltage signal, and the second voltage transmission line VGL may be configured to transmit a second voltage signal. The first voltage signal may be greater than the second voltage signal.

[0102] In one example, providing an electrostatic discharge circuit can prevent static electricity accumulation in the data lead-out line from causing discharge breakdown and resulting in damage, so as to release the static electricity accumulated in the data lead-out line and protect the data lead-out line.

[0103] In another example, the electrostatic discharge circuit may include two transistors, wherein one electrode of each transistor is connected to its own gate, thereby forming an equivalent diode connection; and the signal line to be protected is connected between the two "diodes", and the other two ends of the two "diodes" are respectively connected to the first voltage transmission line VGH and the second voltage transmission line VGL. Thus, when a transient high voltage (such as 100V) appears in the signal line due to the accumulation of positive charges, one of the "diodes" is turned on to release the positive charges in the signal line; and when a transient low voltage (such as -100V) appears in the signal line due to the accumulation of negative charges, the other "diode" is turned on to release the negative charges in the signal line.

[0104] In some implementations, there is a high-low voltage difference between the first voltage transmission line and the second voltage transmission line connected to the multiple electrostatic discharge circuits in the second sub-area, and metal corrosion is prone to occur in this area under reliable operation, resulting in display abnormality. The display panel provided in this embodiment optimizes the setting of the electrostatic discharge circuit to improve the corrosion resistance of the electrostatic discharge circuit.

[0105] Figure 6 It is a partial plan view of the first frame area of ​​at least one embodiment of the utility model. Fig. 7A for Figure 6 Schematic diagram of a display panel after the first semiconductor layer is formed. Figure 7B for Figure 6 Schematic diagram of a display panel after a second gate metal layer is formed. Figure 7C for Figure 6 Schematic diagram of a display panel after the first source and drain metal layer is formed. Figure 8 for Figure 6 Schematic diagram of the local section along the QQ' direction.

[0106] In some examples, such as Figure 6 As shown, the multiple electrostatic release circuits in the second sub-area can be arranged in an array along the first direction D1 and the second direction D2. The multiple electrostatic release circuits arranged along the second direction D2 are a row of electrostatic release circuits, and the multiple electrostatic release circuits arranged along the first direction D1 are a column of electrostatic release circuits. For example, the circuit setting area of ​​the second sub-area can be arranged with two rows and multiple columns of electrostatic release circuits. Among them, a row of electrostatic release circuits close to the bending area is the first row of electrostatic release circuits 401, and a row of electrostatic release circuits away from the bending area is the second row of electrostatic release circuits 402.

[0107] In some examples, such as Figure 6As shown, two rows of electrostatic discharge circuits can be connected to the same second voltage transmission line VGL, the first voltage transmission line VGHa connected to the first row of electrostatic discharge circuits 401 can be located on the side of the second voltage transmission line VGL close to the bending area, and the first voltage transmission line VGHb connected to the second row of electrostatic discharge circuits 402 can be located on the side of the second voltage transmission line VGL away from the bending area. The second voltage transmission line VGL, the first voltage transmission lines VGHa and VGHb can all extend along the second direction D2, and the second voltage transmission line VGL can be located between the two first voltage transmission lines VGHa and VGHb in the first direction D1.

[0108] In some examples, such as Figure 6 As shown, the arrangement of the four transistors of the first row electrostatic discharge circuit 401 along the first direction D1 may be opposite to the arrangement of the four transistors of the second row electrostatic discharge circuit 402 along the first direction D1. Among them, the first transistor ST1, the second transistor ST2, the third transistor ST3 and the fourth transistor ST4 of each electrostatic discharge circuit (for example, the electrostatic discharge circuit 40a) in the first row electrostatic discharge circuit 401 may be arranged in sequence from the second voltage transmission line VGL to the first voltage transmission line VGHa along the first direction D1; the first transistor ST1, the second transistor ST2, the third transistor ST3 and the fourth transistor ST4 of each electrostatic discharge circuit (for example, the electrostatic discharge circuit 40b) in the second row electrostatic discharge circuit 402 may be arranged in sequence from the second voltage transmission line VGL to the first voltage transmission line VGHb along the first direction D1.

[0109] The structure of the electrostatic discharge circuit is described below by taking the first row electrostatic discharge circuit 401 as an example.

[0110] In some examples, such as Figure 6 and Fig. 7A As shown, the first semiconductor layer in the first border region may include: active layers of transistors of multiple electrostatic discharge circuits, for example, an active layer ST10 of a first transistor ST1 of an electrostatic discharge circuit 40a, an active layer ST20 of a second transistor ST2, an active layer ST30 of a third transistor ST3, and an active layer ST40 of a fourth transistor ST4. The active layer ST10 of a first transistor ST1 of an electrostatic discharge circuit, the active layer ST20 of a second transistor ST2, the active layer ST30 of a third transistor ST3, and the active layer ST40 of a fourth transistor ST4 may be an integrated structure. For example, the orthographic projection of the integrated structure on the substrate may be a strip extending along the first direction D1.

[0111] In some examples, such as Figure 6 and Figure 7BAs shown, the first gate metal layer in the first frame region may include: a plurality of second data lead lines 262a, and gates of transistors of a plurality of electrostatic discharge circuits (for example, the gate ST11 of the first transistor ST1 of the electrostatic discharge circuit 40a, the gate ST21 of the second transistor ST2, the gate ST31 of the third transistor ST3, and the gate ST41 of the fourth transistor ST4). The gate ST11 of the first transistor ST1 of an electrostatic discharge circuit, the gate ST21 of the second transistor ST2, the gate ST31 of the third transistor ST3, and the gate ST41 of the fourth transistor ST4 may all extend along the second direction D2, and be aligned along the first direction D1. The orthographic projection of the gate ST11 of the first transistor ST1, the gate ST21 of the second transistor ST2, the gate ST31 of the third transistor ST3, and the gate ST41 of the fourth transistor ST4 on the substrate may be a strip extending along the second direction D2.

[0112] In some examples, such as Figure 6 and Figure 7B As shown, the second gate metal layer in the first frame region may include: a plurality of second data lead lines 262b. The plurality of second data lead lines 262a and 262b may extend at least along the first direction D1 and be alternately arranged along the second direction D2. A second data lead line 262a and a second data lead line 262b may be arranged between two adjacent columns of electrostatic discharge circuits.

[0113] In some examples, such as Figure 6 and Figure 7CAs shown, the first source-drain metal layer in the first frame region may include: two first voltage transmission lines VGHa and VGHb, and a plurality of connection electrodes (for example, including a first connection electrode 331, a second connection electrode 332, a third connection electrode 333, a fourth connection electrode 334, and a fifth connection electrode 335). The orthographic projections of the first connection electrode 331, the second connection electrode 332, the fourth connection electrode 334, and the fifth connection electrode 335 on the substrate may be strips extending along the first direction D1, and the orthographic projection of the third connection electrode 333 on the substrate may be approximately L-shaped. Among them, the first connection electrode 331 can be connected to the gate ST41 of the fourth transistor ST4 and the active layer ST40; the second connection electrode 332 can be connected to the gate ST31 of the third transistor ST3 and the active layer ST30; the third connection electrode 333 can be connected to the gate ST21 of the second transistor ST2 and the active layer ST20 and a second data lead line 262a (or a second data lead line 262b); the fourth connection electrode 334 can be connected to the gate ST11 of the first transistor ST1 and the active layer ST10; the fifth connection electrode 335 can be connected to the active layer ST10 of the first transistor ST1. The first connection electrode 331 connected to the first row electrostatic discharge circuit 401 and the first voltage transmission line VGHa connected thereto can be an integrated structure. The first connection electrode 331 connected to the second row electrostatic discharge circuit 402 and the first voltage transmission line VGHb connected thereto can be an integrated structure.

[0114] In some examples, such as Figure 6 As shown, the second source-drain metal layer in the first frame region may include at least: a second voltage transmission line VGL. The second voltage transmission line VGL may extend at least along the second direction D2. The second voltage transmission line VGL may be connected to a plurality of fifth connection electrodes 335 located in the first source-drain metal layer. For example, the length of the second voltage transmission line VGL along the first direction D1 may be greater than the length of the first voltage transmission line VGHa (or VGHb) along the first direction D1.

[0115] In some examples, the film layer of the display area of ​​the display panel is Figure 3C As shown in the example, Figure 8As shown, in the first frame area, the first voltage transmission lines VGHa and VGHb located in the first source and drain metal layer can be provided with a display inorganic insulating layer 301 on the side close to the substrate 10, and the display inorganic insulating layer 301 can include, for example: a stacked first insulating layer 101, a second insulating layer 102 and a third insulating layer 103. The first voltage transmission lines VGHa and VGHb located in the first source and drain metal layer are provided with a sixth insulating layer 106 (also referred to as a passivation layer) and a seventh insulating layer 107 (also referred to as a first flat layer) on the side away from the substrate 10, and the second voltage transmission line VGL located in the second source and drain metal layer is provided with an eighth insulating layer 108 (also referred to as a second flat layer) on the side away from the substrate 10. The eighth insulating layer 108 is provided with a touch interlayer insulating layer 153 and a touch protection layer 154 on the side away from the substrate 10. The orthographic projections of the touch interlayer insulating layer 153 and the touch protection layer 154 on the substrate 10 can cover the orthographic projections of multiple electrostatic discharge circuits on the substrate 10.

[0116] In this example, by setting the first voltage transmission line and the second voltage transmission line in different conductive layers, wherein the first voltage transmission line is set in the first source-drain metal layer and the second voltage transmission line is set in the second source-drain metal layer, the electric field strength between the first voltage transmission line and the second voltage transmission line can be reduced, water vapor corrosion can be improved, thereby reducing electrochemical corrosion and enhancing the corrosion resistance of the electrostatic release circuit.

[0117] Fig. 9 Another partial plan view of the first border area of ​​at least one embodiment of the utility model. Fig.10 for Fig. 9 Schematic diagram of a display panel after the first source and drain metal layer is formed. Fig.11 for Fig. 9 Schematic diagram of the local section along the RR' direction.

[0118] In some examples, such as Figures 9 to 11As shown, multiple electrostatic release circuits in the second sub-area are arranged in an array along the first direction D1 and the second direction D2, for example, arranged in two rows and multiple columns. Two rows of electrostatic release circuits are connected to the same second voltage transmission line VGL, and each row of electrostatic release circuits is connected to a first voltage transmission line, wherein the first row of electrostatic release circuits 401 is connected to the first voltage transmission line VGHa, and the second row of electrostatic release circuits 402 is connected to the first voltage transmission line VGHb. The first voltage transmission lines VGHa and VGHb can be located in the second source and drain metal layer, and the second voltage transmission line VGL can be located in the first source and drain metal layer. The second voltage transmission line VGL and the multiple fifth connection electrodes 335 located in the first source and drain metal layer can be an integrated structure. The first voltage transmission line VGHa can be connected to the first connection electrode 331 located in the first source and drain metal layer and connected to the first row of electrostatic release circuits 401; the first voltage transmission line VGHb can be connected to the first connection electrode 331 located in the first source and drain metal layer and connected to the second row of electrostatic release circuits 402. The remaining structures of the electrostatic discharge circuit of this example can refer to the description of the aforementioned embodiment, so they are not described again here.

[0119] In this example, by setting the first voltage transmission line and the second voltage transmission line in different conductive layers, wherein the first voltage transmission line is set in the second source-drain metal layer and the second voltage transmission line is set in the first source-drain metal layer, the electric field strength between the first voltage transmission line and the second voltage transmission line can be reduced, water vapor corrosion can be improved, thereby reducing electrochemical corrosion and enhancing the corrosion resistance of the electrostatic release circuit.

[0120] Fig.12 FIG. 1 is another partial plan view of the first border region of at least one embodiment of the utility model. In some examples, such as Fig.12 As shown, two rows of electrostatic discharge circuits can share a first voltage transmission line VGH, the second voltage transmission line VGLa connected to the first row of electrostatic discharge circuits 401 can be located on the side of the first voltage transmission line VGH close to the bending region, and the second voltage transmission line VGLb connected to the second row of electrostatic discharge circuits 402 can be located on the side of the first voltage transmission line VGH away from the bending region. The first voltage transmission line VGH, the second voltage transmission lines VGLa and VGLb can all extend along the second direction D2, and the first voltage transmission line VGH can be located between the two second voltage transmission lines VGLa and VGLb in the first direction D1.

[0121] In some examples, such as Fig.12As shown, the arrangement of the four transistors of the first row electrostatic discharge circuit 401 along the first direction D1 may be opposite to the arrangement of the four transistors of the second row electrostatic discharge circuit 402 along the first direction D1. The first transistor ST1, the second transistor ST2, the third transistor ST3 and the fourth transistor ST4 of each electrostatic discharge circuit in the first row electrostatic discharge circuit 401 may be arranged in sequence along the first direction D1 from the second voltage transmission line VGLa to the first voltage transmission line VGH; the first transistor ST1, the second transistor ST2, the third transistor ST3 and the fourth transistor ST4 of each electrostatic discharge circuit in the second row electrostatic discharge circuit 402 may be arranged in sequence along the first direction D1 from the second voltage transmission line VGLb to the second voltage transmission line VGH.

[0122] In this example, the first voltage transmission line VGH is located in the second source-drain metal layer, and the two second voltage transmission lines VGLa and VGLb are located in the first source-drain metal layer, which can reduce the electric field strength between the first voltage transmission line and the second voltage transmission line, improve the water vapor corrosion situation, thereby reducing the electrochemical corrosion situation and improving the corrosion resistance of the electrostatic discharge circuit. The rest of the description of the display panel of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here. In other examples, the first voltage transmission line VGH can be located in the first source-drain metal layer, and the two second voltage transmission lines VGLa and VGLb can be located in the second source-drain metal layer.

[0123] Fig.13 Another partial schematic diagram of the first border area of ​​at least one embodiment of the utility model. Fig.14 for Fig.13 A partial enlarged schematic diagram of the middle area S1. Fig.15 This is a partial cross-sectional schematic diagram of the first border area of ​​at least one embodiment of the utility model. Fig.15 for Fig.13 Schematic diagram of the local section along the PP' direction, Fig.15 Only part of the membrane layer is shown. Fig.13 The figure mainly illustrates the data lead-out lines in the first border area, and omits the illustration of the remaining wiring lines in the first border area.

[0124] In some examples, such as Figures 13 to 15 As shown, the organic flat layer in the first frame area may have an isolation groove 50 surrounding a plurality of electrostatic discharge circuits. For example, the isolation groove 50 may surround the circuit setting area B132. For example, the orthographic projection of the isolation groove 50 on the substrate may be a rectangular ring. In other examples, the orthographic projection of the isolation groove 50 on the substrate may be other shapes such as a circular ring or an elliptical ring.

[0125] The film layer of the display area of ​​the display panel is as follows Figure 3CFor example, Fig.15 As shown, the organic flat layer in the first border area may include: a seventh insulating layer 107 and an eighth insulating layer 108 stacked together. The organic flat layer in the first border area may include: a first flat portion and a second flat portion separated by an isolation groove 50. The first flat portion may be a portion surrounded by the isolation groove 50, and the second flat portion may be a portion outside the isolation groove 50. For example, the orthographic projection of the first flat portion on the substrate may cover the orthographic projections of multiple electrostatic release circuits 40 on the substrate. The touch-sensitive inorganic insulating layer located on the side of the organic flat layer away from the substrate 10 may be a touch-sensitive interlayer insulating layer 153. The touch-sensitive interlayer insulating layer 153 may be in contact with the first inorganic insulating layer through the isolation groove 50, and the first inorganic insulating layer may be the sixth insulating layer 106 (also referred to as a passivation layer). In other examples, Figure 3C As an example of the film structure shown in FIG. 1 , when the sixth insulating layer is omitted, the first inorganic insulating layer may be the third insulating layer, and the touch interlayer insulating layer may be in contact with the third insulating layer through the isolation groove; Figure 3A Taking the film layer structure shown as an example, when the sixth insulating layer is omitted, the first inorganic insulating layer can be the fifth insulating layer, and the touch interlayer insulating layer can contact the fifth insulating layer through the isolation groove. Since it is necessary to remove part of the inorganic insulating layer in the bending area to improve the bending performance, it is easy to increase the risk of water vapor intrusion in the second sub-area. In this example, by setting an isolation groove in the organic flat layer, and making the inorganic insulating layer on the side of the organic flat layer away from the substrate and the side close to the substrate contact through the isolation groove, water vapor barrier can be achieved, and the wiring corrosion in the circuit setting area can be improved, thereby improving the corrosion resistance of the electrostatic discharge circuit.

[0126] In some examples, such as Fig.14As shown, the circuit setting area B132 can be provided with multiple electrostatic discharge circuits 40 and multiple test circuits, and the multiple test circuits can be located on the side of the multiple electrostatic discharge circuits 40 away from the second fan-out area B131. A first peripheral power line 61 can be set on both sides of the multiple electrostatic discharge circuits 40 along the second direction D2, and the first peripheral power line 61 can be configured to provide a first power signal to the sub-pixels of the display area. For example, the first peripheral power line 61 can be located in the first source and drain metal layer or the second source and drain metal layer. Multiple electrostatic discharge circuits 40 can be connected to the first voltage transmission lines VGHa and VGHb, and to the second voltage transmission line VGL. The first voltage transmission lines VGHa and VGHb can be connected to the first voltage connection line 411, and the second voltage transmission line VGL can be connected to the second voltage connection line 421. The first voltage connection line 411 and the second voltage connection line 421 can extend at least along the first direction D1, and the second voltage connection line 421 can be located on the side of the first voltage connection line 411 away from the multiple electrostatic discharge circuits 40. The first voltage connection line 411 and the second voltage connection line 421 may extend to the second signal access area B135 and be connected to the corresponding second contact pad in the second signal access area B135. For example, the first voltage connection line 411 and the second voltage connection line 421 may be located in the first source-drain metal layer. The first voltage connection line 411 and the first voltage transmission lines VGHa and VGHb located in the first source-drain metal layer may be an integrated structure, and the second voltage transmission line VGL located in the second source-drain metal layer may be connected to the second voltage connection line 421 through an opening provided in the insulating layer.

[0127] In this example, by setting the first voltage transmission line and the second voltage transmission line in different conductive layers, wherein the first voltage transmission line is set in the first source-drain metal layer and the second voltage transmission line is set in the second source-drain metal layer, the electric field strength between the first voltage transmission line and the second voltage transmission line can be reduced, the water vapor corrosion situation can be improved, thereby reducing the electrochemical corrosion situation and improving the corrosion resistance of the electrostatic discharge circuit. In addition, by setting isolation grooves around multiple electrostatic discharge circuits in the organic flat layer, water vapor isolation can be achieved, and the wiring corrosion situation in the circuit setting area can be improved, thereby improving the corrosion resistance of the electrostatic discharge circuit.

[0128] Fig.16 Another partial cross-sectional schematic diagram of the first frame area of ​​at least one embodiment of the utility model. Fig.16 Can be Fig.13 Another partial cross-sectional schematic diagram along the PP' direction in FIG. 1 is shown, and only part of the film layer is shown. In some examples, such as Fig.16As shown, the organic planar layer in the first frame region (including the stacked seventh insulating layer 107 and the eighth insulating layer 108) may have an isolation groove 50 surrounding a plurality of electrostatic discharge circuits. The first voltage transmission lines VGHa and VGHb may be located in the first source-drain metal layer, and the second voltage transmission line VGL may be located in the second source-drain metal layer.

[0129] In this example, by setting the first voltage transmission line and the second voltage transmission line in different conductive layers, wherein the first voltage transmission line is set in the second source-drain metal layer, and the second voltage transmission line is set in the first source-drain metal layer, the electric field strength between the first voltage transmission line and the second voltage transmission line can be reduced, the water vapor corrosion situation can be improved, thereby reducing the electrochemical corrosion situation and improving the corrosion resistance of the electrostatic discharge circuit. Moreover, by setting an isolation groove 50 around multiple electrostatic discharge circuits in the organic flat layer, water vapor barrier can be achieved, and the wiring corrosion situation in the circuit setting area can be improved, thereby improving the corrosion resistance of the electrostatic discharge circuit. The rest of the description of the display panel of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0130] Fig.17 Another partial cross-sectional schematic diagram of the first frame area of ​​at least one embodiment of the utility model. Fig.17 Can be Fig.13 Another partial cross-sectional schematic diagram along the PP' direction in FIG. 1 is shown, and only part of the film layer is shown. In some examples, such as Fig.17 As shown, the organic flat layer (including the seventh insulating layer 107 and the eighth insulating layer 108) in the first frame area may have an isolation groove 50 surrounding multiple electrostatic discharge circuits. The first voltage transmission lines VGHa and VGHb may be located in the first source-drain metal layer, and the second voltage transmission line VGL may be located in the second source-drain metal layer. A metal cover layer (MCL, Metal Cover Layer) 16 is also provided on the side of the touch protection layer 154 away from the substrate 10. The metal cover layer 16 may be configured to cover the routing in the bending area. The touch protection layer 154 may have a hollow area 1540 in the first frame area, and the hollow area 1540 may expose a portion of the surface of the touch interlayer insulating layer 153 away from the substrate 10. For example, the orthographic projection of the hollow area 1540 and the isolation groove 50 on the substrate 10 may partially overlap, or may not overlap, for example, the isolation groove 50 may surround the hollow area 1540. The metal cover layer 16 may be filled in the hollow area 1540. The orthographic projection of the hollow area 1540 on the substrate 10 can cover the orthographic projections of multiple electrostatic discharge circuits on the substrate 10. For example, the material of the metal covering layer 16 may include an organic insulating material. In this example, the stress on the electrostatic discharge circuit after the metal covering layer is set can be reduced by removing the touch protection layer above the electrostatic discharge circuit. The rest of the description of the display panel of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0131] Fig.18 Another partial cross-sectional schematic diagram of the first frame area of ​​at least one embodiment of the utility model. Fig.18 Can be Fig.13 Another partial cross-sectional schematic diagram along the PP' direction in FIG. 1 is shown, and only part of the film layer is shown. In some examples, such as Fig.18 As shown, the organic flat layer in the first frame area (including the stacked seventh insulating layer 107 and the eighth insulating layer 108) may have an isolation groove 50 surrounding multiple electrostatic release circuits. The first voltage transmission lines VGHa and VGHb may be located in the second source-drain metal layer, and the second voltage transmission line VGL may be located in the first source-drain metal layer. The touch protection layer 154 may have a hollow area 1540 in the first frame area, and the metal covering layer 16 may be filled in the hollow area 1540. The orthographic projection of the hollow area 1540 on the substrate 10 may cover the orthographic projections of multiple electrostatic release circuits on the substrate 10. In this example, by digging out the touch protection layer above the electrostatic release circuit, the stress on the electrostatic release circuit after the metal covering layer is set can be reduced. The rest of the description of the display panel of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0132] Fig.19 Another partial cross-sectional schematic diagram of the first frame area of ​​at least one embodiment of the utility model. Fig.19 Can be Fig.13 Another partial cross-sectional schematic diagram along the PP' direction in FIG. 1 is shown, and only part of the film layer is shown. In some examples, such as Fig.19 As shown, the organic flat layer in the first frame area (including the stacked seventh insulating layer 107 and the eighth insulating layer 108) may have an isolation groove 50 surrounding multiple electrostatic discharge circuits. The first voltage transmission lines VGHa and VGHb, and the second voltage transmission line VGL may all be located in the first source and drain metal layer. The touch interlayer insulating layer 153 may contact the sixth insulating layer 106 through the isolation groove 50. The positive projection of the touch protection layer 154 on the substrate 10 may cover the positive projection of multiple electrostatic discharge circuits on the substrate 10. In this example, by providing an isolation groove around multiple electrostatic discharge circuits in the organic flat layer, the risk of water vapor intrusion caused by the removal of part of the inorganic insulating layer in the bending area can be improved, water vapor barrier can be achieved, and the corrosion of the wiring in the circuit setting area can be improved, thereby improving the corrosion resistance of the electrostatic discharge circuit. In other examples, the first voltage transmission lines VGHa and VGHb, and the second voltage transmission line VGL may all be located in the second source and drain metal layer. The remaining description of the display panel of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0133] Fig. 20 Another partial cross-sectional schematic diagram of the first frame area of ​​at least one embodiment of the utility model. Fig. 20 Can be Fig.13 Another partial cross-sectional schematic diagram along the PP' direction in FIG. 1 is shown, and only part of the film layer is shown. In some examples, such as Fig. 20 As shown, the first voltage transmission lines VGHa and VGHb, and the second voltage transmission line VGL may be located in the first source-drain metal layer. The touch protection layer 154 may have a hollow area 1540 in the first frame area, and the metal covering layer 16 may be filled in the hollow area 1540. The orthographic projection of the hollow area 1540 on the substrate 10 may cover the orthographic projections of multiple electrostatic release circuits on the substrate 10. In this example, the stress on the electrostatic release circuit after the metal covering layer 16 is set can be reduced by removing the touch protection layer 154 above the electrostatic release circuit. The rest of the description of the display panel of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0134] Figure 21 to Figure 24 Another partial cross-sectional schematic diagram of the first frame area of ​​at least one embodiment of the utility model. Figure 21 to Figure 24 Can be Fig.13 Another partial cross-sectional schematic diagram along the PP' direction is shown, and only part of the film layer is shown. Figure 3B or Figure 3D As shown in the example, Figure 21 to Figure 24 As shown, the organic planar layer in the first frame region may include: a stacked seventh insulating layer 107, an eighth insulating layer 108, and a ninth insulating layer 109. The touch inorganic insulating layer located on the side of the organic planar layer away from the substrate 10 may be a touch interlayer insulating layer 153. The touch interlayer insulating layer 153 may be in contact with the first inorganic insulating layer through the isolation groove 50, and the first inorganic insulating layer may be the sixth insulating layer 106 (also referred to as a passivation layer).

[0135] In some examples, such as Fig.21 As shown, the first voltage transmission lines VGHa and VGHb may be located in the third source-drain metal layer, and the second voltage transmission line VGL may be located in the first source-drain metal layer. Fig. 22 As shown, the first voltage transmission lines VGHa and VGHb may be located at the first source-drain metal layer, and the second voltage transmission line VGL may be located at the third source-drain metal layer. Fig.23 As shown, the first voltage transmission lines VGHa and VGHb may be located in the third source-drain metal layer, and the second voltage transmission line VGL may be located in the second source-drain metal layer. Fig.24 As shown, the first voltage transmission lines VGHa and VGHb may be located in the second source-drain metal layer, and the second voltage transmission line VGL may be located in the third source-drain metal layer.

[0136] In this example, by setting the first voltage transmission line and the second voltage transmission line in different conductive layers, the electric field strength between the first voltage transmission line and the second voltage transmission line can be reduced, the water vapor corrosion situation can be improved, thereby reducing the electrochemical corrosion situation and improving the corrosion resistance of the electrostatic discharge circuit. In addition, by setting an isolation groove 50 around multiple electrostatic discharge circuits in the organic flat layer, water vapor isolation can be achieved, and the wiring corrosion situation in the circuit setting area can be improved, thereby improving the corrosion resistance of the electrostatic discharge circuit. The rest of the description of the display panel of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0137] In other examples, when the circuit structure layer of the display panel also includes: a third source-drain metal layer, a third flat layer, a fourth source-drain metal layer and a fourth flat layer located on the side of the second source-drain metal layer away from the substrate, the first voltage transmission line and the second voltage transmission line in the first frame area can be located in different source-drain metal layers. For example, the first voltage transmission line can be located in the fourth source-drain metal layer, and the second voltage transmission line can be located in the third source-drain metal layer, the second source-drain metal layer or the first source-drain metal layer; the organic insulating layer with isolation grooves may include: a stacked first flat layer, a second flat layer, a third flat layer and a fourth flat layer.

[0138] The present embodiment also provides a display panel, comprising: a substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of data lead-out lines, a plurality of electrostatic discharge circuits, and an organic planar layer. The substrate comprises: a display area and a first frame area located on one side of the display area along a first direction. The first frame area comprises: a first sub-area, a bending area, and a second sub-area arranged in sequence along a first direction away from the display area. A plurality of sub-pixels are arranged on one side of the substrate and located in the display area. A plurality of data lines are located in the display area and are configured to provide data signals to the plurality of sub-pixels. A plurality of data lead-out lines are located in the first frame area and are connected to the plurality of data lines. A plurality of electrostatic discharge circuits are located in the first frame area and are connected to the plurality of data lead-out lines. The organic planar layer has an isolation groove surrounding the plurality of electrostatic discharge circuits in the second sub-area of ​​the first frame area.

[0139] This embodiment can improve the risk of water vapor intrusion caused by the removal of part of the inorganic insulating layer in the bending area by setting isolation grooves around multiple electrostatic release circuits in the organic flat layer, achieve water vapor barrier, improve the wiring corrosion in the circuit setting area, and thus enhance the corrosion resistance of the electrostatic release circuit.

[0140] In some exemplary embodiments, the display panel may further include: a first inorganic insulating layer and a touch inorganic insulating layer. The first inorganic insulating layer is located on a side of the organic flat layer close to the substrate; the touch inorganic insulating layer is located on a side of the organic flat layer away from the substrate. The touch inorganic insulating layer contacts the first inorganic insulating layer through the isolation groove. For example, the touch inorganic insulating layer may include a touch interlayer insulating layer. In this example, by providing an isolation groove in the organic flat layer and making the inorganic insulating layer on the side of the organic flat layer away from the substrate and the side close to the substrate contact through the isolation groove, water vapor barrier can be achieved, and the corrosion of the wiring in the circuit setting area can be improved, thereby improving the corrosion resistance of the electrostatic discharge circuit.

[0141] In some exemplary embodiments, the display panel may further include: a touch layer and a metal covering layer. The touch protection layer is located on a side of the touch inorganic insulating layer away from the substrate, and the touch protection layer has a hollow area in the second sub-area of ​​the first frame area, and the orthographic projection of the hollow area on the substrate covers the orthographic projection of the multiple electrostatic release circuits on the substrate. The metal covering layer is located on a side of the touch protection layer away from the substrate, and the metal covering layer fills the hollow area. In this example, by digging out the touch protection layer above the electrostatic release circuit, the stress on the electrostatic release circuit after the metal covering layer is set can be reduced.

[0142] For the description of the display panel of this example, reference can be made to the description of the aforementioned embodiment, and thus it will not be repeated here.

[0143] Fig.25 FIG. 1 is a schematic diagram of a display device according to at least one embodiment of the present invention. Fig.25 As shown, the present embodiment provides a display device 91, including the display panel 910 of the aforementioned embodiment. In some examples, the display panel 910 may be an OLED display panel, such as an OLED display panel with an integrated touch structure. The display device 91 may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator, or may be a product or component with touch and display functions. In some examples, the display device 91 may be a wearable display device, such as one that can be worn on a human body in some manner. For example, the display device 91 may be a smart watch, a smart bracelet, etc. However, the present embodiment is not limited to this.

[0144] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example" or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the utility model. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0145] Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations of the present invention. Ordinary technicians in the field can change, modify, replace and modify the above embodiments within the scope of the present invention.

Claims

1. A display panel, characterized in that: include: A substrate, comprising: a display area and a first frame area located at one side of the display area along a first direction; A plurality of sub-pixels are arranged on one side of the substrate and located in the display area; a plurality of data lines, located in the display area, configured to provide data signals to the plurality of sub-pixels; A plurality of data lead-out lines, located in the first frame area and connected to the plurality of data lines; A plurality of electrostatic discharge circuits, located in the first frame area and connected to the plurality of data lead lines; at least one first voltage transmission line, located in the first frame area and connected to the plurality of electrostatic discharge circuits, and configured to provide a first voltage signal; at least one second voltage transmission line, located in the first frame area and connected to the plurality of electrostatic discharge circuits, configured to provide a second voltage signal, the second voltage signal being different from the first voltage signal; The at least one first voltage transmission line and the at least one second voltage transmission line are located in different conductive layers.

2. The display panel according to claim 1, characterized in that: The at least one first voltage transmission line is located on a side of the at least one second voltage transmission line away from the substrate; or, the at least one second voltage transmission line is located on a side of the at least one first voltage transmission line away from the substrate.

3. The display panel according to claim 2, characterized in that: The display panel at least comprises: a first source-drain metal layer and a second source-drain metal layer disposed on the substrate; the second source-drain metal layer is located on a side of the first source-drain metal layer away from the substrate; The at least one first voltage transmission line is located in the first source-drain metal layer, and the at least one second voltage transmission line is located in the second source-drain metal layer; or, the at least one second voltage transmission line is located in the first source-drain metal layer, and the at least one first voltage transmission line is located in the second source-drain metal layer.

4. The display panel according to claim 2, characterized in that: The display panel at least comprises: a first source-drain metal layer, a second source-drain metal layer and a third source-drain metal layer arranged on the substrate; the second source-drain metal layer is located on a side of the first source-drain metal layer away from the substrate, and the third source-drain metal layer is located on a side of the second source-drain metal layer away from the substrate; The at least one first voltage transmission line is located in the first source-drain metal layer or the second source-drain metal layer, and the at least one second voltage transmission line is located in the third source-drain metal layer; or, the at least one second voltage transmission line is located in the first source-drain metal layer or the second source-drain metal layer, and the at least one first voltage transmission line is located in the third source-drain metal layer.

5. The display panel according to claim 1, characterized in that: The display panel at least comprises: two first voltage transmission lines and one second voltage transmission line, the two first voltage transmission lines and the second voltage transmission line both extend along a second direction, the second voltage transmission line is located between the two first voltage transmission lines along the first direction; the second direction intersects the first direction; Alternatively, the display panel includes at least two second voltage transmission lines and one first voltage transmission line, the two second voltage transmission lines and the first voltage transmission line both extend along the second direction, and the first voltage transmission line is located between the two second voltage transmission lines along the first direction.

6. The display panel according to claim 5, characterized in that: The plurality of electrostatic discharge circuits are arranged in an array along the first direction and the second direction; The plurality of electrostatic discharge circuits are arranged in at least two rows along the first direction, and each row of electrostatic discharge circuits includes a plurality of electrostatic discharge circuits arranged along the second direction; Two rows of electrostatic discharge circuits are connected to the same first voltage transmission line or the same second voltage transmission line; The data lead-out lines connected to the first row of electrostatic discharge circuits and the data lead-out lines connected to the second row of electrostatic discharge circuits are located in different conductive layers.

7. The display panel according to claim 6, characterized in that: The electrostatic discharge circuit comprises: a first transistor, a second transistor, a third transistor and a fourth transistor; The first electrode of the first transistor is electrically connected to the second voltage transmission line, the gate and the second electrode of the first transistor are electrically connected to the first electrode of the second transistor, the gate and the second electrode of the second transistor are electrically connected to the first electrode of the third transistor and the data lead-out line, the gate and the second electrode of the third transistor are electrically connected to the first electrode of the fourth transistor, and the second electrode of the fourth transistor is electrically connected to the first voltage transmission line; The arrangement of the first transistor, the second transistor, the third transistor and the fourth transistor of the first row of electrostatic release circuits along the first direction is opposite to the arrangement of the first transistor, the second transistor, the third transistor and the fourth transistor of the second row of electrostatic release circuits along the first direction.

8. The display panel according to any one of claims 1 to 7, characterized in that: The display panel further includes: an organic planar layer, wherein the organic planar layer has an isolation groove surrounding the plurality of electrostatic discharge circuits in the first frame region; A first inorganic insulating layer, located on a side of the organic planar layer close to the substrate; A touch-control inorganic insulating layer, located on a side of the organic planar layer away from the substrate; The touch inorganic insulating layer contacts the first inorganic insulating layer through the isolation groove.

9. The display panel according to claim 8, characterized in that: The display panel further includes: A touch protection layer, located on a side of the touch inorganic insulating layer away from the substrate; The orthographic projection of the touch protection layer on the substrate covers the orthographic projections of the plurality of electrostatic discharge circuits on the substrate.

10. The display panel according to claim 8, characterized in that: The display panel further includes: A touch protection layer, located on a side of the touch inorganic insulating layer away from the substrate, the touch protection layer having a hollow area in the first frame area, the orthographic projection of the hollow area on the substrate covering the orthographic projection of the multiple electrostatic release circuits on the substrate; The metal covering layer is located on a side of the touch protection layer away from the substrate, and the metal covering layer fills the hollow area.

11. The display panel according to claim 1, characterized in that: The first border area includes: a first sub-area, a bending area and a second sub-area arranged in sequence along a first direction away from the display area; the multiple electrostatic release circuits, the at least one first voltage transmission line and the at least one second voltage transmission line are located in the second sub-area.

12. A display device, characterized in that: The invention comprises the display panel as claimed in any one of claims 1 to 11.

13. A display panel, characterized in that: include: A substrate, comprising: a display area, a first frame area located at one side of the display area along a first direction, the first frame area comprising: a first sub-area, a bending area, and a second sub-area arranged in sequence along the first direction away from the display area; A plurality of sub-pixels are arranged on one side of the substrate and located in the display area; a plurality of data lines, located in the display area, configured to provide data signals to the plurality of sub-pixels; A plurality of data lead-out lines, located in the first frame area and connected to the plurality of data lines; A plurality of electrostatic discharge circuits, located in the second sub-region of the first frame region and connected to the plurality of data lead-out lines; The organic planar layer has an isolation groove surrounding the multiple electrostatic discharge circuits in the second sub-region of the first frame region.

14. The display panel according to claim 13, characterized in that: The display panel further includes: A first inorganic insulating layer, located on a side of the organic planar layer close to the substrate; A touch-control inorganic insulating layer, located on a side of the organic planar layer away from the substrate; The touch inorganic insulating layer contacts the first inorganic insulating layer through the isolation groove.

15. The display panel according to claim 14, characterized in that: The display panel further includes: A touch protection layer, located on a side of the touch inorganic insulating layer away from the substrate, the touch protection layer having a hollow area in the second sub-area of ​​the first frame area, the orthographic projection of the hollow area on the substrate covering the orthographic projection of the multiple electrostatic release circuits on the substrate; The metal covering layer is located on a side of the touch protection layer away from the substrate, and the metal covering layer fills the hollow area.

Images