Mask and VCSEL chip
By designing a mask plate with multiple raised structures and bosses, the problem of difficulty in lithography of the P-type DBR layer with low internal resistance and good heat dissipation effect in the prior art is solved, and the performance improvement of the VCSEL chip is achieved.
Patent Information
- Application Number
- CN202422228743.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-11
- Publication Date
- 2025-05-13
- Estimated Expiration
- 2034-09-11
AI Technical Summary
The existing mask version is difficult to lithographically produce a P-type DBR layer that can reduce internal resistance of VCSEL chips and improve heat dissipation.
A mask plate is designed, including a substrate and a pattern layer, with multiple raised structures and bosses arranged away from the side of the substrate, and the desired structure is formed on the P-type DBR layer through etching technology.
It achieves better heat dissipation effect of VCSEL chips, while reducing the internal resistance of the chip.
Smart Images
Figure CN222867001U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of optical fiber communication and semiconductor lasers, and in particular to a mask plate and a VCSEL chip. Background Art
[0002] Common Metal Mask (CMM) plays the role of defining the panel AA area (active area) during the evaporation process and is widely used in AMOLED, PMOLED, micro OLED and other fields.
[0003] The mask plate includes a substrate with shading properties for exposure light, and a graphic metal layer located on the substrate, wherein the graphic metal layer includes at least one geometric figure with shading properties for exposure light, which can selectively block the light irradiated on the photoresist to form a pattern on the photoresist.
[0004] In the process of realizing the present invention, the inventor of the present invention found that: at present, photolithography is a crucial technology in semiconductor manufacturing technology, which can realize the transfer of patterns from the mask to the surface of the silicon wafer to form semiconductor products that meet the design requirements. It is difficult to photolithograph the P-type DBR layer that can reduce the internal resistance of the chip and ensure the heat dissipation effect with the current mask. Summary of the invention
[0005] In view of the above problems, the present invention is proposed to provide a mask and a VCSEL chip that overcome the above problems or at least partially solve the above problems.
[0006] In a first aspect, an embodiment of the utility model provides a mask for photolithography of a VCSEL chip, comprising:
[0007] A substrate and a pattern layer, wherein the pattern layer is arranged on one side of the substrate;
[0008] Wherein, a plurality of protruding structures are arranged on the side of the pattern layer away from the substrate, and the protruding structures are arranged in sequence and side by side along a straight line direction, and bosses are evenly arranged on the surfaces of the protruding structures.
[0009] Furthermore, the bosses are evenly arranged to terminate in sequence along the side straight lines of the protruding structure.
[0010] Furthermore, the protrusion height of the boss is controlled to be 1-1.5um. The height difference between the two side surfaces of two adjacent bosses which are parallel to the P-type DBR layer is 0.8-2um.
[0011] Furthermore, the boss includes a first side surface, and the first side surface and the substrate.
[0012] Furthermore, the distance between the protrusion structures is 0-1 um.
[0013] Furthermore, the transverse cross-section of the protrusion structure is triangular or trapezoidal.
[0014] Furthermore, the pattern layer is a film layer made of positive photoresist.
[0015] Furthermore, the substrate is a quartz plate.
[0016] The second aspect also discloses a VCSEL chip, comprising: prepared using any one of the mask plates described.
[0017] The beneficial effects of the above technical solution provided by the embodiment of the utility model at least include:
[0018] The utility model provides a mask in an embodiment, wherein a pattern layer is arranged above a substrate, and a plurality of raised structures are arranged on the side of the pattern layer away from the substrate, and the raised structures are arranged in a straight line in sequence and side by side, and bosses are evenly arranged on the surface of the raised structures. In this way, the raised structures of the pattern layer and the bosses on the raised structures can be etched to obtain the required structure on the P-type DBR layer through etching technology, so that the VCSEL chip has a better heat dissipation effect and reduces the internal resistance of the VCSEL chip.
[0019] Other features and advantages of the utility model will be described in the following description, and partly become apparent from the description, or understood by implementing the utility model. The purpose and other advantages of the utility model can be realized and obtained by the structures particularly pointed out in the written description and the drawings.
[0020] The technical solution of the utility model is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] In order to more clearly illustrate the specific implementation of the utility model or the technical solution in the prior art, the following is a brief introduction to the drawings required for the specific implementation or the prior art description. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, each element or part is not necessarily drawn according to the actual scale.
[0022] Figure 1 It is a structural schematic diagram of the mask of the first embodiment of the utility model;
[0023] Figure 2 This utility model Figure 1 A magnified schematic diagram;
[0024] Figure 3 This utility model Figure 1 Schematic diagram from another perspective;
[0025] Figure 4 This utility model Figure 3 B is an enlarged schematic diagram;
[0026] Figure 5 It is a structural schematic diagram of a mask plate of a second embodiment of the utility model;
[0027] Figure 6 This utility model Figure 5 Schematic diagram of C enlargement.
[0028] Indicated in the figure:
[0029] 10. substrate; 20. pattern layer; 200. raised structure; 201. boss. DETAILED DESCRIPTION
[0030] The following embodiments of the technical solution of the utility model are described in detail in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the utility model, and are therefore only used as examples, and cannot be used to limit the protection scope of the utility model.
[0031] It should be noted that, unless otherwise specified, the technical terms or scientific terms used in this application should have the common meanings understood by technicians in the field to which the utility model belongs.
[0032] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.
[0033] In addition, the terms "first", "second", etc. are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. In the description of the present utility model, "plurality" means more than two, unless otherwise clearly and specifically defined.
[0034] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this utility model can be understood according to specific circumstances.
[0035] In the present application, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.
[0036] High-speed modulated VCSEL is a hot topic in the industry. Currently, VCSEL with 25GHz bandwidth has been mass-produced, but further improving the modulation speed of VCSEL faces many challenges. If you want to further improve the modulation bandwidth of VCSEL, you need to consider two aspects: on the one hand, you need to further reduce the memory of such chips. It is difficult to further reduce the internal resistance of such chips using conventional designs to increase the modulation bandwidth; on the other hand, you need to further improve the heat dissipation performance of such devices. However, the current VCSEL chip structure cannot solve the problems of excessive internal resistance and poor heat dissipation at the same time, which restricts the development of high-speed modulated VCSEL.
[0037] Embodiment, photolithography is a crucial technology in semiconductor manufacturing technology. Photolithography can realize the transfer of graphics from the mask to the surface of the silicon wafer to form a semiconductor product that meets the design requirements. The photolithography process includes an exposure step, a development step performed after the exposure step, and an etching step after the development step. In the exposure step, light is irradiated onto the silicon wafer coated with photoresist through the light-transmitting area in the mask, and the photoresist undergoes a chemical reaction under the irradiation of light; in the development step, the different degrees of solubility of the photosensitive and non-photosensitive photoresists in the developer are used to form a photolithography pattern, and the mask pattern is transferred to the photoresist; in the etching step, the silicon wafer is etched based on the photolithography pattern formed by the photoresist layer, and the mask pattern is further transferred to the silicon wafer. The present utility model finds that it is difficult to etch the required P-type DBR layer with the current mask.
[0038] See attached Figure 1 As shown, the utility model provides a mask plate in an embodiment for VCSEL chip photolithography pattern, including:
[0039] A substrate 10 and a pattern layer 20, wherein the pattern layer 20 is disposed on one side of the substrate 10;
[0040] A plurality of protruding structures 200 are disposed on the side of the pattern layer 20 away from the substrate 10 , and the protruding structures 200 are arranged in sequence and side by side along a straight line, and bosses 201 are evenly disposed on the surface of the protruding structures 200 .
[0041] It is understandable that due to the current structure of the current high-speed modulated VCSEL chip, there are problems of large internal resistance and poor thermal effect. In order to be able to obtain a P-type DBR layer that can reduce the internal resistance and has a good heat dissipation effect when performing P-type DBR layer lithography for VCSEL chips. In an embodiment, a pattern layer 20 is arranged above the substrate 10, and a plurality of protruding structures 200 are arranged on the side of the pattern layer 20 away from the substrate 10, and the protruding structures 200 are arranged in sequence side by side in a straight line direction, and bosses 201 are evenly arranged on the surface of the protruding structures 200. In this way, the protruding structures 200 of the pattern layer 20 and the bosses 201 on the protruding structures 200 can be obtained by etching technology in the P-type DBR layer to obtain the required structure, so that the VCSEL chip has a better heat dissipation effect and reduces the internal resistance of the VCSEL chip.
[0042] When working in real time, when preparing a VCSEL chip, the mask is set on a photolithography machine to perform photolithography on the epitaxial wafer, and the pattern on the pattern layer 20 on the mask can be etched onto the epitaxial wafer to obtain the desired shape and pattern, so that the VCSEL chip prepared using the mask can achieve reduced internal resistance and better heat dissipation.
[0043] Since the pattern layer 20 of the mask is away from the side of the substrate 10, a plurality of raised structures 200 are provided, and the raised structures 200 are arranged in a straight line in sequence, and bosses 201 are evenly arranged on the surface of the raised structures 200. During photolithography, the thinner parts on the pattern layer 20 will disappear first, and then the other parts will gradually disappear, so that the pattern on the pattern layer 20 is photolithographically transferred to the epitaxial wafer, so that the outer surface of the P-type DBR layer has a stepped shape. The raised structure 200 is set as a structure with both sides gradually raised toward the center.
[0044] See attached Figure 2 As shown, in a further embodiment, the bosses 201 are evenly arranged along the side straight lines of the protruding structure 200 and are connected in sequence.
[0045] It can be understood that on the side of the protruding structure 200, the bosses 201 are sequentially arranged along the edge of the side, and the bosses 201 are arranged to be connected at the end, that is, by arranging the pattern layer 20 on the upper side of the substrate 10, the pattern layer 20 is arranged with multiple protruding structures 200. During photolithography, the protruding structure 200 is a gradually protruding structure, and the bosses 201 are evenly arranged on the protruding structure 200, so that when continuing the photolithography, a step structure can be effectively formed on the surface of the P-type DBR layer. To ensure the accuracy of photolithography, the step structure formed on the surface of the P-type DBR layer can effectively reduce the internal resistance of the chip as a whole and improve the efficiency of heat dissipation.
[0046] Refer to the attached Figure 4 As shown, in a further embodiment, the protrusion height of the boss 201 is controlled to be 1-1.5 um.
[0047] It can be understood that the height difference between the two sides of the two adjacent bosses 201 of the boss 201, which are respectively parallel to the substrate 10, is 0.8-2um. In the embodiment, by controlling the protrusion height of the boss 201, the structural height of the P-type DBR layer obtained during photolithography is achieved. It can also be considered that by controlling the height h of the boss 201, the height h of the step structure formed on the surface of the P-type DBR layer during photolithography can be achieved.
[0048] In some embodiments, the height of the boss 201 can be set according to the thickness of each layer in the P-type DBR layer obtained by epitaxial wafer growth. For example, when the thickness of each layer in the P-type DBR layer is 1 um, when the boss 201 of the mask is manufactured, the height of the boss 201 is set to 1 um; when the thickness of each layer in the P-type DBR layer is 2 um, when the boss 201 of the mask is manufactured, the height of the boss 201 is set to 2 um; when the thickness of each layer in the P-type DBR layer is 0.8 um, when the boss 201 of the mask is manufactured, the height of the boss 201 is set to 0.8 um.
[0049] Refer to the attached Figure 3 As shown, in a further embodiment, the boss 201 includes a first side surface, and the first side surface is connected to the substrate 10 .
[0050] In order to ensure the stepped shape of the P-type DBR layer of the VCSEL chip, so that the VCSEL chip as a whole obtains the desired structure, so that the overall internal resistance of the P-type DBR layer can be effectively reduced, and the heat dissipation effect will be better, in an embodiment, at least one first side surface is provided on the boss 201, and the first side surface is parallel to the substrate 10.
[0051] In the embodiment, the first side surface may be a plane or other planes. It can be understood that by setting the shape of the first side surface of the boss 201, the desired selection can be obtained on the P-type DBR layer during photolithography. For example, in the embodiment, the first side surface is set as a plane, and the first side surface is set parallel to the substrate 10. When the epitaxial wafer is photolithographically processed, a corresponding plane can be obtained on the P-type DBR layer.
[0052] Refer to the attached Figure 4 As shown, in a further embodiment, the distance h between the protrusion structures 200 is 0-1 um.
[0053] It can be understood that the distance between the protruding structures 200 can be considered as the distance between the closest positions of two protruding structures 200 that are close to each other. The distance can be 0, or the two can be separated by a certain distance.
[0054] In some embodiments, the distance between two adjacent protrusion structures 200 is set to 0, that is, the closest position between the two is in contact with each other; in other embodiments, the distance between two adjacent protrusion structures 200 is set to 0.5 um, that is, the closest position between the two is a certain distance; in still other embodiments, the distance between two adjacent protrusion structures 200 is set to 0.8 um, that is, the closest position between the two is a certain distance.
[0055] Refer to the attached Figure 3 and 5 As shown, in a further embodiment, the transverse cross-section of the protrusion structure 200 is triangular or trapezoidal.
[0056] It can be understood that the transverse cross section here can be considered as a cross section opposite to the end face of the protruding structure 200, or the protruding structure 200 can be considered as a structure extending along a direction, and the cross section here is a cross section perpendicular to the extending direction.
[0057] In one embodiment, the transverse cross section of the protruding structure 200 is set to a triangular structure, where the angle of the triangle can be rounded, and when performing photolithography, the pattern will show a phenomenon that the cross-sectional area of the triangle gradually decreases, or the cross-sectional area of the triangle is proportionally reduced; in another embodiment, the transverse cross section of the protruding structure 200 is set to a trapezoidal structure, where the angle of the trapezoid can be rounded, and when performing photolithography, the pattern will show a phenomenon that the cross-sectional area of the trapezoid gradually decreases. Of course, the protruding structure 200 can also be designed into other shapes according to the actual chip design requirements, which are not listed here one by one.
[0058] In a further embodiment, the pattern layer 20 is a film layer made of positive photoresist.
[0059] It can be understood that in order to ensure that the P-type DBR layer of the VCSEL chip can obtain a stepped shape, an embodiment is that a pattern layer 20 is made of a positive photoresist. During photolithography, the raised structure 200 on the pattern layer 20 is a gradually raised structure, and a boss 201 is provided on the raised structure 200. During photolithography, the pattern layer 20 made of the positive photoresist gradually disappears. The disappearance here starts from the part closest to the substrate 10 and gradually proceeds to the highest part of the boss 201 structure.
[0060] It should be noted that the characteristic of positive photoresist is that after the coating is exposed and developed, the exposed part is dissolved and the unexposed part remains. Therefore, when using positive photoresist for photolithography, the photoresist on the exposed part will gradually disappear, while the photoresist on the unexposed part will remain to form the desired image.
[0061] In a further embodiment, the substrate 10 is a quartz plate.
[0062] Based on the same utility model concept, a VCSEL chip is also disclosed, which is prepared using the mask.
[0063] By placing the mask on a photolithography machine to perform photolithography on an epitaxial wafer, the pattern on the pattern layer 20 on the mask can be etched onto the epitaxial wafer to obtain a desired shape and pattern, so that the VCSEL chip prepared using the mask can achieve reduced internal resistance and better heat dissipation.
[0064] For specific examples and descriptions of beneficial effects of the method described in this embodiment, reference may be made to the description of the saturable absorber described above, which will not be repeated here.
[0065] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. The present disclosure is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes may be made without departing from its scope. The scope of the present disclosure is limited only by the appended claims. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.
Claims
1. A mask for VCSEL chip lithography pattern, characterized in that: include: A substrate and a pattern layer, wherein the pattern layer is arranged on one side of the substrate; Wherein, a plurality of protruding structures are arranged on the side of the pattern layer away from the substrate, and the protruding structures are arranged in sequence and side by side along a straight line direction, and bosses are evenly arranged on the surfaces of the protruding structures.
2. The mask according to claim 1, characterized in that: The bosses are evenly arranged along the side straight lines of the protruding structures and are connected in sequence.
3. The mask according to claim 2, characterized in that: The protrusion height of the boss is controlled to be 1-1.5um; in two adjacent bosses, the height difference between the two side surfaces which are parallel to the P-type DBR layer is 0.8-2um.
4. The mask according to claim 2, characterized in that: The boss includes a first side surface and the substrate.
5. The mask according to claim 2, characterized in that: The distance between the protruding structures is 0-1um.
6. The mask according to any one of claims 2 to 5, characterized in that: The transverse cross-section of the protrusion structure is in the shape of a triangle or a trapezoid.
7. The mask according to claim 2, characterized in that: The pattern layer is a film layer made of positive photoresist.
8. The mask according to claim 1, characterized in that: The substrate is a quartz plate.
9. A VCSEL chip, characterized in that: include: The method is prepared by using the mask described in any one of claims 1 to 8.