Code receiving system and alarm system

Abstract

The utility model discloses a code receiving system and an alarm system, and the code receiving system comprises a host end code receiving circuit which comprises a short circuit detection circuit and a medium level control circuit; the short circuit detection circuit comprises a first sampling module and a signal output module, two ends of the first sampling module are respectively connected with a bus positive electrode connecting end and a bus positive electrode output end, the bus positive electrode connecting end is used for receiving a first power supply signal or a second power supply signal, and the first power supply signal is larger than the second power supply signal; the medium level control circuit is used for outputting a second power supply signal; the node end matching circuit comprises a first anti-reverse module and a power supply capacitor, the input end of the first anti-reverse module is connected with the bus anode output end, the output end of the first anti-reverse module is connected with the load connecting end, one end of the power supply capacitor is connected with the load connecting end, and the other end of the power supply capacitor is grounded; and after the power supply capacitor is fully charged, the voltage signal of the load connection end is greater than or equal to the first power signal minus the first anti-reverse module voltage drop. The code receiving system can avoid false alarm and missing alarm of short circuit detection.

Description

Technical Field

[0001] The utility model relates to the technical field of line detection, in particular to a code receiving system and an alarm system. Background Art

[0002] The fire alarm control system is a complex system that can simultaneously access more than a dozen node devices such as smoke sensors, temperature sensors, sound and light, manual alarm buttons, and fire hydrant buttons. The wiring method of each node device may also be different. Each building area has rigid requirements for meeting fire inspection and acceptance. For fire alarm system equipment installation projects, small projects need to install hundreds of node devices, and large projects need to install tens of thousands or hundreds of thousands of points. However, when the number of equipment installed is large, it is inevitable that there will be short circuits, circuit breaks, virtual grounding, and virtual connection equipment. These situations have added difficulties to the debugging of the fire alarm system. For loop line breaks, it is relatively easy to confirm. If the loop line is broken or the loop line is virtual at a certain position, when the host end of the fire alarm system registers the receiving point, it can only register the points with normal wiring. Then, by looking up the point map, which positions are not online, and the corresponding positions can be checked in a targeted manner to solve the line problem. Some loop lines have short circuits in the positive and negative poles. The on-site construction master can also use a multimeter to measure the resistance between the lines to determine whether the circuit is short-circuited. However, some virtual grounding situations cannot be measured using a multimeter, and most of the commissioning masters on site construction have no habit of checking the lines. They completely rely on the prompts on the host side. The construction masters will check the corresponding prompt circuit only after the fire alarm system detects the short circuit of the circuit and prompts on the screen. However, when the circuit line is virtual, the on-site equipment cannot work normally, and the host side cannot register the point information normally. For some complex lines, the short circuit detection system on the host side cannot detect it, resulting in a clueless system debugging, which seriously affects the debugging progress.

[0003] In addition, with the downturn in the manufacturing industry, all industries have begun to reduce costs and increase efficiency. For loop lines, many construction parties use multi-core cables in order to reduce construction costs, and the copper wires in the cores are thinner, resulting in increased resistance between wires when using wires of the same distance. When the equipment is installed far away, if the line is virtually grounded or short-circuited, the short-circuit current is greatly reduced due to the large resistance between the wires, and the fuse of the short-circuit protection system cannot be activated, increasing the difficulty of short-circuit detection. Therefore, the demand for detection lines that can prevent false alarms and missed alarms is imminent. Utility Model Content

[0004] The utility model provides a code receiving system and an alarm system. The code receiving system can avoid false alarms and missed alarms in short circuit detection, is suitable for various short circuit detections, enables a host end to correctly prompt line conditions, and greatly reduces the debugging burden.

[0005] In order to achieve the above object, the utility model provides the following technical solutions:

[0006] A code receiving system, comprising:

[0007] A host-side code receiving circuit includes a short-circuit detection circuit and a medium-level control circuit; the short-circuit detection circuit includes a first sampling module and a signal output module, the two ends of the first sampling module are respectively connected to the bus positive connection end and the bus positive output end, the bus positive connection end is used to receive a first power supply signal or a second power supply signal, the first power supply signal is greater than the second power supply signal, the signal output module is used to output a detection signal according to the signal on the first sampling module; the medium-level control circuit is used to output the second power supply signal according to the control signal;

[0008] The node-end matching circuit includes a first anti-reverse module and a power supply capacitor, wherein the input end of the first anti-reverse module is connected to the positive output end of the bus, the output end of the first anti-reverse module is connected to the load connection end, one end of the power supply capacitor is connected to the load connection end, and the other end is grounded, and when the power supply capacitor is fully charged, the voltage signal of the load connection end is greater than or equal to the first power supply signal minus the voltage drop of the first anti-reverse module.

[0009] Optionally, the short-circuit detection circuit further includes an overcurrent protector;

[0010] The first sampling module is connected to the positive output terminal of the bus through the overcurrent protector, and the overcurrent protector is used to increase resistance when the load line is short-circuited.

[0011] Optionally, the signal output module includes a first signal amplification unit and a voltage stabilization unit;

[0012] The input end of the first signal amplifying unit is connected to two ends of the first sampling module, and the output end of the first signal amplifying unit is connected to the detection signal output end;

[0013] The input end of the voltage stabilizing unit is connected to the output end of the first signal amplifying unit, and the output end of the voltage stabilizing unit is grounded.

[0014] Optionally, the medium-level control circuit includes a voltage dividing module, a voltage stabilizing module, a switch module and a second anti-reverse module;

[0015] The input end of the voltage divider module is connected to the power supply, the output end of the voltage divider module is connected to the input end of the voltage stabilizing module, and the output end of the voltage stabilizing module is grounded;

[0016] The input end of the switch module is connected to the output end of the voltage divider module, the output end of the switch module is connected to the input end of the second anti-reverse module, and the output end of the second anti-reverse module is connected to the positive electrode connection end of the bus;

[0017] The control end of the switch module is connected to the signal control end, and the signal control end is used to receive a switch control signal, and the switch control signal is used to adjust the on-off state of the switch module.

[0018] Optionally, the switch module includes a first switch unit and a second switch unit;

[0019] The input end of the first switch unit is connected to the output end of the voltage divider module, and the output end of the first switch unit is connected to the input end of the second anti-reverse module;

[0020] The input end of the second switch unit is connected to the control end of the first switch unit, the output end of the second switch unit is grounded, the control end of the second switch unit is connected to the signal control end, and the states of the first switch unit and the second switch unit are synchronized.

[0021] Optionally, the first switch unit includes a first switch tube, a first switch resistor and a second switch resistor;

[0022] The input end of the first switch tube is connected to the output end of the voltage divider module, the output end of the first switch tube is connected to the input end of the second anti-reverse module, the control end of the first switch tube is connected to the first end of the first switch short rent, the second end of the first switch resistor is connected to the input end of the switch unit, the first end of the second switch resistor is connected to the output end of the first switch tube, and the second end of the second switch resistor is connected to the control end of the second switch tube.

[0023] Optionally, the switch module further includes a common cathode diode;

[0024] The first input end of the common cathode diode is connected to the positive electrode connection end of the bus, and the output end of the common cathode diode is connected to the input end of the second switch unit;

[0025] The control end of the first switch unit is connected to the input end of the second switch unit through the first input end of the common cathode diode.

[0026] Optionally, the medium-level control circuit further includes a second sampling module, and the output end of the switch module is connected to the input end of the second anti-reverse module through the second sampling module;

[0027] The host-side code receiving circuit further includes a code receiving and analyzing module, an input end of the code receiving and analyzing module is connected to two ends of the second sampling module, and an output end of the code receiving and analyzing module is connected to a code receiving end;

[0028] The code receiving and analyzing module is used to output a load return code signal according to the signal on the second acquisition module.

[0029] Optionally, the code receiving and analyzing module includes a second signal amplifying unit, a third switching unit and a current limiting unit;

[0030] The input end of the second signal amplifying unit is connected to two ends of the second sampling module, and the output end of the second signal amplifying unit is connected to the control end of the third switch unit;

[0031] The input end of the third switch unit is connected to the code receiving end, the input end of the third switch unit is connected to the decoding power supply through the current limiting unit, and the output end of the third switch unit is grounded.

[0032] The utility model also provides an alarm system, comprising any one of the code receiving systems provided in the above technical solutions.

[0033] The embodiment of the utility model provides a code receiving system and an alarm system, in which the load connection end of the node end matching circuit in the code receiving system can be connected to the node device, and the line abnormality can be detected through the short-circuit detection circuit of the host end code receiving circuit; when the middle level control circuit does not output and the positive electrode connection end of the bus receives the first power supply signal, the signal output module can output the first detection signal according to the signal on the first sampling module, if there is no abnormality in the line, the line where the positive electrode connection end of the bus, the first sampling module, the first anti-reverse module and the load connection end are located is turned on, and the voltage at both ends of the first sampling module is small, and if the line is short-circuited, the voltage at both ends of the first sampling module increases sharply, and the conventional short-circuit situation can be detected according to the first detection signal; if it is necessary to detect whether there is a false alarm or missed alarm of a short circuit or virtual connection in the system line, the first circuit can be turned off. The source signal is not output, but the control signal is used to control the middle level control circuit, so that the middle level control circuit outputs the second power signal to the positive connection end of the bus. When the power supply capacitor is fully charged, the voltage signal of the load connection end is greater than or equal to the first power signal minus the voltage drop of the first anti-reverse module, and the first power signal is greater than the second power signal. At this time, under the action of the first anti-reverse module, the node device can be powered by the power supply capacitor. The signal output module can output the second detection signal according to the signal on the first sampling module. If there is no abnormality in the line, the line where the first sampling module, the positive connection end of the bus, the first sampling module, the first anti-reverse module, and the load connection end are located is not conductive. If the line is short-circuited or virtual connected, the loop has a certain leakage current, and the second detection signal is quite different from the detection signal when the line is normal. The above-mentioned code receiving system can avoid the situation of false alarm and missed alarm of short-circuit detection, and is suitable for various short-circuit detection, so that the host end can correctly prompt the line situation, which greatly reduces the debugging burden. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 A schematic diagram of the structure of a host-side code receiving circuit provided by an embodiment of the utility model;

[0035] Figure 2 A schematic diagram of the structure of a node end coordination circuit provided by an embodiment of the utility model;

[0036] Figure 3 A schematic diagram of the structure of a host-side code receiving circuit provided by an embodiment of the utility model;

[0037] Figure 4 A schematic diagram of the structure of a short circuit detection module provided by an embodiment of the utility model;

[0038] Figure 5 A schematic diagram of the structure of a medium-level control circuit provided by an embodiment of the utility model;

[0039] Figure 6A schematic diagram of the structure of a voltage dividing module and a voltage stabilizing module provided in an embodiment of the utility model;

[0040] Figure 7 A schematic diagram of the structure of a switch module and a second anti-reverse module provided in an embodiment of the utility model;

[0041] Figure 8 A schematic diagram of the structure of a code receiving and analyzing module and a response module provided in an embodiment of the utility model;

[0042] Fig. 9 A schematic diagram of the structure of a code receiving and parsing module provided in an embodiment of the utility model;

[0043] Fig.10 A schematic diagram of the structure of a code receiving system provided by an embodiment of the utility model;

[0044] Fig.11 A schematic diagram of the structure of a node coordination circuit provided by an embodiment of the utility model;

[0045] Fig.12 A control flow chart of a code receiving system provided in an embodiment of the utility model. DETAILED DESCRIPTION

[0046] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0047] The fire alarm control system can simultaneously access more than a dozen node devices such as smoke sensors, temperature sensors, sound and light sensors, manual alarm buttons, fire hydrant buttons, etc. The host end of the fire alarm system communicates with the node devices through two buses. The wiring method of each node device may also be different. When a large number of node devices are installed, line short circuits, open circuits, virtual grounding, and virtual connection of equipment are inevitable.

[0048] When registering receiving points on the host side of the fire alarm system, only the points with normal wiring can be registered. Then, by looking up the point map, you can find out which points are not online and solve the line problem by checking the corresponding positions in a targeted manner.

[0049] In the related technology, the host side will send communication instructions to the node device through the second bus. The host side will enter the receiving state for a period of time to receive the return code response of the node device, that is, the host code receiving circuit starts working. If there is no abnormality in the system line, the node device will respond with the return code according to the communication timing agreed with the host side. After the host code receiving circuit receives the response code of the node device, the host side registers the point where the upper wiring is normal.

[0050] However, when the loop line is loosely connected, the on-site node equipment cannot work normally, and the host side cannot register the point information normally. For some complex lines, the short-circuit detection system on the host side cannot detect them, resulting in false alarms and missed protection, which makes the system debugging clueless and seriously affects the debugging progress.

[0051] Among them, virtual connection of lines may include problems such as virtual grounding and virtual connection of equipment; virtual grounding refers to the virtual grounding of the positive line or negative line of the second bus; virtual connection of equipment refers to the poor contact of node equipment, which can sometimes be connected but sometimes cannot be connected.

[0052] In order to solve the above technical problems, the utility model provides a code receiving system, such as Figure 1 and Figure 2 As shown, including:

[0053] The host-side code receiving circuit 1 includes a short-circuit detection circuit 11 and a medium-level control circuit 12; the short-circuit detection circuit 11 includes a first sampling module 111 and a signal output module 112, the two ends of the first sampling module 111 are respectively connected to the bus positive connection terminal V_BUS and the bus positive output terminal BUS_P, the bus positive connection terminal V_BUS is used to receive a first power supply signal or a second power supply signal, the first power supply signal is greater than the second power supply signal, and the signal output module 112 is used to output a detection signal according to the signal on the first sampling module 111; the medium-level control circuit 12 is used to output the second power supply signal according to the control signal;

[0054] The node-end matching circuit 2 includes a first anti-reverse module 21 and a power supply capacitor C0, wherein the input end of the first anti-reverse module 21 is connected to the bus positive output end BUS_P, the output end of the first anti-reverse module 21 is connected to the load connection end V_OUT, one end of the power supply capacitor C0 is connected to the load connection end V_OUT, and the other end is grounded, and when the power supply capacitor C0 is fully charged, the voltage signal of the load connection end V_OUT is greater than or equal to the first power supply signal minus the voltage drop of the first anti-reverse module 21.

[0055] In the code receiving system provided by the embodiment of the utility model, the load connection terminal V_OUT of the node-side matching circuit 2 can be connected to the node device, and the line abnormality can be detected through the short-circuit detection circuit 11 of the host-side code receiving circuit 1; when the middle-level control circuit 12 does not output and the bus positive connection terminal V_BUS receives the first power signal, the signal output module 112 can output the first detection signal according to the signal on the first sampling module 111. If there is no abnormality in the line, the line where the bus positive connection terminal V_BUS, the first sampling module 111, the first anti-reverse module 21, and the load connection terminal V_OUT are located is turned on, and the voltage across the first sampling module 111 is small. If the line is short-circuited, the voltage across the first sampling module 111 increases sharply, and a conventional short circuit can be detected according to the first detection signal; if it is necessary to detect whether the system line has a short circuit, a false alarm, or a missed alarm, the first power signal output can be turned off, but The middle level control circuit 12 is controlled by the control signal, so that the middle level control circuit 12 outputs the second power signal to the positive connection terminal V_BUS of the bus. When the power supply capacitor C0 is fully charged, the voltage signal of the load connection terminal V_OUT is greater than or equal to the first power signal minus the voltage drop of the first anti-reverse module 21, and the first power signal is greater than the second power signal. At this time, under the action of the first anti-reverse module 21, the node device can be powered by the power supply capacitor C0. The signal output module 112 can output the second detection signal according to the signal on the first sampling module 111. If there is no abnormality in the line, the line where the first sampling module 111, the positive connection terminal V_BUS of the bus, the first sampling module 111, the first anti-reverse module 21, and the load connection terminal V_OUT are located is not conductive, and if there is a short circuit or virtual connection in the line, the loop has a certain leakage current, and the second detection signal is greatly different from the detection signal when the line is normal. The above-mentioned code receiving system can avoid the situation of false alarm and missed alarm of short circuit detection, and is suitable for various short circuit detection, so that the host end can correctly prompt the line situation, which greatly reduces the debugging burden.

[0056] Specifically, the first power signal is a bus positive power signal. Generally, the power supply V1 of the second bus is +24V, and the bus negative line is grounded. The second power signal is smaller than the first power signal, for example, 6.8V.

[0057] Specifically, the first sampling module 111 may be one first sampling resistor R0 or multiple first sampling resistors R0, which is not limited here and depends on the situation.

[0058] In the embodiment of the utility model, Figure 3As shown, the short circuit detection circuit 11 may also include an overcurrent protector 13; the first sampling module 111 is connected to the bus positive output terminal BUS_P through the overcurrent protector 13, and the overcurrent protector 13 is used to increase the resistance when the load line is short-circuited. Specifically, the overcurrent protector 13 may be an overcurrent protection resistor RT.

[0059] In the above-mentioned code receiving system, when the line is short-circuited, the loop current where the first sampling module 111 is located is relatively large, the voltage at both ends of the first sampling module 111 increases sharply, and the overcurrent protector 13 is actuated, causing its own resistance to increase sharply. Most of the voltage acts on both ends of the overcurrent protector 13, and the voltage of other circuit parts decreases, the total loop resistance increases greatly, and the short-circuit loop current decreases, thereby protecting devices and equipment from damage.

[0060] In actual applications, if the construction party uses low-quality wire materials in order to reduce costs, the resistance of the line in the loop will be relatively large. When a short circuit occurs at the far end, the short-circuit current is limited due to the influence of the line, which can easily lead to the short-circuit current failing to reach the action current of the overcurrent protector 13. At this time, the node device is powered by the bus positive power supply signal (first level signal), and the short-circuit detection circuit 11 is prone to false alarms and omissions when detecting the line.

[0061] In the embodiment of the utility model, the above-mentioned code receiving system can perform short circuit detection in two ways:

[0062] The first detection method is to first perform short circuit detection through the short circuit detection circuit 11 when the first power supply signal supplies power to the positive connection terminal V_BUS of the bus; if the output detection signal is abnormal, then switch to the medium level control circuit 12 to provide the second level signal to the positive connection terminal V_BUS of the bus. This detection method has a short detection cycle, and its purpose is to prevent the short circuit current from being large when the short circuit occurs. The medium level switching can be performed as soon as possible to reduce the voltage output, thereby reducing the short circuit current and protecting the system circuit. The code receiving system can detect the line through the first detection method at regular intervals. The second detection method is to switch the code receiving system to the situation where the medium level control circuit 12 supplies power and the power supply capacitor C0 is full. At this time, the short circuit detection circuit 11 is used to perform short circuit detection, which can prevent the virtual short circuit from being missed. When the line is virtual short, the short circuit current is small, and the fuse may not operate, or the first detection method may not meet the abnormal triggering conditions. The code receiving system can detect the line through the second detection method at regular intervals.

[0063] In the embodiment of the utility model, Figure 4 As shown, the signal output module 112 may include a first signal amplifying unit 1121 and a voltage stabilizing unit 1122;

[0064] The input end of the first signal amplifying unit 1121 is connected to the two ends of the first sampling module 111, and the output end of the first signal amplifying unit 1121 is connected to the detection signal output end BUS_AD; the input end of the voltage stabilizing unit 1122 is connected to the output end of the first signal amplifying unit 1121, and the output end of the voltage stabilizing unit 1122 is grounded. The voltage at the two ends of the first sampling module 111 can be amplified by the first signal amplifying unit 1121, which is convenient for signal collection; the voltage stabilizing unit 1122 can protect the detection signal output end BUS_AD from being damaged by high voltage.

[0065] Specifically, Figure 4 As shown, the first signal amplifying unit 1121 may include a first operational amplifier U1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4 and a fifth resistor R5; the positive input terminal of the first operational amplifier U1 may be connected to the input terminal of the first sampling module 111 through the first resistor R1, and grounded through the second resistor R2; the negative input terminal of the first operational amplifier U1 may be connected to the output terminal of the first sampling module 111 through the third resistor R3, and connected to the output terminal of the first operational amplifier U1 through the fourth resistor R4; the output terminal of the first operational amplifier U1 is connected to the input terminal of the fifth resistor R5, and the output terminal of the fifth resistor R5 is connected to the detection signal output terminal BUS_AD.

[0066] The amplification factor of the first operational amplifier U1 is A=R3 / R4, R1=R3, R2=R4; R5 is a discharge resistor, which can ensure that the detection signal output from the detection signal output terminal BUS_AD has no sampling waveform delay.

[0067] Specifically, Figure 4 As shown, the voltage stabilizing unit 1122 may include a first voltage stabilizing diode D1, the cathode of the first voltage stabilizing diode D1 is connected to the output end of the fifth resistor R5, and the anode of the first voltage stabilizing diode D1 is grounded. The first voltage stabilizing diode D1 can protect the detection signal output terminal BUS_AD from being damaged by high voltage. For example, when the voltage of the detection signal outputted from the output end of the first operational amplifier U1 is greater than 3.3V, the first voltage stabilizing diode D1 can clamp the voltage of the detection signal at 3.3V to protect the signal output terminal from being damaged by high voltage.

[0068] In the embodiment of the utility model, Figure 5As shown, the medium-level control circuit 12 may include a voltage divider module 121, a voltage stabilizing module 122, a switch module 123 and a second anti-reverse module 124; wherein, the input end of the voltage divider module 121 is connected to the power supply V1, the output end of the voltage divider module 121 is connected to the input end of the voltage stabilizing module 122, and the output end of the voltage stabilizing module 122 is grounded; the input end of the switch module 123 is connected to the output end of the voltage divider module 121, the output end of the switch module 123 is connected to the input end of the second anti-reverse module 124, and the output end of the second anti-reverse module 124 is connected to the bus positive connection end V_BUS; the control end of the switch module 123 is connected to the signal control end BUS_R / T, the signal control end BUS_R / T is used to receive a switch control signal, and the switch control signal is used to adjust the on-off state of the switch module 123.

[0069] The above-mentioned medium-level control circuit 12 can divide the power supply V1 through the voltage dividing module 121 . For example, the voltage of the power supply V1 can be +28V, and the power supply voltage can be divided through the voltage dividing module 121 .

[0070] Specifically, Figure 6 As shown, the voltage divider module 121 may include a first voltage divider resistor R12, a second voltage divider resistor R13 and a third voltage divider resistor R14, through which the power supply V1 may be voltage divided. The three resistors may be packaged in a large package to facilitate heat dissipation.

[0071] Specifically, Figure 6 As shown, the above-mentioned voltage stabilizing module 122 may include a first anti-reverse diode D2, a second voltage stabilizing diode D3, a first voltage stabilizing capacitor C1 and a second voltage stabilizing capacitor C2, the anode of the first anti-reverse diode D2 is connected to the output end of the voltage divider module 121, the cathode of the first anti-reverse diode D2 is connected to the cathode of the second voltage stabilizing diode D3, the anode of the second voltage stabilizing diode D3 is grounded, the first end of the first voltage stabilizing capacitor C1 is connected to the output end of the voltage divider module 121, the second end of the first voltage stabilizing capacitor C1 is grounded, the first end of the second voltage stabilizing diode D3 is connected to the output end of the voltage divider module 121, and the second end of the second voltage stabilizing diode D3 is connected to the output end of the voltage divider module 121.

[0072] For example, the second voltage stabilizing diode D3 can clamp the voltage at the anode terminal of the first anti-reverse diode D2 at a target value. For example, the target value can be 7.5V=6.8V (second power signal)+0.7V (voltage drop of the first anti-reverse diode D2).

[0073] The first voltage stabilizing capacitor C1 and the second voltage stabilizing capacitor C2 can play a role in voltage stabilization, ensuring that the positive terminal voltage output of the first anti-reverse diode D2 is stable.

[0074] In the embodiment of the utility model, Figure 7 As shown, the above-mentioned switch module 123 may include a first switch unit 1231 and a second switch unit 1232; wherein, the input end of the first switch unit 1231 is connected to the output end of the voltage divider module 121, and the output end of the first switch unit 1231 is connected to the input end of the second anti-reverse module 124; the input end of the second switch unit 1232 is connected to the control end of the first switch unit 1231, the output end of the second switch unit 1232 is grounded, the control end of the second switch unit 1232 is connected to the signal control end BUS_R / T, and the states of the first switch unit 1231 and the second switch unit 1232 are synchronized.

[0075] Specifically, when the second switch unit 1232 is not conducting, the first switch unit 1231 is not conducting, and the medium-level control circuit 12 does not supply power to the bus positive connection terminal V_BUS; when the bus positive power supply signal supplies power to the bus positive connection terminal V_BUS, the second anti-reverse diode D5 can prevent the components of the medium-level control circuit 12 from being damaged by high voltage;

[0076] When it is necessary to switch to the medium-level control circuit 12 to power the bus positive connection terminal V_BUS, the bus positive power signal can be controlled to be turned off to power the bus positive connection terminal V_BUS, and then the second switch unit 1232 is controlled to be turned on, and the first switch unit 1231 is turned on, and the medium-level control circuit 12 outputs the second power signal to power the bus positive connection terminal V_BUS.

[0077] Specifically, Figure 7 As shown, the first switch unit 1231 may include a first switch tube Q1, a first switch resistor R15 and a second switch resistor R16, the input end of the first switch tube Q1 is connected to the output end of the voltage divider module 121, the output end of the first switch tube Q1 is connected to the input end of the second anti-reverse module 124, the control end of the first switch tube Q1 is connected to the first end of the first switch resistor R15, the second end of the first switch resistor R15 is connected to the input end of the second switch unit 1232, the first end of the second switch resistor R16 is connected to the output end of the first switch tube Q1, and the second end of the second switch resistor R16 is connected to the control end of the second switch tube Q2.

[0078] Specifically, Figure 7 As shown, the second switch unit 1232 may include a third switch resistor R20 and a second switch tube Q2, the first end of the third switch resistor R20 is connected to the signal control end BUS_R / T, the second end of the third switch resistor R20 is connected to the control end of the second switch tube Q2, the input end of the second switch tube Q2 is connected to the second end of the first switch resistor R15, and the output end of the second switch tube Q2 is grounded.

[0079] The first switch tube Q1 and the second switch tube Q2 may be triodes. The second anti-reverse module 124 may be a second anti-reverse diode D5.

[0080] In the embodiment of the utility model, the control signal can be a low level or a high level. In the switch module 123, when the signal control terminal BUS_R / T receives a low level, the second switch tube Q2 is not turned on, and the voltage divider module 121, the second switch resistor R16, the first switch resistor R15, the second switch tube Q2, and the GND loop are not turned on. At this time, the voltages at both ends of the second switch resistor R16 are equal, and the first switch tube Q1 is not turned on, and the medium-level control circuit 12 does not supply power; and when the signal control terminal BUS_R / T receives a high level, the second switch tube Q2 is turned on, and the voltage divider module 121, the second switch resistor R16, the first switch resistor R15, the second switch tube Q2, and the GND loop form a path, and there is a voltage difference at both ends of the first switch resistor R15, then the first switch tube Q1 is turned on, and the medium-level control circuit 12 outputs a second power signal to the bus positive connection terminal V_BUS.

[0081] In the embodiment of the utility model, Figure 7 As shown, the switch module 123 may also include a common cathode diode D4; wherein the first input end of the common cathode diode D4 is connected to the bus positive connection end V_BUS, and the output end of the common cathode diode D4 is connected to the input end of the second switch unit 1232; the control end of the first switch unit 1231 is connected to the input end of the second switch unit 1232 through the first input end of the common cathode diode D4.

[0082] The first input end of the common cathode diode D4 may be connected to the bus positive electrode connection end V_BUS through the first current limiting resistor R17 and the second current limiting resistor R18.

[0083] Specifically, in the switch module 123, when the second switch tube Q2 is turned on, the first switch tube Q1 is turned on, and the voltage divider module 121, the second switch resistor R16, the first switch resistor R15, the common cathode diode D4, the second switch tube Q2, and the GND loop form a path; in addition, the bus positive connection terminal V_BUS, the first current limiting resistor R17, the second current limiting resistor R18, the common cathode diode D4, the second switch tube Q2, and the GND loop also form a path to form a discharge loop, which can ensure that when the signal received by the bus positive connection terminal V_BUS switches from the first power supply signal to the second power supply signal, there is no falling edge, a slow falling delay, and a delay waveform to ensure the communication timing.

[0084] In the embodiment of the utility model, Figure 7As shown, the medium-level control circuit 12 also includes a second sampling module 112, and the output end of the switch module 123 is connected to the input end of the second anti-reverse module through the second sampling module 112; the host-end code receiving circuit 1 also includes a code receiving analysis module 13, the input end of the code receiving analysis module 13 is connected to the two ends of the second sampling module 112, and the second end of the code receiving analysis module 13 is connected to the code receiving end BUS_R; the code receiving analysis module 13 is used to output a load return code signal according to the signal on the second acquisition module.

[0085] like Figure 8 As shown, the node device may have a response module 3, and the code receiving and analyzing module 13 may receive the communication timing sent by the response and analyzing module, and analyze the communication timing to output a load return code signal.

[0086] Specifically, the host end and the node device can agree on a communication timing, and the specific communication timing content is not limited here and is determined according to the actual situation; when the middle level control circuit 12 supplies power to the bus positive connection terminal V_BUS, and the voltage on the power supply capacitor C0 is less than the second power supply signal minus the voltage drop of the first anti-reverse module, the host end code receiving circuit 1 can communicate with the node device through the agreed communication timing, and the code receiving analysis module can analyze the signal on the second sampling module 112. If the line connection is normal, the load return code signal output by the code receiving analysis module is the agreed communication timing. If the line connection is abnormal, the code receiving analysis module cannot output the agreed communication timing, and the host end cannot realize the registration of the node device point. The code receiving system provided by the utility model can not only complete the two-bus code receiving decoding, but also perform loop line short circuit detection, and completely solve the problem of short circuit false alarm and missed alarm.

[0087] In the embodiment of the utility model, Fig. 9 As shown, the above-mentioned code receiving and parsing module 13 may include a second signal amplifying unit 131, a third switch unit 132 and a current limiting unit; wherein, the input end of the second signal amplifying unit 131 is connected to the two ends of the second sampling module 112, and the output end of the second signal amplifying unit 131 is connected to the control end of the third switch unit 132; the input end of the third switch unit 132 is connected to the code receiving end BUS_R, the input end of the third switch unit 132 is connected to the decoding power supply V2 through the current limiting unit, and the output end of the third switch unit 132 is grounded.

[0088] The decoding power supply V2 may be 3.3V.

[0089] Specifically, the above-mentioned code receiving and parsing module 13 can amplify the signal on the second sampling module 112 through the second signal amplifying unit 131. The host end and the node device agree on the communication timing. When the host end communicates with the node device, the node device will send a node return code response to the host end; if the node device sends a bit of 1, the conduction condition of the third switch unit 132 is not met. At this time, the code receiving end BUS_R receives a high level 1, that is, this bit is parsed as 1; and when the node device sends a bit of 0, the conduction condition of the third switch unit 132 is met, then the code receiving end BUS_R receives a low level 0, that is, this bit is parsed as 0.

[0090] Specifically, the second sampling module 112 may include a second sampling resistor R19 or may include a plurality of sampling resistors, which is not limited here and depends on actual conditions.

[0091] Specifically, Fig. 9 As shown, the second signal amplifying unit 131 may include a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10 and a second operational amplifier U2. The positive input terminal of the second operational amplifier U2 is connected to the input terminal of the second sampling module 112 through the sixth resistor R6 and is grounded through the seventh resistor R7. The negative input terminal of the second operational amplifier U2 is connected to the output terminal of the second sampling module 112 through the eighth resistor R8 and is connected to the output terminal of the second operational amplifier U2 through the ninth resistor R9. The positive power input terminal of the second operational amplifier U2 is connected to the power supply V1, the negative power input terminal of the second operational amplifier U2 is grounded, and the output terminal of the second operational amplifier U2 is connected to the control terminal of the third switch unit 132 through the tenth resistor R10.

[0092] Among them, the amplification factor B of the second signal amplification unit 131 can be B=R9 / R8, wherein R6=R8, R7=R9, and R10 is a discharge resistor, which can ensure that there is no delay when the high and low levels of the signal responded by the node device collected by the second sampling module 112 are switched, thereby preventing the receiving code analysis module 13 from decoding misjudgment.

[0093] Specifically, Fig. 9 As shown, the third switch unit 132 may include a third switch tube M1, a control end of the third switch tube M1 is connected to the output end of the tenth resistor R10, an input end of the third switch tube M1 is connected to the decoding power supply V2 through a current limiting unit, the input end of the third switch tube M1 is also connected to the receiving end BUS_R, and the output end of the third switch tube M1 is grounded.

[0094] The third switch tube M1 may be an NMOS tube; and the current limiting unit may be a third current limiting resistor R11.

[0095] In the above-mentioned code receiving and parsing module, when the node device end sends bit 1, the node device end does not draw current at this time, and there is almost no voltage at both ends of the second sampling resistor R19. After amplification, the voltage difference between the control end and the output end of the third switch tube M1 is small. At this time, the input end and the output end of the third switch tube M1 do not meet the conduction condition. At this time, the code receiving end BUS_R receives a high level 1, that is, this bit is parsed to 1; when the node device end sends bit 0, the node device end draws a certain current at this time. At this time, after the voltage at both ends of the second sampling resistor R19 is amplified, the voltage difference between the control end and the output end of the third switch tube M1 is large. At this time, the voltage difference between the input end and the output end of the third switch tube M1 meets the conduction condition, then the input end and the output end of the third switch tube M1 are connected to the ground, and the code receiving end BUS_R receives a low level 0, that is, this bit is parsed to 0.

[0096] In the embodiment of the utility model, the code receiving system further includes a control module, and three pins in the control module can be connected to the signal control terminal BUS_R / T, the detection signal output terminal BUS_AD, and the code receiving terminal BUS_R respectively. The control module can adjust the switching of the first power signal output and the second electrical signal output by outputting a control signal to the signal control terminal BUS_R / T, and receive the detection signal output by the detection signal output terminal BUS_AD and the load return signal received by the code receiving terminal BUS_R. The control module is a control chip, etc.

[0097] like Fig.10 The overall circuit diagram of the host-side code receiving circuit 1 provided in the embodiment of the utility model; Fig.11 This is a schematic diagram of the structure of the node end coordination circuit 2 provided in an embodiment of the present utility model.

[0098] Specifically, Fig.11 As shown, the first anti-reverse module 21 may include a fourth current limiting resistor R21 and a third anti-reverse diode D6, the first end of the fourth current limiting resistor R21 is connected to the bus positive output terminal BUS_P, the second end of the fourth current limiting resistor R21 is connected to the anode of the third anti-reverse diode D6, and the cathode of the third anti-reverse diode D6 is connected to the load connection terminal V_OUT.

[0099] like Fig.12 A control flow chart of a code receiving system provided in an embodiment of the utility model is provided. The embodiment of the present application is described in detail below in combination with the overall circuit diagram and the control flow chart.

[0100] S1201: the host sends a short circuit detection task instruction, the bus positive connection terminal V_BUS receives the first power signal, the middle level control circuit 12 prohibits output, and the detection signal output terminal BUS_AD outputs the first detection signal to detect whether the line is short-circuited; if the output first detection signal is not detected to be abnormal, step S1202 is performed; if the output first detection signal is detected to be abnormal, step S1203 is performed;

[0101] Among them, Fig.10 As shown, when there is current in the loop where the first sampling resistor R0 is located, the voltage across the first sampling resistor R0 is amplified by the first operational amplifier U1, and the amplification factor is A=R4 / R3, wherein R1=R3, R2=R4, and R5 is a bleeder resistor, which can ensure that the first detection signal output by the detection signal output terminal BUS_AD has no sampling waveform delay. When the voltage output by the output terminal of the first operational amplifier is greater than 3.3V, the first voltage regulator diode D1 can clamp the signal at 3.3V, protecting the sampling port connected to the control module and the detection signal output terminal BUS_AD from being damaged by high voltage.

[0102] S1202: Control the host end to enter the receiving state, and the receiving state short circuit detection task time is up;

[0103] Among them, the receiving state, that is, the host-side code receiving circuit 1 starts working, the bus positive connection terminal V_BUS voltage is switched to the second power supply signal (medium level), and then the node device and the host end agree on the communication timing. When the host end enters the receiving state, the node device that needs to respond sends the node device response timing;

[0104] S1203: Determine whether the receiving end BUS_R of the host-side receiving circuit 1 receives the arrival of the node device response sequence; if the node device response sequence is not received, it indicates that the line is faulty, and then proceed to step S1206; if the node device response sequence is received, then proceed to step S1204;

[0105] S1024: Wait for the host end to receive the node device response sequence to end;

[0106] When the host enters the receiving state, the first power signal is turned off and then the second power signal is switched to supply power. Fig.10As shown, the power supply V1+28V is used for power supply, the first voltage-dividing resistor R12, the second voltage-dividing resistor R13 and the second voltage-dividing resistor R13 in the voltage-dividing module 121 divide the voltage, and the second voltage-stabilizing diode D3 can clamp the voltage of the positive terminal of the first anti-reverse diode D2 at 7.5V=6.8V+0.7V (the voltage drop of the first anti-reverse diode D2). The first voltage-stabilizing capacitor C1 and the second voltage-stabilizing capacitor C2 are used for voltage stabilization to ensure that the positive terminal voltage output of the first anti-reverse diode D2 is stable; when the signal control terminal BUS_R / T is at a low level, the second switch tube Q2 is not turned on, and the route D2+, R16, R15, D4, Q2, and GND is not turned on. At this time, under the action of R16, the voltage of the control terminal of the first switch tube Q1 is equal to the voltage of the input terminal, then the first switch tube Q1 is not turned on, and the medium level is not output to the outside; and when When the signal control terminal BUS_R / T outputs a high level, the input and output ends of the second switch tube Q2 are connected to the ground, and the route of D2+, R16, R15, D4, Q2, and GND forms a path. The voltage across R16 is clamped at 0.7V due to the control end and input end of the first switch tube Q1, so the input and output ends of the first switch tube Q1 are connected, and the medium-level control circuit 12 outputs a second power supply signal. The voltage of the bus positive electrode connection terminal V_BUS can be 6.8V=7.5V-0.7V (the voltage drop of the second anti-reverse diode D5); the bus positive electrode connection terminal V_BUS and R17, R18, D20, Q6, and GND are another discharge circuit, ensuring that when the bus positive electrode connection terminal V_BUS switches from +24V to the medium level 6.8V, there is no falling edge, it falls slowly, and the waveform is delayed to ensure the communication timing.

[0107] When the node device is in the code receiving timing state, the node device will draw current in the middle level state, so no short circuit detection and judgment is performed at this time; because when the middle level (second power supply signal) is output, the current in the loop is limited, the three resistors R12, R13, and R14 are connected in parallel, and R19, R0, and RT are connected in series for voltage division, that is, the maximum current in the loop is limited to 28V / (R12 / 3+R19+R0+RT). This current is relatively small, and the overcurrent protector 13 will not act. Even if short circuit detection is not performed in the code receiving timing, the device components will not be burned out due to short circuit;

[0108] Among them, Fig.10As shown, the node device communicates with the host end through the agreed communication timing; when the node device end sends bit 1, the node end does not draw current at this time, and there is almost no voltage at both ends of the second sampling resistor R19. After amplification, the voltage at the control end of the third switch tube M1 is small. At this time, the voltage difference between the control end and the output end of the third switch tube M1 does not meet the conduction condition. At this time, the code receiving end BUS_R receives a high level 1, that is, this bit is interpreted as 1; when the node sends bit 0, the node device end draws a certain current at this time. At this time, after the voltage at both ends of the third switch tube M1 is amplified, the voltage at the control end of the third switch tube M1 is large. At this time, the voltage difference between the control end and the output end of the third switch tube M1 meets the conduction condition, then the input end and the output end of the third switch tube M1 are connected to the ground, and the code receiving end BUS_R receives a low level 0, that is, this bit is interpreted as 0, and the two-bus code receiving decoding can be realized.

[0109] S1025: Wait for a preset time to charge the power supply capacitor C0; if the power supply capacitor C0 is fully charged, proceed to step S1206; wherein the preset time may be 500ms;

[0110] S1206: Turn off the first power signal power supply, control the intermediate level control circuit 12 to supply power to the bus positive electrode connection terminal V_BUS, and the short circuit detection circuit 11 outputs a second detection signal;

[0111] S1207: Determine whether the second detection signal is abnormal; if the second detection signal is abnormal, proceed to step S1208; if the second detection signal is normal, end the detection;

[0112] S1208: Report a loop short circuit fault.

[0113] like Fig.10 and Fig.11As shown, when the host end is in a non-receiving state, the bus positive output terminal BUS_P voltage output is 24V, that is, the input voltage of each node device end is 24V, and the voltage drop of the third anti-reverse diode D6 is removed. The load connection terminal V_OUT voltage is maintained at about 23.3V. When the host end enters the node device power supply and switches to a medium level, the bus positive output terminal BUS_P voltage drops to a medium level of 6.8V, and the voltage of the power supply capacitor C0 when fully charged is 23.3V. Because of the effect of the third anti-reverse diode D6, the power supply capacitor C0 will not reversely supply power. When switching from the non-receiving state to the receiving state, the node device will not return the code to pull current, because the voltage supplied by the power supply capacitor C0 is greater than The voltage at the output end of the positive bus, so at this time, all node devices will not generate any current. Of course, this situation is not infinite. When the voltage of the power supply capacitor C0 drops below 6.8V, the node device will use medium-level charging to pull current. According to the formula C△U=I△t, the time when the node device does not use medium-level charging △t=C*(23.3V-6.8V) / I, C is the capacity of the power supply capacitor C0, and I is the current of the line when the power supply capacitor C0 is powered. The current loss at the node end is relatively small, so as long as the capacitance value of the power supply capacitor C0 is selected, it can be ensured that there is enough time for short-circuit detection without false alarm when the host end is in the receiving state.

[0114] When the host end switches from the non-receiving state to the receiving state, when the line is not short-circuited or virtually connected, there is no current in the loop where the first sampling resistor R0 is located, and the sampling value of the second detection signal is almost close to 0; when the loop line is short-circuited or the line is virtually grounded, the loop line has a certain leakage current, and the sampling value of the second detection signal is quite different from that of the normal line. Assuming the short-circuit leakage current is I1mA, the sampling value of the second detection signal can be AD_SAMPLE=I1*R0*(R79 / R74)*4096 / 3300. Therefore, by performing loop line detection in the receiving state of the non-node return code timing state, any abnormal short-circuit state of the line can be detected, the bus output can be turned off, and the line abnormality can be displayed on the host screen to remind the construction master to check the line. At the same time, when the power consumption of the loop node device suddenly increases, according to the same principle, in the receiving state, short circuit detection is performed. If the sampling value of the second sampling signal is close to 0, it means that the power consumption of the loop node device has increased rather than the line abnormality. If the sampling value of the second sampling signal changes greatly, it means that the line is abnormal, the bus output is turned off, and the line fault information is displayed on the host screen. Therefore, the code receiving system provided in this embodiment can prevent both missed reports and false reports, and completely solves the missed reports of virtual grounding of the line and false reports caused by a large number of devices and high power consumption.

[0115] The embodiment of the utility model further provides an alarm system, comprising any one of the code receiving systems provided in the above technical solution.

[0116] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A code receiving system, characterized in that: include: A host-side code receiving circuit includes a short-circuit detection circuit and a medium-level control circuit; the short-circuit detection circuit includes a first sampling module and a signal output module, the two ends of the first sampling module are respectively connected to the bus positive connection end and the bus positive output end, the bus positive connection end is used to receive a first power supply signal or a second power supply signal, the first power supply signal is greater than the second power supply signal, the signal output module is used to output a detection signal according to the signal on the first sampling module; the medium-level control circuit is used to output the second power supply signal according to the control signal; The node-end matching circuit includes a first anti-reverse module and a power supply capacitor, wherein the input end of the first anti-reverse module is connected to the positive output end of the bus, the output end of the first anti-reverse module is connected to the load connection end, one end of the power supply capacitor is connected to the load connection end, and the other end is grounded, and when the power supply capacitor is fully charged, the voltage signal of the load connection end is greater than or equal to the first power supply signal minus the voltage drop of the first anti-reverse module.

2. The code receiving system according to claim 1, characterized in that: The short circuit detection circuit also includes an overcurrent protector; The first sampling module is connected to the positive output terminal of the bus through the overcurrent protector, and the overcurrent protector is used to increase the resistance when the load line is short-circuited.

3. The code receiving system according to claim 1, characterized in that: The signal output module includes a first signal amplification unit and a voltage stabilization unit; The input end of the first signal amplifying unit is connected to two ends of the first sampling module, and the output end of the first signal amplifying unit is connected to the detection signal output end; The input end of the voltage stabilizing unit is connected to the output end of the first signal amplifying unit, and the output end of the voltage stabilizing unit is grounded.

4. The code receiving system according to any one of claims 1 to 3, characterized in that: The medium-level control circuit includes a voltage dividing module, a voltage stabilizing module, a switch module and a second anti-reverse module; The input end of the voltage divider module is connected to the power supply, the output end of the voltage divider module is connected to the input end of the voltage stabilizing module, and the output end of the voltage stabilizing module is grounded; The input end of the switch module is connected to the output end of the voltage divider module, the output end of the switch module is connected to the input end of the second anti-reverse module, and the output end of the second anti-reverse module is connected to the positive electrode connection end of the bus; The control end of the switch module is connected to the signal control end, and the signal control end is used to receive a switch control signal, and the switch control signal is used to adjust the on-off state of the switch module.

5. The code receiving system according to claim 4, characterized in that: The switch module includes a first switch unit and a second switch unit; The input end of the first switch unit is connected to the output end of the voltage divider module, and the output end of the first switch unit is connected to the input end of the second anti-reverse module; The input end of the second switch unit is connected to the control end of the first switch unit, the output end of the second switch unit is grounded, the control end of the second switch unit is connected to the signal control end, and the states of the first switch unit and the second switch unit are synchronized.

6. The code receiving system according to claim 5, characterized in that: The first switch unit includes a first switch tube, a first switch resistor and a second switch resistor; The input end of the first switch tube is connected to the output end of the voltage divider module, the output end of the first switch tube is connected to the input end of the second anti-reverse module, the control end of the first switch tube is connected to the first end of the first switch resistor, the second end of the first switch resistor is connected to the input end of the switch unit, the first end of the second switch resistor is connected to the output end of the first switch tube, and the second end of the second switch resistor is connected to the control end of the first switch tube.

7. The code receiving system according to claim 5, characterized in that: The switch module also includes a common cathode diode; The first input end of the common cathode diode is connected to the positive electrode connection end of the bus, and the output end of the common cathode diode is connected to the input end of the second switch unit; The control end of the first switch unit is connected to the input end of the second switch unit through the first input end of the common cathode diode.

8. The code receiving system according to claim 4, characterized in that: The medium level control circuit further includes a second sampling module, and the output end of the switch module is connected to the input end of the second anti-reverse module through the second sampling module; The host-side code receiving circuit further includes a code receiving and analyzing module, an input end of the code receiving and analyzing module is connected to two ends of the second sampling module, and an output end of the code receiving and analyzing module is connected to a code receiving end; The code receiving and analyzing module is used to output a load return code signal according to the signal on the second sampling module.

9. The code receiving system according to claim 8, characterized in that: The code receiving and analyzing module includes a second signal amplifying unit, a third switch unit and a current limiting unit; The input end of the second signal amplifying unit is connected to two ends of the second sampling module, and the output end of the second signal amplifying unit is connected to the control end of the third switch unit; The input end of the third switch unit is connected to the code receiving end, the input end of the third switch unit is connected to the decoding power supply through the current limiting unit, and the output end of the third switch unit is grounded.

10. An alarm system, characterized in that: The invention comprises a code receiving system as described in any one of claims 1 to 9.

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