PIP stacked packaging structure
By designing a PIP stacked packaging structure including the bottom carrier board and the top carrier board, using pads and hot balls to achieve electrical connection of the chip, and installing sealant and thermal grease on the carrier board, the problems of low yield and poor scalability of traditional PIP packaging products are solved, achieving more efficient testing and better product performance.
Patent Information
- Application Number
- CN202421535067.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-01
- Publication Date
- 2025-05-13
- Estimated Expiration
- 2034-07-01
AI Technical Summary
The yield rate of traditional PIP packaging products is affected by KGD. A single chip cannot be tested separately before packaging, the yield rate is limited, and the product is poor in scalability.
A PIP stacked packaging structure is designed, including a bottom carrier board and a top carrier board. The two are electrically connected by a pad. A first chip is provided on the bottom carrier board and a second chip is provided on the top carrier board. The electrical connection between the chips is achieved through a solder ball electrical connection, and sealant and thermally conductive silicone grease are provided on the carrier board to improve heat dissipation and protection effects.
By separately testing the top-layer carrier board and the bottom-layer carrier board, the test efficiency and product yield are improved, the heat dissipation effect and protection of the chip are increased, and the stability and scalability of the packaged products are improved.
Smart Images
Figure CN222867665U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductor device packaging, in particular to a PIP stacking packaging structure. Background Art
[0002] As people's requirements for the portability of electronic products are increasing, it is a well-known development trend for electronic products to be light, thin, short and small. The traditional single chip packaging technology can no longer meet the market demand for increasingly lightweight products.
[0003] The PIP (Package in Package) packaging series products are mainstream new products developed in response to the trend of the times. PiP is generally called stacked package, package in package, or device built-in device. The chip in the package is stacked on the substrate through gold wire bonding. The same stacking, the substrate between the two stacks is bonded by gold wire, and then the whole package is packaged into a component, which is PiP (device built-in device).
[0004] The yield rate of traditional PIP packaging products is affected by KGD. Single chips cannot be tested individually before packaging, which limits the yield rate. In addition, the chip and substrate are determined by the design service company. After the product is packaged, it cannot be partially upgraded. The upgrade requires replacing the substrate, and the product's scalability is poor. Utility Model Content
[0005] In order to solve the problems existing in the above-mentioned prior art, a PIP stacking packaging structure is provided. The technical solution adopted by the utility model to solve the technical problem is:
[0006] A PIP stacking package structure, comprising:
[0007] A bottom carrier and a top carrier, the upper surface of the bottom carrier contacts the lower surface of the top carrier, the upper surface of the bottom carrier and the lower surface of the top carrier are both provided with pads, the pads of the bottom carrier match the pads of the top carrier, the upper surface of the bottom carrier is provided with a groove, a first chip is provided in the groove, the first chip is electrically connected to the pads of the bottom carrier, the upper surface of the top carrier is provided with a second chip, the second chip is electrically connected to the pads of the top carrier;
[0008] The plastic cover is located above the top carrier plate and is fixedly connected to the upper surface of the top carrier plate.
[0009] Preferably, the pads of the bottom carrier board are electrically connected to the pads of the top carrier board via solder balls.
[0010] Preferably, a sealant is coated between the upper surface of the bottom carrier plate and the lower surface of the top carrier plate.
[0011] Preferably, the bottom carrier and the top carrier include HTG resin carriers.
[0012] Preferably, a via hole is provided on the top-layer carrier plate above the groove, a metal block is passed through and fixedly connected to the via hole, and the metal block matches the groove.
[0013] Preferably, the size of the metal block is larger than the size of the groove.
[0014] Preferably, the lower end of the metal block is fixedly connected with an extension plate after passing through the through hole, the size of the extension plate is larger than the size of the metal block, and the lower surface of the extension plate is in contact with the upper surface of the bottom carrier plate.
[0015] Preferably, a plurality of groups of card slots are spaced apart on the inner wall of the through hole, and a matching card block is fixedly connected to the side wall of the metal block. The card block is inserted into the card slot and is in close contact with the card slot.
[0016] Preferably, the cross-sections of the card block and the card slot include squares.
[0017] Preferably, the cross-section of the card block and the card slot comprises a semicircle.
[0018] Preferably, the second chip is fixedly disposed on the upper surface of the metal block, and an insulating coating is disposed between the second chip and the metal block.
[0019] Preferably, the thickness of the insulating coating is 3-4 μm.
[0020] Compared with the prior art, the beneficial effects of the utility model are:
[0021] 1. The utility model is provided with a top carrier board and a bottom carrier board, a first chip is provided on the bottom carrier board, the first chip is electrically connected to the bottom carrier board, a second chip is provided on the top carrier board, the second chip is electrically connected to the top carrier board, both the top carrier board and the bottom carrier board are provided with matching pads, the pads of the top carrier board and the bottom carrier board are electrically connected, so as to realize the electrical connection between the first chip and the second chip. When in use, after the first chip and the second chip are respectively arranged on the bottom carrier board and the top carrier board, the top carrier board and the bottom carrier board can be respectively subjected to relevant tests. After the test is passed, they are electrically connected through the pads between the top carrier board and the bottom carrier board, so as to effectively improve the test efficiency and improve the yield rate of the product.
[0022] 2. In the utility model, a groove is provided on the upper surface of the bottom carrier board, and the first chip is arranged in the groove. A via hole penetrating the top carrier board is provided on the top carrier board, and a metal block is passed through and fixedly connected in the via hole. Thermal conductive silicone grease is also provided in the groove, and the thermal conductive silicone grease is in contact with the first chip and the metal block respectively. Firstly, the heat conduction efficiency of the metal is better. By providing the thermal conductive silicone grease in the groove, the heat generated by the first chip is better conducted to the metal block, which is beneficial to the heat dissipation of the first chip; secondly, the metal block seals the first chip in the groove, and the thermal conductive silicone grease also has a certain buffering effect, which provides better protection for the first chip.
[0023] 3. In the utility model, a plurality of groups of card slots are arranged at intervals on the inner wall of the via hole, and a matching card block is fixedly connected to the side wall where the metal block contacts the via hole, and the card block is inserted into the card slot, and the card block is in close contact with the card slot. By setting the card block and the card slot, on the one hand, the contact area between the metal block and the via hole is effectively increased, and the roughness of the contact surface between the metal block and the via hole is increased, so that the connection between the metal block and the via hole is more firmly connected. In addition, the side wall of the metal block is fixedly connected with a matching card block. When the metal block is deformed by heat, a certain extension space is provided between adjacent card blocks for the heat deformation of the metal block, thereby avoiding irregular deformation of the metal block and the top carrier board, and improving the stability of the packaged product during use. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:
[0025] Figure 1 It is a sectional view of the overall structure of the utility model;
[0026] Figure 2 This is a cross-sectional view of the overall structure of the utility model (with an extension plate added);
[0027] Figure 3 It is a top view of the bottom carrier board;
[0028] Figure 4 This is a top view of the top carrier board (the card slot block is square);
[0029] Figure 5 yes Figure 4 A magnified view of the structure of part A;
[0030] Figure 6 This is a top view of the top carrier board (the card slot block is circular);
[0031] Figure 7 yes Figure 6 A magnified view of the structure of part B;
[0032] Description of reference numerals:
[0033] 100 bottom carrier board; 101 solder pad; 102 groove; 103 first chip; 104 solder ball; 105 sealant; 106 thermal grease; 107 through hole; 110 top carrier board; 111 second chip; 112 via hole; 113 metal block; 114 extension board; 115 card slot; 116 card block; 117 insulation coating; 120 plastic cover. DETAILED DESCRIPTION
[0034] The embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.
[0035] like Figure 1-Figure 3 As shown, the utility model proposes a PIP stacking packaging structure, which includes:
[0036] A bottom carrier board 100 and a top carrier board 110, the upper surface of the bottom carrier board 100 contacts the lower surface of the top carrier board 110, the upper surface of the bottom carrier board 100 and the lower surface of the top carrier board 110 are both provided with pads 101, the pads 101 of the bottom carrier board 100 match the pads 101 of the top carrier board 110, a groove 102 is provided on the upper surface of the bottom carrier board 100, a first chip 103 is provided in the groove 102, the first chip 103 is electrically connected to the pads 101 of the bottom carrier board 100, a second chip 111 is provided on the upper surface of the top carrier board 110, and the second chip 111 is electrically connected to the pads 101 of the top carrier board 110;
[0037] The plastic cover 120 is located above the top carrier board 110 and is fixedly connected to the upper surface of the top carrier board 110 .
[0038] Furthermore, the pads 101 of the bottom substrate 100 are electrically connected to the pads 101 of the top substrate 110 via solder balls 104 .
[0039] Furthermore, a sealant 105 is coated between the upper surface of the bottom carrier 100 and the lower surface of the top carrier 110 .
[0040] Furthermore, the bottom carrier 100 and the top carrier 110 include HTG resin carriers.
[0041] It should be specially noted that, in the present embodiment, pads 101 are also provided on the lower surface of the bottom substrate 100 and the upper surface of the top substrate 110, wherein the second chip 111 is electrically connected to the pads 101 on the upper surface of the top substrate 110 by means of gold wire bonding or the like, and the pads 101 on the lower surface of the bottom substrate 100 are used to be electrically connected to an external circuit such as a PCB board, that is, after the packaged product is formed, the pads 101 on the lower surface of the bottom substrate 100 are exposed, and the packaged product is connected to the external circuit via the pads 101 on the lower surface of the bottom substrate 100.
[0042] The pads 101 on the upper surface of the bottom substrate 100 and the lower surface of the top substrate 110 are arranged in the same manner. When the upper surface of the bottom substrate 100 contacts the lower surface of the top substrate 110, the pads 101 on the upper surface of the bottom substrate 100 correspond to the pads 101 on the lower surface and contact each other.
[0043] Applying sealant 105 between the upper surface of the bottom carrier 100 and the lower surface of the top carrier 110 can effectively improve the sealing performance and the connection quality between the bottom carrier 100 and the top carrier 110. In this embodiment, sealant 105 is applied on the upper surface of the bottom carrier 100 and the periphery of the lower surface of the top carrier 110.
[0044] When performing the initial chip design, it is necessary to design the correspondence between the pads 101 on the upper and lower surfaces of the top substrate 110, the correspondence between the pads 101 on the upper and lower surfaces of the bottom substrate 100, the correspondence between the lower surface of the top substrate 110 and the upper surface of the bottom substrate 100, the pins of the second chip 111 and the pads 101 on the upper surface of the top substrate 110, and the correspondence between the first chip 103 and the pads 101 on the upper surface of the bottom substrate 100.
[0045] It should be noted that, according to design requirements, the bottom substrate 100 and the top substrate 110 may be provided with a through hole 107 penetrating the substrate, and the inside of the through hole 107 is tin-plated so as to be conductive. Figure 1 and Figure 2 As shown, some pads 101 on the upper and lower surfaces of the bottom substrate 100 and the top substrate 110 are provided with via holes 107 penetrating the substrates, and electrical connections are made through the via holes 107, thereby realizing the supply of power to the chip or the introduction and extraction of electrical signals. The design of the corresponding relationship of the pads 101 belongs to the conventional process of chip design, and the setting of the via holes 107 belongs to the prior art, which will not be described in detail in this embodiment.
[0046] Taking the second chip 111 as a DRAM memory chip and the first chip 103 as a logic chip as an example, the specific use process is described:
[0047] First, the second chip 111 is fixedly set on the upper surface of the top substrate 110, and the pins of the second chip 111 are electrically connected to the pads 101 on the upper surface of the top substrate 110 according to a designed correspondence through gold wire bonding or the like; the first chip 103 is set in the groove 102, and the pins of the first chip 103 are electrically connected to the pads 101 on the upper surface of the bottom substrate 100 according to a designed correspondence through gold wire bonding or the like.
[0048] Afterwards, the top substrate 110 and the bottom substrate 100 are respectively tested for related electrical connections and chip logic functions, and unqualified top substrates 110 and bottom substrates 100 are eliminated, and qualified parts are retained. Through this separate testing method, unqualified parts can be quickly and effectively eliminated, which is beneficial to improving the test efficiency and the yield rate of packaged products.
[0049] Then, solder balls 104 are set on the soldering pads 101 on the lower surface of the top substrate 110 or the soldering pads 101 on the upper surface of the bottom substrate 100, and the upper surface of the top substrate 110 that has passed the test is brought into contact with the lower surface of the bottom substrate 100 that has passed the test. Under the action of the solder balls 104, the electrical connection between the top substrate 110 and the bottom substrate 100 is achieved. The method of using the solder balls 104 for electrical connection belongs to the prior art and will not be described in detail in this embodiment.
[0050] Finally, the upper surface of the top carrier board 110 is plastic-sealed to form a plastic cover 120 , and then cut to form a single packaged product.
[0051] After the top substrate 110 is electrically connected to the bottom substrate 100, the top substrate 110 covers the groove 102. At this time, the first chip 103 is in a closed space. The top substrate 110 and the groove 102 together protect the first chip 103. In addition, the plastic cover 120 also protects the second chip 111.
[0052] In addition, since the first chip 103 and the second chip 111 are respectively arranged on different carriers, their testing and local upgrades are very convenient. For example, in this embodiment, the combination and supplier of the storage chip corresponding to the first chip 103 and the logic chip corresponding to the second chip 111 can be freely selected, which is also convenient for replacement, thereby facilitating flexible design and upgrade of the product.
[0053] like Figure 1 and Figure 2 As shown, in one embodiment of the PIP stacking packaging structure of the present utility model,
[0054] Furthermore, a via hole 112 is provided on the top carrier board 110 above the groove 102 , and a metal block 113 is passed through and fixedly connected in the via hole 112 , and the metal block 113 matches the groove 102 .
[0055] Furthermore, the second chip 111 is fixedly disposed on the upper surface of the metal block 113 , and an insulating coating 117 is disposed between the second chip 111 and the metal block 113 .
[0056] Furthermore, the thickness of the insulating coating 117 is comprised between 3 and 4 μm.
[0057] In this embodiment, the metal block 113 is a finely machined metal block, and its processing technology belongs to the prior art, which will not be described in detail in this embodiment.
[0058] The second chip 111 is arranged on the upper surface of the metal block 113. The metal material has better thermal conductivity and better heat conduction efficiency, which is more conducive to the heat dissipation of the second chip 111. The insulating coating 117 is used to achieve insulation between the second chip 111 and the metal block 113 to ensure the safety of the second chip 111 during operation.
[0059] Please refer to Figure 1 Furthermore, the size of the metal block 113 is larger than the size of the groove 102 .
[0060] In this embodiment, the size of the metal block 113 is larger than the size of the groove 102. When the top carrier 110 is covered on the bottom carrier 100, a portion of the lower surface of the metal block 113 contacts the upper surface of the bottom carrier 100. The bottom carrier 100 also supports the metal block 113, making the connection between the metal block 113 and the groove 102 more stable.
[0061] Please refer to Figure 2 Furthermore, the lower end of the metal block 113 passes through the through hole 112 and is fixedly connected to an extension plate 114 . The size of the extension plate 114 is larger than that of the metal block 113 , and the lower surface of the extension plate 114 contacts the upper surface of the bottom carrier board 100 .
[0062] In this embodiment, since the size of the extension plate 114 is larger than that of the metal block 113, when the top carrier plate 110 is covered on the bottom carrier plate 100, a portion of the lower surface of the extension plate 114 contacts the upper surface of the bottom carrier plate 100, and the bottom carrier plate 100 also supports the metal block 113, making the connection between the metal block 113 and the groove 102 more stable.
[0063] The metal block 113 cooperates with the groove 102 to protect the first chip 103. In addition, the metal material has a better thermal conductivity and a better heat conduction efficiency, which is beneficial to the heat dissipation of the first chip 103. In addition, it should be specially noted that a thermal grease 106 is also provided in the groove 102. The thermal grease 106 is in contact with the first chip 103 and the metal block 113 respectively. By providing the thermal grease in the groove 102, the heat generated by the first chip 103 is better conducted to the metal block 113, which is beneficial to the heat dissipation of the first chip; secondly, the metal block 113 seals the first chip 103 in the groove 102, and the thermal grease 106 also has a certain buffering effect, which better protects the first chip 103.
[0064] like Figure 4-Figure 7 As shown, in one embodiment of the PIP stacking packaging structure of the present utility model,
[0065] Furthermore, a plurality of groups of slots 115 are spaced apart on the inner wall of the via hole 112 , and a matching block 116 is fixedly connected to the side wall of the metal block 113 . The block 116 penetrates the slot 115 , and the block 116 is in close contact with the slot 115 .
[0066] Please refer to Figure 4 and Figure 5 Furthermore, the cross-section of the card block 116 and the card slot 115 includes a square.
[0067] Please refer to Figure 6 and Figure 7 Furthermore, the cross-section of the card block 116 and the card slot 115 includes a semicircle.
[0068] In this embodiment, a plurality of groups of card grooves 115 are provided on the inner wall of the via hole 112, and a matching card block 116 is fixedly connected to the side wall where the metal block 113 contacts the via hole 112, thereby effectively improving the roughness of the side wall of the metal block 113 and the inner wall of the via hole 112. When the card block 116 is inserted into the card groove 115, it is also beneficial to improve the roughness of the metal block 113 and the via hole 112. Of course, sealant can also be applied simultaneously between the side wall of the metal block 113 and the inner wall of the via hole 112 and between the card block 116 and the card groove 115, thereby making the connection between the metal block 113 and the via hole 112 more stable.
[0069] In addition, a plurality of groups of card blocks 116 are arranged on the side wall of the metal block 113. When the metal block 113 is deformed by heat, a certain extension space is provided between adjacent card blocks 116 for the metal block 113 to be deformed by heat, thereby avoiding irregular deformation between the metal block 113 and the top carrier board 110 and improving the stability of the packaged product during use.
[0070] When in use, the metal block 113 is first inserted into the through hole 112, and the clamping block 116 on the side wall of the metal block 113 is inserted into the clamping groove 115 on the inner wall of the through hole 112. With the cooperation of the clamping block 116 and the clamping groove 115, the metal block 113 and the through hole 112 are fixed.
[0071] Afterwards, the second chip 111 is fixed on the upper surface of the top substrate 110, and the pins of the second chip 111 are electrically connected to the pads 101 on the upper surface of the top substrate 110; the first chip 103 is set in the groove 102, and the pins of the first chip 103 are electrically connected to the pads 101 on the upper surface of the bottom substrate 100.
[0072] Then, the top substrate 110 and the bottom substrate 100 are respectively tested for related electrical connection and chip logic function, and unqualified top substrates 110 and bottom substrates 100 are eliminated, and the qualified parts are retained. Upper solder balls 104 are set on the solder pads 101 on the lower surface of the top substrate 110 or the solder pads 101 on the upper surface of the bottom substrate 100, and the upper surface of the top substrate 110 that has passed the test is brought into contact with the lower surface of the bottom substrate 100 that has passed the test. Under the action of the solder balls 104, the electrical connection between the top substrate 110 and the bottom substrate 100 is achieved.
[0073] Finally, the upper surface of the top carrier board 110 is plastic-sealed to form a plastic cover 120 , and then cut to form a single packaged product.
[0074] Although the embodiments of the present invention have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.
Claims
1. A PIP stacking packaging structure, characterized in that: It includes: A bottom carrier (100) and a top carrier (110), wherein the upper surface of the bottom carrier (100) contacts the lower surface of the top carrier (110), the upper surface of the bottom carrier (100) and the lower surface of the top carrier (110) are both provided with solder pads (101), the solder pads (101) of the bottom carrier (100) match the solder pads (101) of the top carrier (110), the upper surface of the bottom carrier (100) is provided with a groove (102), a first chip (103) is provided in the groove (102), the first chip (103) is electrically connected to the solder pads (101) of the bottom carrier (100), and the upper surface of the top carrier (110) is provided with a second chip (111), the second chip (111) is electrically connected to the solder pads (101) of the top carrier (110); A plastic cover (120), wherein the plastic cover (120) is located above the top carrier plate (110) and is fixedly connected to the upper surface of the top carrier plate (110).
2. The PIP stacked package structure according to claim 1, characterized in that: The solder pad (101) of the bottom carrier board (100) is electrically connected to the solder pad (101) of the top carrier board (110) via solder balls (104).
3. The PIP stacked package structure according to claim 1, characterized in that: The bottom carrier (100) and the top carrier (110) include HTG resin carriers.
4. The PIP stacked package structure according to claim 1, characterized in that: A via hole (112) is provided on the top carrier plate (110) above the groove (102), a metal block (113) is passed through and fixedly connected to the via hole (112), and the metal block (113) matches the groove (102).
5. The PIP stacked package structure according to claim 4, characterized in that: The size of the metal block (113) is larger than the size of the groove (102).
6. The PIP stacked package structure according to claim 4, characterized in that: The lower end of the metal block (113) passes through the through hole (112) and is fixedly connected to an extension plate (114); the size of the extension plate (114) is larger than the size of the metal block (113); and the lower surface of the extension plate (114) is in contact with the upper surface of the bottom carrier plate (100).
7. The PIP stacked package structure according to claim 4, characterized in that: A plurality of groups of card slots (115) are arranged at intervals on the inner wall of the through hole (112); a matching card block (116) is fixedly connected to the side wall of the metal block (113); the card block (116) is inserted into the card slot (115); and the card block (116) is in close contact with the card slot (115).
8. The PIP stacked package structure according to claim 7, characterized in that: The cross-sections of the clamping block (116) and the clamping slot (115) include a square.
9. The PIP stacked package structure according to claim 7, characterized in that: The cross-sections of the clamping block (116) and the clamping slot (115) include semicircular shapes.
10. The PIP stacked package structure according to claim 4, characterized in that: The second chip (111) is fixedly arranged on the upper surface of the metal block (113), and an insulating coating (117) is arranged between the second chip (111) and the metal block (113).