Chip flip packaging fan-out structure

Abstract

The utility model discloses a flip chip packaging fan-out structure, which comprises a glass substrate, a rewiring layer, a chip, a protective layer, a passivation layer and solder, and is characterized in that the rewiring layer is arranged on the glass substrate; the chip is connected with the rewiring layer; the protective layer wraps the chip and is located between the chip and the rewiring layer; the passivation layer is connected with the glass substrate and is arranged on the surface of the rewiring layer; the solder is connected with the rewiring layer and is partially exposed. The glass chip of the flip chip packaging fan-out structure is packaged in the protection layer, the passivation layer can protect the re-wiring layer and the protection layer at the same time, and a chip circuit is led out sequentially through the re-wiring layer and the solder, so that the glass substrate does not need to be provided with a groove for mounting the chip, the thickness of the glass substrate is reduced, the product size is reduced, and the production cost is reduced. And the packaging process is simplified.

Description

Technical Field

[0001] The utility model relates to the field of chip packaging, in particular to a chip flip package fan-out structure. Background Art

[0002] In the flip-chip fan-out structure, the electrical surface faces downward, opposite to the connection surface of the glass substrate. The existing flip-chip fan-out structure usually packages the chip inside the glass substrate or between the glass substrates, so that the thickness of the glass substrate or the spacing between the glass substrates is large, making the overall volume of the product larger; at the same time, when encapsulating inside the glass substrate, it is necessary to open a groove on the glass substrate, and the process is more complicated.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0004] 1. Technical issues to be resolved

[0005] The utility model provides a chip flip package fan-out structure, which at least solves the technical problem of how to reduce the volume of the product and simplify the process.

[0006] (II) Technical solution

[0007] In order to solve the above technical problems, the utility model provides the following technical solutions:

[0008] A chip flip package fan-out structure, comprising:

[0009] Glass substrate;

[0010] A redistribution layer is disposed on the glass substrate;

[0011] A chip connected to the rewiring layer;

[0012] A protection layer, the protection layer surrounds the chip and is located between the chip and the rewiring layer;

[0013] A passivation layer connected to the glass substrate and disposed on a surface of the rewiring layer;

[0014] Solder is connected to the redistribution layer and is partially exposed.

[0015] In some embodiments, the chip is located in the middle of one of the surfaces of the glass substrate.

[0016] In some embodiments, the chip and the protection layer are located between the solders.

[0017] In some embodiments, the protection layer covers the side surfaces of the chip and the end surface close to the glass substrate.

[0018] In some embodiments, the chip and the redistribution layer are connected via micro bumps.

[0019] In some embodiments, the micro-bumps are made of copper.

[0020] (III) Beneficial effects

[0021] Compared with the prior art, the chip flip package fan-out structure provided by the utility model has the following beneficial effects:

[0022] The glass chip of the chip flip-package fan-out structure is encapsulated inside the protective layer. The passivation layer can protect the rewiring layer and the protective layer at the same time. The chip circuit is led outward through the rewiring layer and solder in turn. In this way, the glass substrate does not need to have grooves to install the chip, which is conducive to reducing the thickness of the glass substrate, reducing the product volume, and simplifying the packaging process. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 Schematic diagram of a chip flip package fan-out structure in an embodiment.

[0024] Reference numerals: glass substrate 1 , redistribution layer 2 , chip 3 , protective layer 4 , passivation layer 5 , solder 6 , micro bumps 7 . DETAILED DESCRIPTION

[0025] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0026] The thickness of the glass substrate or the spacing between the glass substrates of the existing chip flip package fan-out structure is relatively large, which makes the overall volume of the product larger; at the same time, when encapsulating inside the glass substrate, it is necessary to open a groove on the glass substrate, and the process is relatively complicated.

[0027] To solve the above technical problems, this embodiment provides a chip flip package fan-out structure, please refer to Figure 1 As shown, Figure 1 Schematic diagram of a chip flip package fan-out structure in an embodiment.

[0028] The chip flip package fan-out structure of this embodiment includes: a glass substrate 1, a redistribution layer 2, a chip 3, a protection layer 4, a passivation layer 5 and solder 6.

[0029] The redistribution layer 2 is disposed on the glass substrate 1 .

[0030] The above-mentioned redistribution layer 2 can be arranged on the glass substrate 1 by connecting with the connection points on the glass substrate 1. According to the position of the redistribution bumps, the redistribution layer 2 can be divided into two types: fan-in type and fan-out type. The fan-in type package concentrates the circuits inside the chip and is mainly used in low I / O node number and smaller bare chip process.

[0031] The chip 3 is connected to the rewiring layer 2 .

[0032] The chip 3 leads out the circuit through the rewiring layer 2 .

[0033] The protection layer 4 surrounds the chip 3 and is located between the chip 3 and the rewiring layer 2 .

[0034] The protective layer 4 may be made of an insulating material that is waterproof and airtight to provide physical protection for the chip 3 .

[0035] The passivation layer 5 is connected to the glass substrate 1 and is provided on the surface of the rewiring layer 2 .

[0036] The passivation layer 5 is used to protect the redistribution layer 2 and the chip 3 from the external environment, and can be made of glass, silicon nitride or other materials.

[0037] The solder 6 is connected to the redistribution layer 2 and is partially exposed.

[0038] The solder 6 is used to solder the redistribution layer 2 to corresponding solder joints on the external circuit substrate to achieve electrical connection.

[0039] The chip flip package fan-out structure of the above technical solution encapsulates the glass chip 3 inside the protective layer 4. The passivation layer 5 can protect the rewiring layer 2 and the protective layer 4 at the same time. The chip 3 circuit is led outward through the rewiring layer 2 and the solder 6 in turn. In this way, the glass substrate 1 does not need to have a groove to install the chip 3, which is beneficial to reduce the thickness of the glass substrate 1, reduce the product volume, and simplify the packaging process.

[0040] In some embodiments, the chip 3 is located in the middle of one of the surfaces of the glass substrate 1 .

[0041] In order to make the product structure more uniform, the chip 3 and the protection layer 4 are located between the solder 6 .

[0042] In an embodiment in which the protection layer 4 surrounds the chip 3 , the protection layer 4 covers the side surfaces of the chip 3 and the end surface close to the glass substrate 1 .

[0043] In one embodiment of the connection between the chip 3 and the rewiring layer 2 , the chip 3 and the rewiring layer 2 are connected via micro bumps 7 .

[0044] Furthermore, the micro bumps 7 are made of copper or other conductive materials.

[0045] Although the embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A chip flip package fan-out structure, characterized in that: include: Glass substrate; A redistribution layer is disposed on the glass substrate; A chip connected to the rewiring layer; A protection layer, the protection layer surrounds the chip and is located between the chip and the rewiring layer; A passivation layer connected to the glass substrate and disposed on a surface of the rewiring layer; Solder is connected to the redistribution layer and is partially exposed.

2. The chip flip package fan-out structure according to claim 1, characterized in that: The chip is located in the middle of one of the surfaces of the glass substrate.

3. The chip flip package fan-out structure according to claim 1, characterized in that: The chip and the protection layer are located between the solders.

4. The chip flip package fan-out structure according to claim 1, characterized in that: The protection layer covers the side surface of the chip and the end surface close to the glass substrate.

5. The chip flip package fan-out structure according to claim 1, characterized in that: The chip and the rewiring layer are connected via micro bumps.

6. The chip flip package fan-out structure according to claim 5, characterized in that: The material of the micro-bumps is copper.

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