Novel packaged semiconductor device

Abstract

The utility model belongs to the technical field of semiconductors, and discloses a novel packaged semiconductor device which comprises a chip, the chip is provided with a plurality of alternately arranged electrodes, and each electrode is provided with an electrode connection area used for being connected with an external circuit; the substrate assembly is used for packaging the chip, the substrate assembly comprises a first metal layer and a second metal layer, the first metal layer and the second metal layer are both located on the same side of the chip, and the second metal layer is located on the side, away from the chip, of the first metal layer; the first metal layer is electrically connected with the second metal layer, and the first metal layer is electrically connected with the chip through the electrode connection area; in the direction perpendicular to the chip, the plurality of electrodes are electrically connected with the second metal layer through the first metal layer. The semiconductor device has the advantages that heat dissipation of the semiconductor device is improved, and meanwhile parasitic resistance in the semiconductor device is reduced.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductors, and more specifically, to a novel packaged semiconductor device. Background Art

[0002] With the development of semiconductor materials, the third-generation semiconductors (silicon carbide, gallium nitride) have been commercialized on a large scale. Compared with the traditional silicon semiconductor materials, the third-generation semiconductor devices have brought huge performance and revolutionary changes to the power electronic system due to their high-frequency and high-efficiency performance advantages. For power semiconductor devices with coplanar electrodes or lateral structures, parasitic resistance is introduced to minimize the package, so FCQFN (Flip Chip Quad Flat No-Lead) packaging is widely used. Existing gallium nitride semiconductor devices usually use FCQFN packaging.

[0003] In the FCQFN package, such as Figure 1 As shown, the power electrodes are alternately arranged on multiple pins to increase the current transmission area, reduce the influence of parasitic resistance, and improve the working efficiency and performance of the device. In the existing solution, the pads of semiconductor devices must be consistent with the pin distribution of the chip. In order to meet the electrical and mounting requirements, a certain distance must be maintained between different pins, and a certain spacing must also be maintained between the metal traces of the substrate, making the pins and pads slender, resulting in large parasitic resistance of the substrate, and a small pin area, and very limited heat dissipation capacity.

[0004] The above technical means have the defects of large parasitic resistance and poor heat dissipation capability. Utility Model Content

[0005] The embodiments of the present application provide a novel packaged semiconductor device, which can improve the heat dissipation effect of the semiconductor device and reduce the parasitic resistance within the semiconductor device.

[0006] A novel packaged semiconductor device provided in the present application adopts the following technical solution:

[0007] A novel packaged semiconductor device, comprising:

[0008] A chip, wherein the chip is provided with a plurality of electrodes arranged alternately, and the electrodes have an electrode connection area for connecting to an external circuit;

[0009] A substrate assembly is used to encapsulate the chip, the substrate assembly includes a first metal layer and a second metal layer, the first metal layer and the second metal layer are both located on the same side of the chip, and the second metal layer is located on the side of the first metal layer away from the chip, the first metal layer is electrically connected to the second metal layer, and the first metal layer is electrically connected to the chip through the electrode connection area; in a direction perpendicular to the chip, a plurality of the electrodes are electrically connected to the second metal layer through the first metal layer, respectively.

[0010] Optionally, the first metal layer is provided with an avoidance groove for reducing parasitic resistance, the avoidance groove divides the first metal layer into multiple first installation areas corresponding to different electrodes, and the same electrode corresponds to the same first installation area, and the electrode connection area electrically connects the chip to the first metal layer through the first installation area.

[0011] Optionally, the first metal layer is provided with connection bumps corresponding to the electrode connection area, and the first metal layer is connected to the chip through the connection bumps.

[0012] Optionally, the second metal layer is provided with a plurality of second mounting areas corresponding to different electrodes, the first mounting area and the second mounting area are arranged in alignment, and the first mounting area and the second mounting area corresponding to the same electrode are electrically connected.

[0013] Optionally, multiple second mounting areas are each provided with pins for compatibility with vertical device packaging, and different electrodes are respectively connected to corresponding pins through the first mounting area and the second mounting area in a direction perpendicular to the second metal layer to achieve packaging compatibility between horizontal devices and vertical devices.

[0014] Optionally, a plurality of connecting metals are arranged between the first metal layer and the second metal layer, and the plurality of connecting metals are arranged corresponding to the positions of the plurality of pins, and the first mounting area and the second mounting area corresponding to the same electrode are connected through the connecting metals.

[0015] Optionally, the first mounting area is provided with a plurality of through holes corresponding to the pins, and the plurality of through holes are provided in one-to-one correspondence with the plurality of connecting metals, an end of the connecting metal close to the first mounting area is installed in the through hole, and an end of the connecting metal close to the second metal layer is fixedly connected to the second mounting area; the first metal layer and the second metal layer corresponding to the same electrode are electrically connected through the through hole and the connecting metal.

[0016] Optionally, the through hole may be in various shapes, and the shape and size of the through hole are compatible with the connecting metal.

[0017] Optionally, the first mounting area is provided with a connection terminal for connecting to the same electrode, and the connection terminal is configured as a portion of the first mounting area excluding a connection area corresponding to the electrode, and the connection terminal is used to increase the heat dissipation area of ​​the package.

[0018] Optionally, among the plurality of second connection areas, one of the connection areas has the largest area, and the area of ​​the pins arranged therein is also the largest.

[0019] It can be seen from the above technical solutions that the embodiments of the present application have the following advantages:

[0020] The present invention uses a two-layer metal stack package of a first metal layer and a second metal layer to electrically connect multiple electrodes of a chip through the first metal layer and the second metal layer in a vertical direction via an electrode connection area, and increases the heat dissipation area by surface-connecting two larger layers of metal, thereby enhancing the heat dissipation capacity of the overall package; at the same time, the first metal layer and the second metal layer increase the size of the electrode pins, reduce parasitic resistance, and enhance the ability to resist board-level mechanical deformation. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a FCQFN package diagram of a lateral device in the prior art;

[0022] Figure 2 A three-dimensional structural diagram of a portion of a novel packaged semiconductor device disclosed in an embodiment of the present application;

[0023] Figure 3 A schematic diagram of the structure of each layer of a novel packaged semiconductor device disclosed in an embodiment of the present application;

[0024] Figure 4 A schematic diagram showing electrodes arranged on a chip of a novel packaged semiconductor device disclosed in an embodiment of the present application;

[0025] Figure 5 A schematic diagram showing the connection relationship between a chip and a first metal layer in a novel packaged semiconductor device disclosed in an embodiment of the present application;

[0026] Figure 6 A schematic diagram showing a second metal layer of a semiconductor device of a novel package disclosed in an embodiment of the present application;

[0027] Figure 7 A schematic diagram showing the correspondence between through holes and pins of a novel packaged semiconductor device disclosed in an embodiment of the present application;

[0028] Figure 8 A top view of a PCB structure of a semiconductor device in a novel package disclosed in an embodiment of the present application;

[0029] Fig. 9 A side view of a PCB structure of a novel packaged semiconductor device disclosed in an embodiment of the present application.

[0030] Description of reference numerals:

[0031] 1. Chip; 11. Electrode; 111. First electrode; 112. Second electrode; 113. Third electrode; 12. Electrode connection area; 2. Substrate assembly; 21. First metal layer; 211. Avoidance groove; 212. First mounting area; 213. Connection bump; 214. Through hole; 215. Connection end; 22. Second metal layer; 221. Second mounting area; 222. Pin; 23. Connection metal. DETAILED DESCRIPTION

[0032] The present application is further described in detail below in conjunction with the accompanying drawings.

[0033] The embodiments of the present application provide a novel packaged semiconductor device, which can improve the heat dissipation effect of the semiconductor device and reduce the parasitic resistance within the semiconductor device.

[0034] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0035] The terms "first", "second", "third", "fourth", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0036] For ease of understanding, the novel packaged semiconductor device in the embodiment of the present application is described below. Figure 2 and Figure 3 The embodiment of the present application is an embodiment of a novel packaged semiconductor device, including a chip 1 and a substrate assembly 2 for packaging the chip 1 , wherein the chip 1 is mounted on the substrate assembly 2 .

[0037] Reference Figure 2 and Figure 4 The chip 1 is provided with a plurality of electrodes 11 arranged alternately. The electrode 11 has an electrode connection area 12 for connecting to an external circuit. The electrode connection area 12 is an open metal area for welding or connecting the chip 1 with other circuit elements. In this embodiment, the chip 1 is provided with three different electrodes 11. The three different electrodes 11 are arranged alternately, and a certain distance is ensured between different electrodes 11 to meet electrical and mounting requirements. Specifically, Figure 1 and Figure 4 As shown, the electrode 11 includes a first electrode 111 , a second electrode 112 and a third electrode 113 .

[0038] The purpose of setting different electrodes 11 on the chip 1 is to realize different functions and operations. Different electrodes 11 can be used to transmit current, control signals, store data, etc. The electrodes 11 in this embodiment include but are not limited to power electrodes, ground electrodes, input / output (I / O) electrodes, control electrodes, clock electrodes, memory electrodes, analog input / output (Analog I / O) electrodes, reset electrodes, interrupt electrodes and sensor electrodes, etc. These different electrodes 11 play a key role in the design of the chip 1. Through their combination and connection methods, various functions and applications of the chip 1 are realized.

[0039] Reference Figure 2 and Figure 3 The substrate assembly 2 includes a first metal layer 21 and a second metal layer 22. The first metal layer 21 and the second metal layer 22 are both located on the same side of the chip 1, and the second metal layer 22 is located on the side of the first metal layer 21 away from the chip 1. The first metal layer 21 and the second metal layer 22 are of the same size, and the area of ​​the first metal layer 21 and the second metal layer 22 is larger than the area of ​​the chip 1. The first metal layer 21 and the second metal layer 22 are parallel to the plane where the chip 1 is located. The first metal layer 21 is electrically connected to the second metal layer 22, and the first metal layer 21 is electrically connected to the chip 1 through the electrode connection area 12; in the direction perpendicular to the chip 1, a plurality of electrodes 11 are electrically connected to the second metal layer 22 through the first metal layer 21 respectively. The chip 1 is connected to the first metal layer 21 and the second metal layer 22 in the vertical direction through the electrode connection area 12, and the heat dissipation area is increased by connecting two larger layers of metal, so that the heat dissipation capacity of the overall package is enhanced; at the same time, the first metal layer 21 and the second metal layer 22 increase the electrode 11 pin 222, reduce the parasitic resistance, and enhance the ability to resist board-level mechanical deformation.

[0040] Reference Figure 5, the first metal layer 21 is provided with an avoidance groove 211, and the avoidance groove 211 is used to further reduce the parasitic resistance. The avoidance groove 211 divides the first metal layer 21 into a plurality of first mounting areas 212 corresponding to different electrodes 11, and the same electrode 11 corresponds to the same first mounting area 212, and the electrode connection area 12 electrically connects the chip 1 to the first metal layer 21 through the first mounting area 212. In this embodiment, the first mounting area 212 is provided with three parts, corresponding to the three types of electrodes 11, and the three first mounting areas 212 are spaced apart from each other and not connected through the avoidance groove 211. Furthermore, in order to enhance the connection stability between the chip 1 and the first metal layer 21, the first metal layer 21 is provided with a connection bump 213 corresponding to the electrode connection area 12, and the first metal layer 21 is connected to the chip 1 through the connection bump 213, and the connection bump 213 is located in the first connection area.

[0041] The first mounting area 212 is provided with a connection terminal 215 for connecting to the same electrode 11. The connection terminal 215 is configured as a portion of the first mounting area 212 excluding the corresponding electrode connection area 12. The connection terminal 215 is used to increase the heat dissipation area of ​​the semiconductor device, thereby further enhancing the heat dissipation effect.

[0042] Reference Figure 2 and Figure 3 The second metal layer 22 is provided with a plurality of second mounting areas 221 corresponding to different electrodes 11, the first mounting area 212 and the second mounting area 221 are arranged in alignment, and the first mounting area 212 and the second mounting area 221 corresponding to the same electrode 11 are electrically connected. In this embodiment, three second mounting areas 221 are provided, corresponding to the three types of electrodes 11 respectively.

[0043] Reference Figure 6 , multiple second mounting areas 221 are all provided with pins 222 for compatibility with vertical device packaging, and different electrodes 11 are respectively connected to corresponding pins 222 through the first mounting area 212 and the second mounting area 221 in a direction perpendicular to the second metal layer 22, so as to achieve packaging compatibility between horizontal devices and vertical devices, and can be directly replaced and applied, thereby expanding the adaptability of semiconductor devices. Among multiple second connection areas, one connection area has the largest area, and the area of ​​the pin 222 set therein is also the largest. Through two-layer metal stacking packaging, one of the electrodes 11 in the chip 1 is directly led to the relatively large pin 222 at the bottom of the device in the vertical direction, and the other electrode 11 is connected to another pin 222 at the bottom of the device through a large-area two-layer metal connection, thereby overcoming the shortcomings of current packaging.

[0044] Reference Figure 2 and Figure 6A plurality of connection metals 23 are arranged between the first metal layer 21 and the second metal layer 22. The plurality of connection metals 23 are arranged corresponding to the positions of the plurality of pins 222. The connection metals 23 realize the connection between the first mounting area 212 and the second mounting area 221 corresponding to the same electrode 11. In this embodiment, the connection metals 23 are arranged evenly and at intervals, and the connection metals 23 in the first mounting area 212 corresponding to the pin 222 with the largest area are completely paved with the first mounting area 212.

[0045] Reference Figure 7 Furthermore, the first mounting area 212 is provided with a plurality of through holes 214 corresponding to the pins 222, and the plurality of through holes 214 are provided in one-to-one correspondence with the plurality of connection metals 23, and the end of the connection metal 23 close to the first mounting area 212 is installed in the through hole 214, and the end of the connection metal 23 close to the second metal layer 22 is fixedly connected to the second mounting area 221; the first metal layer 21 and the second metal layer 22 corresponding to the same electrode 11 are electrically connected through the through hole 214 and the connection metal 23. The through hole 214 can be of various shapes, and the shape and size of the through hole 214 are adapted to the connection metal 23. In this embodiment, the through hole 214 and the connection metal 23 are circular.

[0046] The present application realizes a large pin 222 package for a lateral device without sacrificing heat dissipation or increasing parasitic resistance. Figure 8 As shown in the figure, the device electrode pin area is large enough, and multiple connection holes can be designed on the PCB pad to connect with other metal layers of the PCB. Fig. 9 As shown, the current can flow directly from different PCB metal layers to the bottom of the device. Compared with the technical solution in the prior art that the current of different metal layers converges to the top metal, then flows into the device laterally, and then flows out of the device laterally, the lateral path through which the current flows in this application is short, which greatly reduces the parasitic impedance of the PCB. Secondly, the device pad is large enough, and the heat dissipation capacity between the device and the PCB is greatly improved. Thirdly, because the device pad area is sufficient and the welding surface is large, the probability of cracking and failure of the solder joint can be reduced under the system board-level stress.

[0047] The above is only one implementation scheme. For coplanar electrode devices or lateral devices, according to the final target package size and form, and the layout defined by different pins 222, the structure and device formed by the method of the present invention through the corresponding graphic design of the first metal layer 21 and the second metal layer 22 and the corresponding connection all belong to the scope of the present invention. The above embodiments are only used to illustrate the technical scheme of the present invention, but not to limit it. Although the present invention is described in detail with reference to the above embodiments, ordinary technicians in this field should understand that they can still modify the technical schemes recorded in the above embodiments, or replace some of the technical features therein by equivalents; and these modifications or replacements do not make the essence of the corresponding technical scheme deviate from the spirit and scope of the technical schemes of the embodiments of the present invention.

Claims

1. A novel packaged semiconductor device, characterized in that: include: A chip (1), wherein the chip (1) is provided with a plurality of electrodes (11) arranged in an alternating manner, and the electrodes (11) have an electrode connection area (12) for connecting to an external circuit; A substrate assembly (2) for packaging the chip (1), the substrate assembly (2) comprising a first metal layer (21) and a second metal layer (22), the first metal layer (21) and the second metal layer (22) being located on the same side of the chip (1), and the second metal layer (22) being located on a side of the first metal layer (21) away from the chip (1), the first metal layer (21) being electrically connected to the second metal layer (22), the first metal layer (21) being electrically connected to the chip (1) via the electrode connection region (12); and in a direction perpendicular to the chip (1), a plurality of the electrodes (11) are electrically connected to the second metal layer (22) via the first metal layer (21), respectively.

2. A novel packaged semiconductor device according to claim 1, characterized in that: The first metal layer (21) is provided with a avoidance groove (211) for reducing parasitic resistance, the avoidance groove (211) divides the first metal layer (21) into a plurality of first mounting areas (212) corresponding to different electrodes (11), and the same electrode (11) corresponds to the same first mounting area (212), and the electrode (11) connection area electrically connects the chip (1) to the first metal layer (21) through the first mounting area (212).

3. A novel packaged semiconductor device according to claim 2, characterized in that: The first metal layer (21) is provided with a connection bump (213) corresponding to the electrode connection area (12), and the first metal layer (21) is connected to the chip (1) via the connection bump (213).

4. A novel packaged semiconductor device according to claim 2, characterized in that: The second metal layer (22) is provided with a plurality of second mounting areas (221) corresponding to different electrodes (11); the first mounting area (212) and the second mounting area (221) are arranged in alignment; and the first mounting area (212) and the second mounting area (221) corresponding to the same electrode (11) are electrically connected.

5. A novel packaged semiconductor device according to claim 4, characterized in that: The plurality of second mounting areas (221) are each provided with pins (222) for being compatible with vertical device packaging, and the different electrodes (11) are respectively connected to corresponding pins (222) through the first mounting area (212) and the second mounting area (221) in a direction perpendicular to the second metal layer (22), so as to achieve packaging compatibility between horizontal devices and vertical devices.

6. A novel packaged semiconductor device according to claim 5, characterized in that: A plurality of connection metals (23) are arranged between the first metal layer (21) and the second metal layer (22); the plurality of connection metals (23) are arranged corresponding to the positions of the plurality of pins (222); and the connection metals (23) are used to realize the connection between the first mounting area (212) and the second mounting area (221) corresponding to the same electrode (11).

7. A novel packaged semiconductor device according to claim 6, characterized in that: The first mounting area (212) is provided with a plurality of through holes (214) corresponding to the pin (222); the plurality of through holes (214) are provided in one-to-one correspondence with the plurality of connecting metals (23); one end of the connecting metal (23) close to the first mounting area (212) is mounted on the through hole (214); one end of the connecting metal (23) close to the second metal layer (22) is fixedly connected to the second mounting area (221); the first metal layer (21) and the second metal layer (22) corresponding to the same electrode (11) are electrically connected via the through hole (214) and the connecting metal (23).

8. A novel packaged semiconductor device according to claim 7, characterized in that: The through hole (214) can be in various shapes, and the shape and size of the through hole (214) are compatible with the connection metal (23).

9. A novel packaged semiconductor device according to claim 2, characterized in that: The first mounting area (212) is provided with a connection end (215) for connecting to the same electrode (11); the connection end (215) is configured as a portion of the first mounting area (212) excluding the corresponding electrode connection area (12); and the connection end (215) is used to increase the heat dissipation area of ​​the package.

10. A novel packaged semiconductor device according to claim 5, characterized in that: Among the plurality of second installation areas (221), one of the second installation areas (221) has the largest area, and the area of ​​the pins (222) arranged therein is also the largest.

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