Embedded fan-out packaging structure
By embedding carrier chips and dielectric layers in the package structure, fan-out interconnection of multi-chips is achieved, solving the complexity and high cost of through-silicon technology, and achieving efficient and low-cost multi-chip packaging.
Patent Information
- Application Number
- CN202421438462.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-21
- Publication Date
- 2025-05-13
- Estimated Expiration
- 2034-06-21
AI Technical Summary
Among the existing 2.5D and 3D packaging technologies, through-silicon technology has problems such as difficult and high cost, which is difficult to meet the needs of multi-chip packaging in portable/mobile electronic devices.
Using an embedded fan-out package structure, by embedding a carrier chip and a plurality of dielectric layers in the rewiring layer, interconnection between the first chip and the second chip is achieved using conductive layers and redistribution lines, thereby avoiding the use of through-silicon holes.
It realizes efficient interconnection of multi-chip, simplifies the preparation process, reduces costs, while avoiding the complexity and high costs of through-silicon technology.
Smart Images
Figure CN222867685U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor packaging, and in particular to an embedded fan-out packaging structure. Background Art
[0002] The current market demand for portable / mobile electronic devices is to integrate more functional devices into smaller and smaller spaces. Therefore, more and more chips are contained in a single package. Existing 2.5D and 3D packaging technologies can realize the packaging of multiple chips, where multiple chips are interconnected through silicon via (TSV) technology. However, TSV technology has the disadvantages of difficult process and high cost. Utility Model Content
[0003] In view of this, it is necessary to provide an embedded fan-out packaging structure that can solve the above problems.
[0004] The embodiment of the present application provides an embedded fan-out packaging structure, comprising a redistribution layer, a first chip, a second chip and a packaging layer, wherein the first chip and the second chip are bonded to a first side of the redistribution layer, and the packaging layer covers the first chip and the second chip and covers the first side. The redistribution layer comprises a plurality of dielectric layers and a carrier chip embedded in the plurality of dielectric layers, a first conductive layer is disposed on the carrier chip, the first conductive layer is exposed from the first side, and interconnects the first chip and the second chip.
[0005] In the embedded fan-out packaging structure provided in the present application, the first chip and the second chip are interconnected through a carrier chip embedded in the dielectric layer of the redistribution layer, without the need to set up silicon through vias, so the preparation process is relatively simple and the cost is relatively low. BRIEF DESCRIPTION OF THE DRAWINGS
[0006] Figure 1 A cross-sectional view of a supporting substrate provided in accordance with an embodiment of the present application.
[0007] Figure 2 For Figure 1 A cross-sectional view of a supporting substrate after a dielectric layer and redistribution lines are formed thereon is shown.
[0008] Figure 3 In order to attach the carrier chip having the conductive layer and the adhesive layer on the two opposite surfaces Figure 2 A cross-sectional view of the structure shown.
[0009] Figure 4 For Figure 3 The structure shown is a cross-sectional view after multiple dielectric layers and a plurality of redistribution lines are formed on the structure to form a redistribution layer.
[0010] Figure 5To bond the first chip and the second chip to Figure 4 A cross-sectional view of the structure shown.
[0011] Figure 6 For Figure 5 A cross-sectional view of the structure after an encapsulation layer is formed on the structure shown.
[0012] Figure 7 For Figure 6 A cross-sectional view of the structure after forming connection pads.
[0013] Main component symbols
[0014] Package structure 100
[0015] Rewiring layer 10
[0016] First chip 40
[0017] The second chip 60
[0018] Encapsulation layer 70
[0019] Carrier chip 30
[0020] First side 11
[0021] Second side 16
[0022] First conductive layer 311
[0023] The first dielectric layer 141
[0024] The second dielectric layer 143
[0025] The third dielectric layer 145
[0026] Fourth dielectric layer 146
[0027] First through hole 1411
[0028] The second through hole 1431
[0029] The third through hole 1451
[0030] Fourth through hole 1461
[0031] The first redistribution line 121
[0032] The second redistribution line 123
[0033] The third redistribution line 125
[0034] Fourth redistribution line 126
[0035] First surface 31
[0036] Second surface 33
[0037] Side 35
[0038] The first fan-out interconnection wiring area 13
[0039] The second fan-out interconnection wiring area 15
[0040] The second conductive layer 351
[0041] Adhesive layer 36
[0042] Connection pad 80
[0043] Conductive bump 50
[0044] Supporting substrate 200
[0045] Separation layer 210
[0046] The following specific implementation methods will further illustrate the present application in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION
[0047] In order to more clearly understand the above-mentioned purposes, features and advantages of the present application, the present application is described in detail below in conjunction with the accompanying drawings and specific embodiments. In the following description, many specific details are set forth to facilitate a full understanding of the present application, and the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application.
[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0049] See also Figure 7In one embodiment of the present application, an embedded fan-out packaging structure 100 is provided, which includes a redistribution layer 10, a first chip 40, a second chip 60 and a packaging layer 70. The redistribution layer 10 includes a plurality of dielectric layers, a plurality of redistribution lines embedded in the plurality of dielectric layers, and a carrier chip 30 embedded in the plurality of dielectric layers. The plurality of redistribution lines are exposed from a first side 11 of the redistribution layer 10 and a second side 16 opposite to the first side 11, and are electrically connected to the first chip 40 and the second chip 60. A first conductive layer 311 is provided on the carrier chip 30, and the first conductive layer 311 is exposed from the first side 11 of the redistribution layer 10. The first chip 40 and the second chip 60 are arranged on the first side 11, and the first conductive layer 311 interconnects the first chip 40 and the second chip 60.
[0050] The plurality of dielectric layers include a first dielectric layer 141, a second dielectric layer 143, a third dielectric layer 145, and a fourth dielectric layer 146 which are stacked. The side of the first dielectric layer 141 facing away from the second dielectric layer 143 serves as the second side 16 of the redistribution layer 10, and the side of the fourth dielectric layer 146 facing away from the third dielectric layer 145 serves as the first side 11 of the redistribution layer 10. The first dielectric layer 141 is provided with a plurality of patterned first through holes 1411. The second dielectric layer 143 is provided with a plurality of patterned second through holes 1431, and the second through holes 1431 are connected to the first through holes 1411. The third dielectric layer 145 is provided with a plurality of patterned third through holes 1451, and the third through holes 1451 are connected to the second through holes. The fourth dielectric layer 146 is provided with a plurality of patterned fourth through holes 1461, and the fourth through holes 1461 are connected to the third through holes 1451.
[0051] The materials of the first dielectric layer 141, the second dielectric layer 143, the third dielectric layer 145 and the fourth dielectric layer 146 can be selected from one or a combination of two or more of epoxy resin, silica gel, polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), silicon oxide, phosphosilicate glass and fluorine-containing glass. In some embodiments, the materials of the first dielectric layer 141, the second dielectric layer 143, the third dielectric layer 145 and the fourth dielectric layer 146 are polyimide (PI) to further reduce the process difficulty and process cost.
[0052] The plurality of redistribution lines include a first redistribution line 121 filled in the first through hole 1411, a second redistribution line 123 filled in the second through hole 1431, a third redistribution line 125 filled in the third through hole 1451, and a fourth redistribution line 126 filled in the fourth through hole 1461. The first redistribution line 121 is exposed outside the second side 16 through the first through hole 1411. The second redistribution line 123 is electrically connected to the first redistribution line 121 and the third redistribution line 125. The fourth redistribution line 126 is electrically connected to the third redistribution line 125 and is exposed outside the first side 11 from the fourth through hole 1461. It can be understood that the number of layers of dielectric layers and redistribution lines in the redistribution layer 10 can be set according to actual needs.
[0053] The materials of the first redistribution line 121 , the second redistribution line 123 , the third redistribution line 125 , and the fourth redistribution line 126 may respectively include one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium.
[0054] The carrier chip 30 includes integrated passive devices, such as resistors, inductors, capacitors, etc. The carrier chip 30 is embedded in the first dielectric layer 141, the second dielectric layer 143, the third dielectric layer 145, and the fourth dielectric layer 146, and includes a first surface 31, a second surface 33 disposed opposite to the first surface 31, and a plurality of side surfaces 35 connecting the first surface 31 and the second surface 33. The first surface 31 and the second surface 33 are disposed substantially in parallel, and the side surfaces 35 are disposed obliquely relative to the first surface 31 and the second surface 33. In some embodiments, the angle between the side surface 35 and the first surface 31 is an obtuse angle, and the angle between the side surface 35 and the second surface 33 is an acute angle.
[0055] The first conductive layer 311 is disposed on the first surface 31 and exposed from the first side 11. The material of the first conductive layer 311 may include one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium.
[0056] The redistribution layer 10 includes a first fan-out interconnection wiring area 13 and a second fan-out interconnection wiring area 15 located on opposite sides of the carrier chip 30. A second conductive layer 351 is provided on the side 35 of the carrier chip 30. The second conductive layer 351 located on one side 35 is electrically connected to the redistribution line located in the first fan-out interconnection wiring area 13, and the second conductive layer 351 located on the other side 35 is electrically connected to the redistribution line located in the second fan-out interconnection wiring area 15. The first conductive layer 311 and the second conductive layer 351 interconnect the redistribution line located in the first fan-out interconnection wiring area 13 and the redistribution line located in the second fan-out interconnection wiring area 15. The material of the second conductive layer 351 may include one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium.
[0057] In some embodiments, the second surface 33 of the carrier chip 30 is bonded to the plurality of dielectric layers via an adhesive layer 36. In this embodiment, the adhesive layer 36 is sandwiched between the first dielectric layer 141 and the second surface 33.
[0058] In some embodiments, a plurality of connection pads 80 are formed on the second side 16 of the redistribution layer 10 to realize electrical lead-out of the redistribution layer 10. Part of the connection pads 80 are electrically connected to the first redistribution line 121 located in the first fan-out interconnection wiring area 13, and other connection pads 80 are electrically connected to the first redistribution line 121 located in the second fan-out interconnection wiring area 15.
[0059] The first chip 40 is electrically connected to the first conductive layer 311 and the redistribution lines in the first fan-out interconnection wiring region 13 , and the second chip 60 is electrically connected to the first conductive layer 311 and the redistribution lines in the second fan-out interconnection wiring region 15 .
[0060] In this embodiment, the first chip 40 and the second chip 60 are bonded to the first side 11 of the redistribution layer 10 using flip chip technology. A plurality of conductive bumps 50 are respectively provided on the first chip 40 and the second chip 60, and the conductive bumps 50 are electrically connected to the first conductive layer 311 and the redistribution line. The material of the conductive bumps 50 is metal, such as copper, titanium, nickel, gold or alloys thereof. In some embodiments, the first chip 40 and the second chip 60 can also be electrically connected to the first conductive layer 311 and the redistribution line by wire bonding.
[0061] The encapsulation layer 70 encapsulates the first chip 40 and the second chip 60, covers the first side 11 of the redistribution layer 10, and fills the gaps between the plurality of conductive bumps 50. The encapsulation layer 70 can be formed using a dry film technique (e.g., lamination) or a liquid-based technique (e.g., curing film). The material of the encapsulation layer 70 can be any suitable molding compound material commonly used in electronic packaging.
[0062] An embodiment of the present application also provides a method for preparing an embedded fan-out packaging structure, which includes the following steps.
[0063] like Figure 1 As shown, step S1 is first performed to provide a supporting substrate 200 .
[0064] The support substrate 200 may be a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate or a ceramic substrate. In this embodiment, the support substrate 200 is a glass substrate.
[0065] In some embodiments, a separation layer 210 is further formed on the surface of the support substrate 200, which is conducive to the subsequent stripping process. As an example, the separation layer 210 includes a light-to-heat conversion layer (LTHC), which is formed on the support substrate 200 by a spin coating process and then cured by a curing process. The light-to-heat conversion layer (LTHC) has stable performance and a relatively smooth surface, which is conducive to the subsequent preparation of the rewiring layer, and in the subsequent stripping process, the stripping difficulty is relatively low.
[0066] See also Figure 2-4 Then, step S2 is performed to form a redistribution layer 10 on the supporting substrate, wherein the redistribution layer 10 includes a plurality of dielectric layers, a plurality of redistribution lines embedded in the plurality of dielectric layers, and a carrier chip 30 embedded in the plurality of dielectric layers, wherein the redistribution lines are exposed from a first side 11 and a second side 16 opposite to the redistribution layer 10, and a first surface 31 of the carrier chip 30 is provided with a first conductive layer 311, and the first conductive layer 311 is exposed from the first side 11 of the redistribution layer 10.
[0067] In some embodiments, the redistribution layer 10 is formed on the separation layer 210, the side of the redistribution layer 10 in contact with the separation layer 210 is the second side 16, and the first side 11 is disposed opposite to the second side 16. Step S2: forming the redistribution layer 10 includes the following steps.
[0068] like Figure 2As shown, step S2-1 is performed, a first dielectric layer 141 is formed on the surface of the separation layer 210 by a chemical vapor deposition process or a physical vapor deposition process, and the first dielectric layer 141 is etched to form a plurality of patterned first through holes 1411. The material of the first dielectric layer 141 is selected from one or a combination of two or more of epoxy resin, silica gel, polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), silicon oxide, phosphosilicate glass and fluorine-containing glass. In some embodiments, the material of the first dielectric layer 141 is polyimide (PI) to further reduce the process difficulty and process cost. The surface of the first dielectric layer 141 in contact with the separation layer 210 serves as the first side of the redistribution layer 10. The first through hole 1411 penetrates the two surfaces of the first dielectric layer 141 and the separation layer 210 that are in contact and away from each other.
[0069] like Figure 2 As shown, step S2-2 is performed to fill the plurality of first through holes 1411 with conductive material to form a plurality of first redistribution lines 121. The material of the first redistribution lines 121 includes one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium. The first redistribution lines 121 are exposed from the second side 16 of the redistribution layer 10 through the first through holes 1411.
[0070] like Figure 3 As shown, step S2 - 3 is performed to provide the carrier chip 30 having the first conductive layer 311 disposed on its surface, and fix the carrier chip 30 on the surface of the first dielectric layer 141 away from the separation layer 210 .
[0071] The carrier chip 30 includes a first surface 31, a second surface 33 disposed opposite to the first surface 31, and a plurality of side surfaces 35 connecting the first surface 31 and the second surface 33. The second surface 33 is in contact with the first dielectric layer 141. The first surface 31 and the second surface 33 are disposed substantially in parallel, and the side surfaces 35 are disposed obliquely relative to the first surface 31 and the second surface 33. In some embodiments, the angle between the side surface 35 and the first surface 31 is an obtuse angle, and the angle between the side surface 35 and the second surface 33 is an acute angle. The inclined side surfaces 35 facilitate the subsequent formation of the second conductive layer interconnecting the first conductive layer 311 and the plurality of redistribution lines 12.
[0072] The first surface 31 of the carrier chip 30 is provided with the first conductive layer 311. The material of the first conductive layer 311 includes one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium.
[0073] In some embodiments, the second surface 33 of the carrier chip 30 is bonded to the surface of the first dielectric layer 141 through an adhesive layer 36 .
[0074] Step S2-3 specifically includes: providing a carrier having the first conductive layer 311 and the adhesive layer 36 disposed on two opposite surfaces respectively; cutting the carrier to form the plurality of side surfaces 35 disposed obliquely relative to the first conductive layer 311 and the adhesive layer 36, thereby forming the carrier chip 30; attaching the carrier chip 30 to the surface of the first dielectric layer 141 away from the separation layer 210 through the adhesive layer 36. The first conductive layer 311 can be formed on the carrier by coating, deposition, and the like. The adhesive layer 36 can be formed on the carrier by coating, attachment, and the like.
[0075] like Figure 4 As shown, step S2-4 is performed to sequentially form a second dielectric layer 143 having a patterned second through hole 1431, a third dielectric layer 145 having a patterned third through hole 1451, and a fourth dielectric layer 146 having a patterned fourth through hole 1461 on the surface of the first dielectric layer 141, and fill the second through hole 1431, the third through hole 1451, and the fourth through hole 1461 with conductive material to form a second redistribution line 123, a third redistribution line 125, and a fourth redistribution line 126, respectively, and form a second conductive layer 351 on the side surface 35 of the carrier chip 30.
[0076] The third dielectric layer 145 is formed on the side of the second dielectric layer 143 away from the first dielectric layer 141, and the fourth dielectric layer 146 is formed on the side of the third dielectric layer 145 away from the second dielectric layer 143. The side of the fourth dielectric layer 146 away from the third dielectric layer 145 serves as the first side 11 of the redistribution layer 10. The second dielectric layer 143, the third dielectric layer 145 and the fourth dielectric layer 146 can be formed by chemical vapor deposition or physical vapor deposition, respectively. The materials of the second dielectric layer 143, the third dielectric layer 145 and the fourth dielectric layer 146 can be selected from one or a combination of two or more of epoxy resin, silica gel, polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), silicon oxide, phosphorus silicon glass and fluorine-containing glass. In some embodiments, the materials of the second dielectric layer 143, the third dielectric layer 145 and the fourth dielectric layer 146 are selected from polyimide (PI).
[0077] The second through hole 1431, the third through hole 1451 and the fourth through hole 1461 may be formed by an etching process. Each second through hole 1431 is connected to the corresponding first through hole 1411, each third through hole 1451 is connected to the corresponding second through hole 1431, and each fourth through hole 1461 is connected to the corresponding third through hole 1451. Each second redistribution line 123 is electrically connected to the corresponding first redistribution line 121, each third redistribution line 125 is electrically connected to the corresponding second redistribution line 123, and each fourth redistribution line 126 is electrically connected to the corresponding third redistribution line 125. The fourth redistribution line 126 is exposed outside the first side 11 through the fourth through hole 1461. The materials of the second redistribution line 123, the third redistribution line 125 and the fourth redistribution line 126 may include one or a combination of two or more of copper, aluminum, nickel, gold, silver and titanium, respectively.
[0078] The first dielectric layer 141, the second dielectric layer 143, the third dielectric layer 145 and the fourth dielectric layer 146 constitute a multi-layer dielectric layer of the redistribution layer 10. The first redistribution line 121, the second redistribution line 123, the third redistribution line 125 and the fourth redistribution line 126 constitute a multi-layer redistribution line of the redistribution layer 10. It can be understood that the number of dielectric layers and redistribution lines in the redistribution layer 10 can be set according to actual needs.
[0079] The second redistribution line 123 contacts the glue layer 36. The second conductive layer 351 electrically connects the second redistribution line 123 and the first conductive layer 311. The second conductive layer 351 may be formed on the side surface 35 of the carrier chip 30 by a sputtering process or an electroplating process. The material of the second conductive layer 351 may include one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium.
[0080] In some embodiments, the thickness of the glue layer 36 is the same as that of the second dielectric layer 143, and the second conductive layer 351 can be formed when manufacturing the second redistribution line 123. The third dielectric layer 145 and the fourth dielectric layer 146 cover the second conductive layer 351, and the first conductive layer 311 is exposed from the first side 11.
[0081] The redistribution layer 10 includes a first fan-out interconnection wiring area 13 and a second fan-out interconnection wiring area 15 located at opposite sides of the carrier chip 30. The first conductive layer 311 and the second conductive layer 351 interconnect the redistribution lines located in the first fan-out interconnection wiring area 13 and the redistribution lines located in the second fan-out interconnection wiring area 15.
[0082] like Figure 5 As shown, step S3 is performed to provide a first chip 40 and a second chip 60 , and to bond the first chip 40 and the second chip 60 to the first side 11 of the redistribution layer 10 to achieve electrical connection with the redistribution layer 10 .
[0083] The first chip 40 is electrically connected to the first conductive layer 311 and the redistribution line located in the first fan-out interconnect wiring area 13, and the second chip 60 is electrically connected to the first conductive layer 311 and the redistribution line located in the second fan-out interconnect wiring area 15. In this embodiment, the first chip 40 and the second chip 60 are bonded to the first side 11 of the redistribution layer 10 using flip chip technology. A plurality of conductive bumps 50 are distributed on the first chip 40 and the second chip 60, and the conductive bumps 50 are electrically connected to the first conductive layer 311 and the redistribution line. The material of the conductive bumps 50 is metal, such as copper, titanium, nickel, gold or alloys thereof. In some embodiments, the first chip 40 and the second chip 60 can also be electrically connected to the first conductive layer 311 and the redistribution line by wire bonding.
[0084] like Figure 6 As shown, step S4 is performed to encapsulate the first chip 40 and the second chip 60 on the redistribution layer 10 to form a packaging layer 70. The first chip 40 and the second chip 60 are encapsulated in the packaging layer 70.
[0085] The encapsulation layer 70 may be formed by dry film technology (eg, lamination) or liquid-based technology (eg, curing film). The material of the encapsulation layer 70 may be any suitable molding compound material commonly used in electronic packaging.
[0086] like Figure 6 and Figure 7 As shown, step S5 is performed to peel off the support substrate 200 and form a plurality of connection pads 80 on the second side 16 of the redistribution layer 10 to realize the electrical lead-out of the redistribution layer 10. Part of the connection pads 80 are electrically connected to the first redistribution line 121 located in the first fan-out interconnection wiring area 13, and other connection pads 80 are electrically connected to the first redistribution line 121 located in the second fan-out interconnection wiring area 15.
[0087] The support substrate 200 is peeled off by peeling off the separation layer 210. After peeling off, the second side 16 of the redistribution layer 10 is exposed.
[0088] The material of the connection pad 80 is metal, such as copper, aluminum, tungsten, gold, silver, nickel or alloys thereof, etc. In this embodiment, the connection pad 80 is a solder ball.
[0089] In the embedded fan-out package structure and its preparation method provided in the embodiment of the present application, the first chip 40 and the second chip 60 are interconnected through the carrier chip 30 embedded in the dielectric layer of the redistribution layer 10, without the need to set up through silicon vias, the preparation process is relatively simple, and the cost is relatively low. The side surface 35 of the carrier chip 30 is arranged obliquely, which is conducive to the formation of the second conductive layer 351.
[0090] The above implementation modes are only used to illustrate the technical solutions of the present application and are not intended to limit the present application. Although the present application has been described in detail with reference to the above preferred implementation modes, a person skilled in the art should understand that the technical solutions of the present application may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present application.
Claims
1. An embedded fan-out packaging structure, comprising a redistribution layer, a first chip, a second chip and a packaging layer, wherein the first chip and the second chip are bonded to a first side of the redistribution layer, and the packaging layer covers the first chip and the second chip and covers the first side, characterized in that: The redistribution layer includes a plurality of dielectric layers and a carrier chip embedded in the plurality of dielectric layers. A first conductive layer is disposed on the carrier chip. The first conductive layer is exposed from the first side and interconnects the first chip and the second chip.
2. The embedded fan-out packaging structure according to claim 1, characterized in that: The redistribution layer further includes a plurality of redistribution lines embedded in the plurality of dielectric layers, the first chip is electrically connected to a portion of the redistribution lines on one side of the carrier chip, and the second chip is electrically connected to another portion of the redistribution lines on the other side of the carrier chip.
3. The embedded fan-out packaging structure according to claim 2, characterized in that: The carrier chip includes a first surface, a second surface arranged opposite to the first surface, and a side surface connecting the first surface and the second surface, the first conductive layer is arranged on the first surface, the side surface is provided with a second conductive layer electrically connected to the first conductive layer, and the first conductive layer and the second conductive layer interconnect redistribution lines located on opposite sides of the carrier chip.
4. The embedded fan-out packaging structure according to claim 3, characterized in that: The side surface is inclined relative to the first surface and the second surface.
5. The embedded fan-out packaging structure according to claim 3, characterized in that: The included angle between the side surface and the first surface is an obtuse angle, and the included angle between the side surface and the second surface is an acute angle.
6. The embedded fan-out packaging structure according to claim 2, characterized in that: The embedded fan-out packaging structure further includes a plurality of connection pads, the redistribution layer includes a second side away from the first side, and the plurality of connection pads are disposed on the second side and electrically connected to the redistribution lines.
7. The embedded fan-out packaging structure according to claim 2, characterized in that: The first chip and the second chip are electrically connected to the first conductive layer and the redistribution line by wire bonding.
8. The embedded fan-out packaging structure according to claim 1, characterized in that: The first chip and the second chip are bonded to the first side by using flip chip technology.
9. The embedded fan-out packaging structure according to claim 1, characterized in that: The carrier chip is bonded to the plurality of dielectric layers through an adhesive layer.
10. The embedded fan-out packaging structure according to claim 1, characterized in that: The carrier chip includes integrated passive devices.