Product for reducing test loss of silicon carbide diode
By etching the P-type deep trench on the silicon carbide epitaxial layer and forming a PN junction, transferring the high electric field strength to the inside of the epitaxial layer, the problem of ignition of the high-voltage silicon carbide diode in the CP test is solved, and the effect of reducing loss cost is achieved.
Patent Information
- Application Number
- CN202421844932.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-31
- Publication Date
- 2025-05-13
- Estimated Expiration
- 2034-07-31
AI Technical Summary
When conducting wafer CP tests for silicon carbide high-voltage diodes, ignition is prone to occur, resulting in damage to the chip and test equipment, especially products of 1700V and above are more susceptible to the impact.
By etching on the silicon carbide epitaxial layer, and forming PN junctions on both sides of the trench, the high electric field strength is transferred to the interior of the epitaxial layer by etching on the silicon carbide epitaxial layer, thereby reducing the occurrence of ignition phenomenon.
It effectively avoids the occurrence of ignition of silicon carbide high-voltage diodes during CP testing, reduces the loss cost of the product, and achieves this goal without increasing the chip terminal size and changing the test machine.
Smart Images
Figure CN222869296U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductors, in particular to a product for reducing test losses of silicon carbide diodes. Background Art
[0002] As the third generation wide bandgap semiconductor, silicon carbide has a bandgap width of 3.26ev, which is three times that of traditional silicon-based materials. Silicon carbide devices made of this material have advantages over traditional silicon devices such as high temperature stability, high power density, high efficiency and high frequency resistance. These advantages make silicon carbide devices in many fields such as electric vehicles, renewable energy, power transmission, smart grids, industrial appliances, rail transportation, aerospace, etc. And with the continuous advancement of design structure technology and the continuous reduction of raw material costs, the cost gap between silicon carbide devices and silicon-based devices is getting smaller and smaller, and the application prospects of SiC devices will be broader.
[0003] As a wide bandgap semiconductor, silicon carbide is particularly suitable for high-voltage devices. Currently, 650V, 1200V, and 1700V silicon carbide devices have been used in large quantities in the market, and the share of products with 2000V and above is also increasing. However, such ultra-high voltage products have brought certain difficulties to chip testing. Wafer factory chip testing is also called wafer CP (Chip Probing) testing, which is an electrical test of each chip on the silicon carbide wafer. When the wafer CP test is performed, its reverse voltage will reach the avalanche voltage of the device (generally 1.5 times the designed withstand voltage value of the device). Since the chip edge and the back electrode are equipotential and the silicon carbide diode terminal size is small, the breakdown field strength of the air is also small, about 30KV / CM, and ionization occurs above the diode terminal, and then sparking occurs, damaging the wafer and test equipment. Especially for products with 1700V and above, the JTE (junction terminal extension) terminal structure is generally used to ensure that the terminal size is smaller, which is more prone to sparking, causing chip damage.
[0004] To address this difficulty, the industry generally uses a probe card to blow N2 on the chip surface to reduce the surface pressure of the chip, thereby increasing the air breakdown voltage to avoid sparking. However, this method has basically no effect on silicon carbide high-voltage diodes of 1700V and above. Utility Model Content
[0005] In view of the above problems, the utility model provides a product for reducing the test loss of silicon carbide diodes by avoiding the sparking phenomenon of silicon carbide high-voltage diodes of 1700V or above.
[0006] The technical solution of the utility model is:
[0007] A product for reducing test loss of a silicon carbide diode, comprising, from bottom to top, a back thickened metal, a back ohmic contact metal, a silicon carbide substrate and a silicon carbide epitaxial layer;
[0008] The top surface of the silicon carbide epitaxial layer is provided with:
[0009] A plurality of P-type doped regions 1 are provided, each extending downward from the top surface of the silicon carbide epitaxial layer and arranged at intervals;
[0010] A second P-type doped region extending downward from the top surface of the silicon carbide epitaxial layer;
[0011] A third P-type doping region extends downward from the top surface of the silicon carbide epitaxial layer and is connected to the side of the second P-type doping region; a vertical depth of the third P-type doping region is greater than a vertical depth of the second P-type doping region;
[0012] A P-type doped region four extends downward from the top surface of the silicon carbide epitaxial layer, has a U-shaped cross-section, and is spaced apart from the P-type doped region three;
[0013] Field oxygen is arranged on the top surface of the silicon carbide epitaxial layer, passes through the second P-type doping region, the third P-type doping region and the fourth P-type doping region in sequence, and then extends to the edge of the device;
[0014] A Schottky contact metal is disposed on the top surface of the silicon carbide epitaxial layer, passes through the P-type doping region 1 and the P-type doping region 2 in sequence, and then climbs to the top surface of the field oxide;
[0015] A front thickened metal extending upward from a top surface of the Schottky contact metal;
[0016] The passivation layer extends from the top surface of the field oxide toward the front thickened metal and climbs to the top surface of the front thickened metal.
[0017] Specifically, the passivation layer includes an inorganic passivation layer and an organic passivation layer.
[0018] Specifically, the thickness of the Schottky contact metal ranges from 500A to 1500A.
[0019] Specifically, the thickness of the front thickened metal is 2um-6um.
[0020] Specifically, the thickness of the silicon carbide epitaxial layer is 5-30 um.
[0021] The utility model forms a P-type deep groove by etching on the silicon carbide epitaxial layer, and forms a PN junction on both sides of the groove by inclined ion implantation. When the device is subjected to reverse high-voltage test, due to the presence of the deep groove PN junction, the high electric field is transferred from the surface of the silicon carbide device to the inside of the silicon carbide epitaxial material. In addition, since the breakdown field strength of silicon dioxide and silicon nitride (3-20MV / cm) is much greater than that of air (about 0.033MV / cm), filling silicon dioxide and silicon nitride in the silicon carbide groove can also increase the anti-sparking ability of the diode. The structural optimization design of the utility model can better avoid the occurrence of sparking during the CP test of the silicon carbide high-voltage diode, reducing the loss cost of the product. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] Figure 1 It is a structural schematic diagram of step S100 of the utility model;
[0023] Figure 2 It is a structural schematic diagram of step S200 of the utility model;
[0024] Figure 3 It is a structural schematic diagram of step S300 of the utility model;
[0025] Figure 4 It is a structural schematic diagram of step S400 of the utility model;
[0026] Figure 5 It is a structural schematic diagram of step S500 of the utility model;
[0027] Figure 6 It is a structural schematic diagram of step S600 of the utility model;
[0028] Figure 7 is a schematic diagram of the cross-sectional structure after the inorganic passivation layer is prepared;
[0029] Figure 8 is a schematic diagram of the cross-sectional structure after the organic passivation layer is prepared;
[0030] Fig. 9 is a schematic diagram of the cross-sectional structure of the back ohmic contact electrode;
[0031] Fig.10 This is a schematic diagram of the cross-sectional structure after the back side is thickened with metal;
[0032] In the figure, 1 is a silicon carbide substrate, 2 is a silicon carbide epitaxial layer, 3 is a P-type deep trench region, 4 is a P-type doping region one, 5 is a P-type doping region two, 6 is a P-type doping region three, 7 is a P-type doping region four, 8 is a field oxygen, 9 is a Schottky contact metal, 10 is a front thickened metal, 11 is an inorganic passivation layer, 12 is an organic passivation layer, 13 is a back ohmic contact electrode, and 14 is a back thickened metal. DETAILED DESCRIPTION
[0033] The embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.
[0034] The following describes an embodiment of the utility model with reference to Figures 1-10;
[0035] A method for preparing a product to reduce test loss of a silicon carbide diode comprises the following steps:
[0036] Step S100, growing a silicon carbide epitaxial layer 2 on a silicon carbide substrate 1, referring to Figure 1 As shown;
[0037] Specifically, the thickness of the silicon carbide epitaxial layer 2 ranges from 5 to 30 um.
[0038] Step S200, etching a P-type deep trench 3 near the edge of the silicon carbide epitaxial layer 2 by dielectric film deposition, glue coating, photolithography, development, etching and other processes; Figure 2 As shown;
[0039] Specifically, the cross section of the P-type deep trench 3 is a rectangular structure, with a vertical depth of 2um to 5um and a lateral width of 2um to 5um.
[0040] Step S300, using an ion implantation process on the top surface of the silicon carbide epitaxial layer 2, sequentially preparing a P-type doping region 1 4, a P-type doping region 2 5, a P-type doping region 3 6 and a P-type doping region 4 7 extending downwards respectively;
[0041] Specifically, the dielectric film is deposited, coated, photolithographically, and developed to transfer the ion implantation pattern to the dielectric film, and then the P-type (aluminum ion) ion implantation area is produced through an etching process, wherein the P-type doping area 1 4 and the P-type doping area 2 5 use the same high-temperature ion implantation conditions (the implantation temperature is 450°C-550°C, and the implantation energy is 30KV-450KV). The P-type doping area 3 6 has a lower doping concentration and needs to re-produce the ion implantation window. The P-type doping area 4 7 needs to re-produce the ion implantation window and inject at a tilted angle, generally in the range of 4-10° ( Figure 3 At the middle angle α), a PN junction morphology is formed on both sides of the P-type deep trench 3, referring to Figure 3 As shown;
[0042] Specifically, the P-type doping region 3 6 is a device terminal JTE structure (junction terminal extension), which has the advantages of short terminal structure size and high withstand voltage efficiency, and is particularly suitable for silicon carbide high voltage diodes. Compared with the P-type doping region 1 4, the injection junction depth is deeper and the injection concentration is lower. The principle is to set a lightly doped P-type doping region 3 6 outside the main junction P-type doping region 2 5, and use the extension of the lightly doped P region to form a depletion layer with positive charge in the terminal region, thereby extending the peak electric field, alleviating the electric field concentration effect, and improving the device withstand voltage.
[0043] The doping concentration of the P-type doping region 1 4 is 1e17-1e18, and the depth is 0.6-1um. The benefit is that the device leakage current is reduced when the reverse high voltage is used. The doping concentration of the P-type doping region 2 5 and the P-type doping region 3 6 is 1e15-1e17, and the depth is 0.6-1.2um. The benefit is that a JTE structure is formed to improve the device withstand voltage. The doping concentration of the P-type doping region 4 7 is 1e17-1e18, and the depth is 0.6-1um. The benefit is that during the reverse high voltage test, the high electric field is transferred from the surface of the silicon carbide device to the inside of the silicon carbide epitaxial material to avoid sparking.
[0044] Step S400, a field oxide 8 is formed on the top surface of the silicon carbide epitaxial layer 2 by chemical vapor deposition. The field oxide 8 passes through the P-type doping region 2 5, the P-type doping region 3 6 and the P-type doping region 4 7 in sequence and then extends to the edge of the device. Figure 4 As shown;
[0045] The material of the field oxygen 8 is silicon dioxide.
[0046] Step S500, a layer of metal is sputtered on the top surface of the silicon carbide epitaxial layer 2, which passes through the P-type doping region 1 4 and the P-type doping region 2 5 in sequence and extends to the top surface of the field oxide 8. After annealing, a Schottky contact metal 9 is formed. The Schottky annealing temperature is generally 400°C-500°C; the thickness of the Schottky contact metal 9 ranges from 500A to 1500A; the metal is generally titanium or molybdenum; refer to Figure 5 As shown;
[0047] Step S600, sputtering a layer of aluminum metal on the Schottky contact metal 9 as an anode lead to form a front thickened metal 10 with a thickness of 2um-6um; Figure 6 As shown;
[0048] Step S700, making a passivation layer at the device terminal position, referring to Figure 7 and Figure 8 As shown;
[0049] The passivation layer extends from the top surface of the front thickened metal 10 to the device terminal, that is, starting from the left side of the terminal and ending at the edge of the chip, in order to protect the front contact metal and silicon carbide epitaxy when bonding the silicon carbide diode.
[0050] The passivation layer includes an inorganic passivation layer 11 and an organic passivation layer 12 arranged in sequence from bottom to top, the purpose of which is to insulate and protect the terminal, isolate water vapor, reduce thermal stress, etc. Figure 7 and Figure 8 shown.
[0051] Step S800, forming a back ohmic contact electrode 13 on the back side of the silicon carbide substrate 1, referring to Fig. 9 and depositing a thickened metal 14 on the ohmic contact electrode 13 to form a cathode to complete the device manufacturing, refer to Fig.10 shown.
[0052] A product for reducing test loss of a silicon carbide diode, comprising, from bottom to top, a back thickened metal 14, a back ohmic contact metal 13, a silicon carbide substrate 1, and a silicon carbide epitaxial layer 2;
[0053] The top surface of the silicon carbide epitaxial layer 2 is provided with:
[0054] A plurality of P-type doped regions 4 are provided, extending downward from the top surface of the silicon carbide epitaxial layer 2 and arranged at intervals;
[0055] The P-type doping region 2 5 extends downward from the top surface of the silicon carbide epitaxial layer 2 . The implantation conditions of the P-type doping region 2 5 and the P-type doping region 1 4 are consistent and can be implanted simultaneously.
[0056] A third P-type doping region 6 extends downward from the top surface of the silicon carbide epitaxial layer 2 and is connected to the side of the second P-type doping region 5; the vertical depth of the third P-type doping region 6 is greater than the vertical depth of the second P-type doping region 5;
[0057] The silicon carbide epitaxial layer 2 is provided with a P-type doping region 1 4, a P-type doping region 2 5 and a P-type doping region 3 6 extending downward from the top surface, wherein the P-type doping region 1 4 is used to reduce the reverse leakage of the device, and the P-type doping region 2 5 and the P-type doping region 3 6 are used as device terminals and bear a larger reverse voltage value through a shorter terminal size.
[0058] The P-type doping region four 7 extends downward from the top surface of the silicon carbide epitaxial layer 2, has a U-shaped cross-section, and is spaced apart from the P-type doping region three 6; the spacing between the P-type doping region three 6 and the P-type doping region four 7 is in the range of 5-30um, which increases the distance between the internal high electric field and the front metal during the reverse cp test to avoid sparks.
[0059] The P-type deep trench 3 for setting the P-type doping region 47 is located near the edge of the silicon carbide epitaxial layer 2. The purpose of the P-type doping region 47 is to transfer the high electric field from the surface of the silicon carbide device to the inside of the silicon carbide epitaxial material during CP testing, thereby avoiding sparking.
[0060] Field oxide 8, arranged on the top surface of the silicon carbide epitaxial layer 2, sequentially passes through the P-type doping region 2 5, the P-type doping region 3 6 and the P-type doping region 4 7, and then extends to the edge of the device;
[0061] The purpose of field oxygen 8 is to protect the surface of the epitaxial layer at the silicon carbide terminal during etching and to increase the reliability of the device during operation.
[0062] The Schottky contact metal 9 is arranged on the top surface of the silicon carbide epitaxial layer 2, passes through the P-type doping region 1 4 and the P-type doping region 2 5 in sequence, and then climbs to the top surface of the field oxide 8;
[0063] A front thickened metal 10 extending upward from the top surface of the Schottky contact metal 9;
[0064] The passivation layer extends from the top surface of the field oxide 8 toward the front thickened metal 10 , and climbs up to the top surface of the front thickened metal 10 .
[0065] The passivation layer includes an inorganic passivation layer 11 and an organic passivation layer 12 .
[0066] The preparation process of the utility model enables the chip to transfer the surface high electric field strength to a deeper epitaxial layer through the P-type deep trench 3 PN junction when conducting a reverse high-voltage CP test, and the high breakdown field strength dielectric filled in the trench is optimized through these two methods, and the sparking phenomenon is never avoided. The utility model solves the occurrence of the sparking phenomenon without increasing the chip terminal size and changing the wafer CP test machine, thereby reducing the loss cost of the product.
Claims
1. A product for reducing test loss of silicon carbide diodes, characterized in that: The device comprises, from bottom to top, a back thickening metal (14), a back ohmic contact metal (13), a silicon carbide substrate (1) and a silicon carbide epitaxial layer (2); The top surface of the silicon carbide epitaxial layer (2) is provided with: A plurality of P-type doped regions (4) extending downward from the top surface of the silicon carbide epitaxial layer (2) and arranged at intervals; A second P-type doped region (5) extending downward from the top surface of the silicon carbide epitaxial layer (2); The P-type doped region three (6) extends downward from the top surface of the silicon carbide epitaxial layer (2) and is connected to the side of the P-type doped region two (5); the vertical depth of the P-type doped region three (6) is greater than the vertical depth of the P-type doped region two (5); A P-type doped region four (7), extending downward from the top surface of the silicon carbide epitaxial layer (2), having a U-shaped cross-section, and spaced apart from the P-type doped region three (6); Field oxygen (8) is arranged on the top surface of the silicon carbide epitaxial layer (2), passes through the second P-type doping region (5), the third P-type doping region (6) and the fourth P-type doping region (7) in sequence, and then extends to the edge of the device; A Schottky contact metal (9) is arranged on the top surface of the silicon carbide epitaxial layer (2), passes through the P-type doping region 1 (4) and the P-type doping region 2 (5) in sequence, and then climbs to the top surface of the field oxide (8); A front thickened metal (10) extending upward from the top surface of the Schottky contact metal (9); The passivation layer extends from the top surface of the field oxide (8) in the direction of the front thickened metal (10), and climbs to the top surface of the front thickened metal (10).
2. A product for reducing silicon carbide diode test loss according to claim 1, characterized in that: The passivation layer comprises an inorganic passivation layer (11) and an organic passivation layer (12).
3. The product for reducing silicon carbide diode test loss according to claim 1, characterized in that: The thickness of the Schottky contact metal (9) ranges from 500 Å to 1500 Å.
4. The product for reducing silicon carbide diode test loss according to claim 1, characterized in that: The thickness of the front thickened metal (10) is 2um-6um.
5. The product for reducing silicon carbide diode test loss according to claim 1, characterized in that: The thickness of the silicon carbide epitaxial layer (2) is 5-30 um.