Planar gate silicon carbide VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) with separated current path

Abstract

The utility model provides a planar gate silicon carbide VDMOS with a separated current path. The planar gate silicon carbide VDMOS is characterized in that the lower side surface of a drift layer is connected to the upper side surface of a silicon carbide substrate; a shunting region and a blocking region are arranged in the drift layer, the blocking region is positioned above the shunting region, a lug boss is arranged on the drift layer, and the shunting region is positioned below the lug boss; the well region lower side is connected to the drift layer upper side; an N-type source region and a P-type source region are arranged on the well region, and the inner side surface of the P-type source region is connected to the outer side surface of the N-type source region; the lower side surface of the gate dielectric layer is connected with the well region and the protrusion; the source metal layer is respectively connected with the well region, the N-type source region and the P-type source region; the gate metal layer is connected to the gate dielectric layer; the upper side surface of the drain metal layer is connected to the lower side surface of the silicon carbide substrate; the UIS resistance of the device is improved through the structural design of the device, so that the avalanche breakdown resistance of the device is improved, and the impact of the drain voltage spike on the gate medium of the device is inhibited.

Description

Technical Field

[0001] The utility model relates to a planar gate silicon carbide VDMOS with a separated current path. Background Art

[0002] Silicon carbide VDMOS is a typical representative of silicon carbide power devices, and is widely used in electric vehicles, aerospace, power conversion, etc. In some special applications, such as aerospace, existing devices are easily affected by the external environment, resulting in avalanche breakdown and gate reliability problems. Utility Model Content

[0003] The technical problem to be solved by the utility model is to provide a planar gate silicon carbide VDMOS with a separated current path, improve the UIS resistance of the device by structural design of the device, so as to improve the device's avalanche breakdown resistance and suppress the impact of the drain voltage spike on the device gate dielectric.

[0004] The utility model is implemented as follows: a planar gate silicon carbide VDMOS with a separated current path, comprising:

[0005] Silicon carbide substrate,

[0006] A drift layer, wherein the lower side of the drift layer is connected to the upper side of the silicon carbide substrate; a shunt region and a blocking region are provided in the drift layer, wherein the blocking region is located above the shunt region; a convex portion is provided on the drift layer, and the shunt region is located below the convex portion;

[0007] A well region, wherein the lower side of the well region is connected to the upper side of the drift layer; an N-type source region and a P-type source region are arranged on the well region, and the inner side of the P-type source region is connected to the outer side of the N-type source region;

[0008] A gate dielectric layer, the lower side of which is connected to the well region and the protrusion respectively;

[0009] A source metal layer, wherein the source metal layer is respectively connected to the well region, the N-type source region and the P-type source region;

[0010] a gate metal layer, the gate metal layer being connected to the gate dielectric layer;

[0011] and a drain metal layer, wherein the upper side of the drain metal layer is connected to the lower side of the silicon carbide substrate.

[0012] The advantages of the utility model are:

[0013] 1. The utility model divides the current path of the VDMOS device into two left and right branches, thereby improving the UIS resistance of the device;

[0014] Second, a blocking region is constructed directly below the device gate to suppress the voltage drop caused by the drain voltage spike from extending to the device gate, thereby improving the reliability of the device;

[0015] 3. A shunt area is constructed inside the device structure to guide the electrons from the N-type source area of ​​the device to the shunt areas on the left and right sides through the two sides of the barrier area, thereby improving the UIS resistance of the device and reducing the on-resistance of the device;

[0016] 4. The source metal layer directly contacts the P-type source region and the well region to form a body diode, completing the freewheeling of the device during the non-conducting stage. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The present invention will be further described below in conjunction with the embodiments with reference to the accompanying drawings.

[0018] Figure 1 The utility model is a schematic diagram of a planar gate silicon carbide VDMOS with a separated current path.

[0019] Figure 2 The utility model is a flow chart of a method for preparing a planar gate silicon carbide VDMOS with a separated current path.

[0020] Figure 3 This is a process cross-section of a planar gate silicon carbide VDMOS with a separated current path according to the utility model. Figure 1 .

[0021] Figure 4 This is a process cross-section of a planar gate silicon carbide VDMOS with a separated current path according to the utility model. Figure 2 .

[0022] Figure 5 This is a process cross-section of a planar gate silicon carbide VDMOS with a separated current path according to the utility model. Figure 3 .

[0023] Figure 6 This is a process cross-section of a planar gate silicon carbide VDMOS with a separated current path according to the utility model. Figure 4 .

[0024] Figure 7 This is a process cross-section of a planar gate silicon carbide VDMOS with a separated current path according to the utility model. Figure 5 .

[0025] Figure 8 This is a process cross-section of a planar gate silicon carbide VDMOS with a separated current path according to the utility model. Figure 6 .

[0026] Fig. 9 This is a process cross-section of a planar gate silicon carbide VDMOS with a separated current path according to the utility model. Figure 7 .

[0027] Fig.10 This is a process cross-section of a planar gate silicon carbide VDMOS with a separated current path according to the utility model. Figure 8 .

[0028] Fig.11 This is a process cross-section of a planar gate silicon carbide VDMOS with a separated current path according to the utility model. Figure 9 . DETAILED DESCRIPTION

[0029] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0031] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0032] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0033] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0034] like Figure 1 As shown, the embodiment of the present application provides a planar gate silicon carbide VDMOS with a separated current path, including:

[0035] Silicon carbide substrate 1,

[0036] A drift layer 2, wherein the lower side of the drift layer 2 is connected to the upper side of the silicon carbide substrate 1; a shunt region 21 and a barrier region 22 are provided in the drift layer 2, wherein the barrier region 22 is located above the shunt region 21; a convex portion 23 is provided on the drift layer 2, wherein the shunt region 21 is located directly below the convex portion 23;

[0037] A well region 3, wherein the lower side of the well region 3 is connected to the upper side of the drift layer 2; an N-type source region 31 and a P-type source region 32 are arranged on the well region 3, and the inner side of the P-type source region 32 is connected to the outer side of the N-type source region 31;

[0038] A gate dielectric layer 4, the lower side of which is connected to the well region 3 and the protrusion 23 respectively;

[0039] A source metal layer 5, wherein the source metal layer 5 is respectively connected to the well region 3, the N-type source region 31 and the P-type source region 32;

[0040] A gate metal layer 6, wherein the gate metal layer 6 is connected to the gate dielectric layer 4;

[0041] And, a drain metal layer 7 , wherein the upper side of the drain metal layer 7 is connected to the lower side of the silicon carbide substrate 1 .

[0042] like Figures 2 to 11 As shown, the method for preparing the silicon carbide VDMOS comprises the following steps:

[0043] Step 1: depositing metal on the lower side of the silicon carbide substrate 1 to form a drain metal layer 7; epitaxially growing on the side of the silicon carbide substrate 1 to form a drift layer 2;

[0044] Step 2, forming a barrier layer a on the drift layer 2, etching the barrier layer a to form a through hole, and performing ion implantation into the drift layer 2 to form a shunt region 21, wherein the ion implantation energy is 370-470kev;

[0045] Step 3, removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a, forming a through hole, and performing ion implantation into the drift layer 2 to form a barrier region 22, wherein the ion implantation energy is 200-300kev;

[0046] Step 4: remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a, form a through hole, and perform ion implantation into the drift layer 2 to form a well region 3 and a protrusion 23, wherein the ion implantation energy is 10-200 keV;

[0047] Step 5, remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a, form a through hole, perform ion implantation into the well region 3, form an N-type source region 31, and the ion implantation energy is 10-100kev;

[0048] Step 6: remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, and perform ion implantation into the well region 3 to form a P-type source region 32, with the ion implantation energy being 10-100 keV;

[0049] Step 7, removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a, forming a through hole, depositing an insulating dielectric, and forming a gate dielectric layer 4;

[0050] Step 8, removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a, forming a through hole, depositing metal, and forming a gate metal layer 6;

[0051] Step 9: remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a, form a through hole, deposit metal, and form a source metal layer 5.

[0052] The silicon carbide substrate 1 is N-type, the drift layer 2 is N-type, the shunt region 21 is N-type, the barrier region 22 is P-type, and the well region 3 is P-type; the doping concentration of the silicon carbide substrate 1 is 2e18cm -3 The doping concentration of the drift layer 2 is 5e16cm -3 The doping concentration of the shunt region 21 is 6e17cm -3 The doping concentration of the barrier region 22 is 5e16cm -3 The doping concentration of the P-type source region 32 is 5e18cm -3 The doping concentration of the P-type well region 3 is 1e17 cm -3 The doping concentration of the N-type source region 31 is 2e18cm -3 ; The gate dielectric layer 4 is silicon dioxide; the gate metal layer 6, the source metal layer 5 and the drain metal layer 7 are all Al; the thickness of the N-type silicon carbide substrate 1 of the device is 1μm, the thickness of the N-type drift layer 2 is 10-20μm, the thickness of the N-type shunt region 21 is 300nm, the distance between the upper side of the shunt region 21 and the lower side of the well region 3 is 500nm, the thickness of the P-type barrier region 22 is 300nm, the upper side of the barrier region 22 and the lower side of the P-type well region 3 are located in the same plane, the distance from the lower side of the P-type well region 3 to the lower side of the N-type source region 31 and the lower side of the P-type source region 32 are both 300nm, the lower side of the P-type well region 3 to the lower side of the gate dielectric layer 4 and The distance between the lower side of the source metal layer 5 is 600nm, the thickness of the P-type source region 32 is 300nm, the thickness of the N-type source region 31 is 300nm, the thickness of the source metal layer 5 is 300nm, the thickness of the gate dielectric layer 4 is 20nm, the thickness of the gate metal layer 6 is 280nm, and the device withstand voltage is 800-1200V; the concentration of the N-type silicon carbide substrate 1 is to form a low-resistance ohmic contact with the drain metal layer 7 to reduce the on-resistance of the device. Its thickness is based on the design conditions of the device epitaxial thickness (N-type drift layer 2) to ensure support and improve process stability. The thickness and doping concentration of the N-type drift layer 2 are a compromise between on-resistance and withstand voltage;

[0053] The N-type shunt region 21 and the P-type barrier region 22 have two purposes: one is to realize the shunting of the left and right sides of the internal current of the device when the device is turned on, thereby improving the UIS resistance of the device; the other is to suppress the impact of the voltage spike on the device gate through the P-type barrier region 22 when a voltage spike appears at the drain of the device when the device is turned off, thereby improving the reliability of the device;

[0054] When the device is turned off, the gate and source are at zero voltage, and the device drain is connected to a high potential. Under different working conditions, the device drain voltage fluctuates widely. When a voltage spike appears at the device drain, a space charge region is generated that diffuses from the drain to the device gate. When the traditional structure does not have a P-type barrier layer 22, the electric field diffuses upward and easily impacts the device's gate dielectric, affecting the device's reliability. The utility model can effectively suppress the impact of the leakage voltage spike on the gate dielectric by adding a P-type barrier layer 22.

[0055] When a positive voltage is applied to the device gate, the P-type well region 3 is inverted to form an N-type electron channel near the area below the gate. Electrons flow from the N-type source region 31 along the inversion channel to the bottom of the device gate, and then flow to the device drain. At the P-type barrier region 22 of the device, the electrons are shunted from the left and right sides to the N-type shunt regions 21 on the left and right sides, and then flow to the drain of the device, thereby realizing the shunting of the device and improving the UIS characteristics of the device.

[0056] Although the specific implementation methods of the present invention are described above, those skilled in the art should understand that the specific embodiments described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A planar gate silicon carbide VDMOS with separated current paths, characterized in that: include: Silicon carbide substrate, A drift layer, wherein the lower side of the drift layer is connected to the upper side of the silicon carbide substrate; A shunt region and a blocking region are provided in the drift layer, wherein the blocking region is located above the shunt region, a convex portion is provided on the drift layer, and the shunt region is located below the convex portion; A well region, wherein the lower side of the well region is connected to the upper side of the drift layer; an N-type source region and a P-type source region are arranged on the well region, and the inner side of the P-type source region is connected to the outer side of the N-type source region; A gate dielectric layer, the lower side of which is connected to the well region and the protrusion respectively; A source metal layer, wherein the source metal layer is respectively connected to the well region, the N-type source region and the P-type source region; a gate metal layer, the gate metal layer being connected to the gate dielectric layer; and a drain metal layer, wherein the upper side of the drain metal layer is connected to the lower side of the silicon carbide substrate.

2. A planar gate silicon carbide VDMOS with separated current paths as claimed in claim 1, characterized in that: The thickness of the shunt region is 300 nm, and the distance between the upper side of the shunt region and the lower side of the well region is 500 nm.

3. The planar gate silicon carbide VDMOS with separated current paths according to claim 1, characterized in that: The thickness of the blocking region is 300 nm, and the upper side of the blocking region and the lower side of the well region are located in the same plane.

4. The planar gate silicon carbide VDMOS with separated current paths according to claim 1, characterized in that: The silicon carbide substrate is of N type, the drift layer is of N type, the shunt region is of N type, the barrier region is of P type, and the well region is of P type.

5. The planar gate silicon carbide VDMOS with separated current paths according to claim 1, characterized in that: The doping concentration of the shunt region is greater than the doping concentration of the drift layer.

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