Semiconductor device

Abstract

The utility model provides a semiconductor device. A semiconductor device (having a VFET structure) includes: first and second active regions (AR); first and second metal pair gate (MG) contacts adjacent to the channel regions of the first and second AR; a metal pair source / drain (MD) contact and a buried MD (BMD) contact coupled to the corresponding first and second S / D regions of the first and second ARs, respectively; and a metal-to-polycrystalline silicon (MP) contact located at the same level as the MG contact and extending between and coupling the first and second MG contacts together; relative to the first direction, the first AR and the second AR are substantially aligned; and at least a portion of the MP contact extends substantially beyond each of the first and second ARs with respect to a vertical second direction.

Description

Technical Field

[0001] The utility model relates to a semiconductor device. Background Art

[0002] The semiconductor integrated circuit (IC) industry produces a wide variety of analog and digital devices to solve problems in a number of different fields. The development of semiconductor process technology nodes has gradually reduced component size and tightened spacing, thereby increasing transistor density. ICs have become smaller and smaller. Utility Model Content

[0003] The utility model provides a semiconductor device (having a vertical field effect transistor (VFET) architecture), comprising: an active region (AR), comprising a first AR and a second AR separated relative to a first direction, the first AR and the second AR each having a channel axis extending in a second direction perpendicular to the first direction, and each having a channel region located between a selected portion of an overlying first source / drain (S / D) region and a selected portion of an underlying second S / D region relative to the second direction; a metal-to-gate (MG) contact, comprising a first MG contact and a second MG contact respectively adjacent to the channel region of the first AR and the channel region of the second AR and separated relative to the first direction; a metal-to-source / drain (MD) contact and a buried An MD (BMD) contact, which is correspondingly coupled to the corresponding first S / D region and the second S / D region of the first AR and the corresponding first S / D region and the second S / D region of the second AR with respect to the second direction; and a metal-to-polysilicon (MP) contact, which is located at the same level as the MG contact with respect to the second direction, and extends between the first MG contact and the second MG contact with respect to the first direction and couples the first MG contact and the second MG contact together; with respect to a third direction perpendicular to each of the first direction and the second direction, the first AR and the second AR are substantially aligned; and with respect to the third direction, at least a portion of the MP contact substantially extends beyond each of the first AR and the second AR.

[0004] The utility model provides a semiconductor device, comprising: an active region (AR), comprising a first AR, a second AR and a third AR, wherein the first AR, the second AR and the third AR each have a channel axis extending in a first direction, and each have a channel region located between a selected portion of an overlying first source / drain (S / D) region and a selected portion of an underlying second S / D region relative to the first direction, each of the ARs having a width axis extending in a second direction perpendicular to the first direction, and a thickness axis extending in a third direction perpendicular to the first direction and the second direction, and the width axis of the AR is aligned with a corresponding β reference track (β track) extending parallel to the second direction, so that The first AR is aligned with the first β track, and each of the second AR and the third AR is aligned with the second β track; a metal-to-gate (MG) contact, including a first MG contact, a second MG contact, and a second MG contact adjacent to the channel region of the first AR, the channel region of the second AR, and the channel region of the third AR, respectively; a metal-to-source / drain (MD) contact, including a first MD contact and a second MD contact, the first MD contact and the second MD contact are located on the first S / D region of the first AR and the first S / D region of the second AR and are coupled to the first S / D region of the first AR and the first S / D region of the second AR, respectively; a buried MD (BMD) contact contacts, including a first BMD contact and a second BMD contact, the first BMD contact and the second BMD contact are located below the second S / D region of the first AR and the second S / D region of the second AR and are coupled to the second S / D region of the first AR and the second S / D region of the second AR respectively; a metal-to-polycrystalline silicon (MP) contact, located at the same level as the MG contact relative to the second direction, the MP contact including a first metal-to-polycrystalline silicon (MP) contact and a second metal-to-polycrystalline silicon (MP) contact extending between the first MG contact and the second MG contact relative to the first direction and coupling the first MG contact and the second MG contact together; The M_1st segment in the _1st metallization layer has a long axis extending in the third direction and is aligned correspondingly with the α reference track (α track) extending in the third direction, the M_1st segment includes a first M_1st segment and a second M_1st segment aligned correspondingly with the adjacent first α track and second α track; and a through-hole pair M_1st (V_1st) contact, including a first V_1st contact and a second V_1st contact, the first V_1st contact and the second V_1st contact are located above the first M_1st segment and the second M_1st segment, aligned correspondingly with the first α track and the second α track and aligned with the first of the β tracks (the first β track).

[0005] In order to make the above features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figures 1A to 1D is a three-quarter perspective view of a corresponding semiconductor device according to some embodiments.

[0007] FIG. 2A to FIG. 2B is a layout diagram of a corresponding stretched coupling region according to some embodiments.

[0008] FIG. 3A to FIG. 3H is a layout diagram of a corresponding semiconductor device including one or more stretched MP contacts according to some embodiments.

[0009] Figure 4 and FIG. 5A to FIG. 5D is a layout diagram of a corresponding semiconductor device according to some embodiments.

[0010] Figure 6 to Figure 7 is a flow chart of a corresponding method of manufacturing a memory device according to some embodiments.

[0011] Figure 8 is a block diagram of an electronic design automation (EDA) system according to some embodiments.

[0012] Fig. 9 is a block diagram of an integrated circuit (IC) manufacturing system and an IC manufacturing flow associated with the IC manufacturing system according to some embodiments. DETAILED DESCRIPTION

[0013] The following disclosure discloses many different embodiments or examples for implementing different features of the subject matter. The following describes examples of components, materials, values, steps, operations, arrangements, etc. to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. It is expected that there are other components, values, operations, materials, arrangements, etc. For example, the following description forms a first feature on a second feature or on a second feature, including an embodiment in which the first feature and the second feature are formed to be in direct contact, and further includes an embodiment in which an additional feature is formed between the first feature and the second feature so that the first feature and the second feature are in indirect contact. In addition, the present disclosure reuses reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than indicating the relationship between the various embodiments and / or configurations discussed by itself.

[0014] In addition, for ease of description, spatially relative terms such as "beneath", "below", "lower", "above", "upper", etc. are used herein to describe the relationship between one element or feature shown in the figure and another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figure. The device has other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein are also interpreted accordingly. In some embodiments, the term standard cell structure refers to a standardized building block included in a library of various standard cell structures. In some embodiments, various standard cell structures are selected from a library of standard cell structures and the various standard cell structures are used as components in a layout diagram representing a circuit.

[0015] In some embodiments, a semiconductor device includes a metal-oxide field-effect transistor (MOSFET) having a vertical structure (vertical field-effect transistor (VFET)), the semiconductor device including: a metal-to-gate (MG) contact, including a first MG contact and a second MG contact adjacent to a channel region of a first active region (AR) and a channel region of a second AR, respectively, the first AR and the second AR are respectively surrounded by the first MG contact and the second MG contact; a metal-to-source / drain (MD) contact and a buried MD (buried MD) contact; The invention relates to a method of manufacturing a 3D optical fiber optical fiber contact comprising: a 3D optical fiber contact (3D optical fiber contact) and a 3D optical fiber contact (3D optical fiber contact) for coupling the first AR to the second AR; a 3D optical fiber contact (3D optical fiber contact) for coupling the first AR to the second AR; a 3D optical fiber contact (3D optical fiber contact) for coupling the first AR to the second AR; and a 3D optical fiber contact (3D optical fiber contact) for coupling the first AR to the second AR. The method comprises: providing a 3D optical fiber contact (3D optical fiber contact) for coupling the first AR to the second AR; a 3D optical fiber contact (3D optical fiber contact) for coupling the first AR to the second AR; and a 3D optical fiber contact (3D optical fiber contact) for coupling the first AR to the second AR. The method comprises: providing a 3D optical fiber contact (3D optical fiber contact) for coupling the first AR to the second AR; and a 3D optical fiber contact (3D optical fiber contact) for coupling the first AR to the second AR. The method comprises: providing a 3D optical fiber contact (3D optical fiber contact) for coupling the first AR to the second AR; and a 3D optical fiber contact (3D optical fiber contact) for coupling the second AR to the first ... Any additional couplings to the first MG contact and the second MG contact (e.g., to the third MG contact or another component) must be routed through one or more segments in the first metallization layer, which increases signal routing congestion in the first metallization layer. The extended shape of the stretched MP contact according to some embodiments reduces routing congestion by facilitating additional use of the stretched MP contact for one or more additional MG contacts or another component, compared to other approaches.

[0016] Figure 1A and Figure 1C 1 is a three-quarter exploded perspective view of corresponding semiconductor devices 100 ( 1 ) and 100 ( 2 ) according to some embodiments.

[0017] Figure 1A and Figure 1C And the same Figure 1B and Figure 1D It is assumed (discussed below) that the first, second, and third orthogonal directions are, for example, parallel to the X-axis, the Y-axis, and the Z-axis, respectively. Figure 1A The illustrated device 100 ( 1 ) exhibits a M0HM1V architecture in which: the first metallization layer M0 has conductive segments whose long axes extend parallel to the X-axis; and the second metallization layer M1 has conductive segments whose long axes extend parallel to the Y-axis.

[0018] exist Figures 1A to 1D 1, and similarly in other figures of this document, it is assumed that the numbering convention is to label the first metallization layer (i.e., MET_1st) as M0, and correspondingly label the first interconnect layer (VIA_1st layer) as interconnect layer zero (VIA_0). Therefore, the segment in the MET_1st layer is the M_1st segment M0 116. In some embodiments, depending on the numbering convention of the corresponding process node of the manufacturing apparatus 100(1), the MET_1st layer is the metallization layer one (M1), and correspondingly, the VIA_1st layer is the interconnect layer one (VIA1).

[0019] Figure 1A It is an exploded view relative to the Y axis. Therefore, the device 100 (1) is divided into a partition 101A (1), a partition 101A (2), and a partition 101A (3) separated relative to the Y axis, wherein the partition 101A (2) is located between the partition 101A (1) and the partition 101A (3).

[0020] Each of the partitions 101A(1) and 101A(3) includes a metal oxide field effect transistor (MOSFET) having a vertical architecture (VFET), wherein such MOSFETs are referred to herein as VFETs. Partition 101A(1) includes VFETs 102A(1) and 102A(2). Partition 101A(3) includes VFETs 102A(3) and 102A(4).

[0021] VFET 102A(1) will be discussed as an example of VFETs 102A(1) to 102A(4). VFET 102A(1) includes an example of active region 104. Figure 1A Assume that each instance of AR 104 is composed of an instance of nanowire 106. In some embodiments, an instance of AR 104 is composed of one or more nanosheets. Returning to VFET 102A(1), and with respect to the Z-axis, a central region of an instance of AR 104 is surrounded by a metal-to-gate (MG) contact 108(1), wherein a suitable gate insulation layer (not shown) is disposed between the central region of the instance of AR 104 and the MG contact 108(1).

[0022] Relative to the Z-axis, the portion of the instance of nanowire 106 that overlaps the MG contact 108(1) represents a channel portion of the instance of nanowire 106, and the channel portions of the instance of nanowire 106 together represent a channel region of VFET 102A(1). The upper region of the instance of nanowire 106 located above the MG contact 108(1) represents an instance of a first source / drain (S / D) region. The lower region of the instance of nanowire 106 located below the MG contact 108(1) represents an instance of a second S / D region. In some embodiments, the upper region and the lower region of the nanowire are doped with impurities to form a corresponding instance of a first S / D region and a corresponding instance of a second S / D region.

[0023] VFET 102A(1) includes MG contact 108(1), while VFET 102A(2) in subarea 101A(1) includes MG contact 108(2). Similarly, in subarea 101A(3), VFET 102A(3) includes MG contact 108(3), while VFET 102A(4) includes MG contact 108(4).

[0024] Returning to VFET 102A(1), the upper end of the instance of nanowire 106 is adjacent to and coupled to the instance of MD contact 110. The alphabetic text string "MD" is used as a convenient label. In some embodiments, "MD" is an acronym for "metal-to-S / D." Relative to the Z-axis, there is a gap between the instance of MD contact 110 and the MG contact 108(1). The lower end of the instance of nanowire 106 is adjacent to and coupled to the first end region of the instance of BMD contact 112. The instance of BMD contact 112 is located on the opposite side of MG contact 108(1) as the instance of MD contact 110. The alphabetic text string "BMD" is used as a convenient label. In some embodiments, "BMD" is an acronym for "buried MD," where MD is an acronym for "metal-to-S / D." In such an embodiment, the adjective "buried" is intended to imply that the instance of the BMD contact 112 is located below the instance of the AR 104 relative to the Z-axis. Relative to the Z-axis, there is a gap between the instance of the BMD contact 112 and the MG contact 108(1).

[0025] exist Figure 1A, with respect to VFET 102A(1), located on and coupled to MD contact 110 is an instance of VD contact 114. The alphabetic text string "VD" is used as a convenient label. In some embodiments, "VD" is an acronym for "via-to-MD." An instance of conductive M0 segment 116 in first metallization layer M0 is located on and coupled to an instance of VD contact 114. An instance of V0 contact 120 is located on and coupled to an instance of M0 segment 116. The alphabetic text string "V0" is used as a convenient label. In some embodiments, "V0" is an acronym for "VIA0-to-M0." An instance of conductive M1 segment 122 in metallization layer M1 is located on and coupled to an instance of V0120.

[0026] exist Figure 1A , VFET 102A(1) and similarly with respect to VFET 102A(3) have additional structures coupled thereto that are not coupled to VFET 102A(2) or VFET 102A(4), respectively. With respect to VFET 102A, located below and coupled to an instance of BMD 112 is an instance of a conductive buried segment 118 in a first buried metallization layer BM0. An instance of a BPD contact 128 is located above and coupled to an instance of BMD contact 112. The alphabetic text string "BPD" is used as a convenient label. In some embodiments, "BPD" is an acronym for "buried PD," where "PD" is an acronym for "MP-to-BMD."

[0027] With respect to VFET 102A(1), an instance of basic-MP contact 123 is located on and coupled to an instance of BPD contact 128. The alphabetic text string "MP" is used as a convenient label. In some embodiments, "MP" is an acronym for "metal-to-poly" because the corresponding contacts were historically used to couple metallization segments to gate segments, which historically were typically formed of polysilicon. Here, the basic MP contact is a first type of MP contact, while the extended MP contact 124 (discussed below) is a second type of MP contact. The adjectives "basic" and "extended" are convenient labels applied to MP contacts 123 and 124, respectively. The instance of basic MP contact 123 is formed in the same layer as MG contact 108(1).

[0028] exist Figure 1A, with respect to VFET 102A(1), an instance of MV contact 126 is located on and coupled to an instance of base MP contact 123. The alphabetic text string "MV" is used as a convenient label. In some embodiments, "MV" is an acronym for "VG-to-MP," where VG is discussed below. An instance of VG 130 is located on and coupled to an instance of MV contact 126. The alphabetic text string "VG" is used as a convenient label. In some embodiments, "VG" is an acronym for "via-to-gate." An instance of conductive M0 segment 116 in first metallization layer M0 is located on and coupled to VG 130.

[0029] exist Figure 1A , the long axis of an instance of nanowire 106 extends parallel to the Z axis. Thus, the channel axis of each instance of AR 104 extends parallel to the Z axis. Each instance of AR 104 has a width axis extending parallel to the Y axis, and a thickness axis extending parallel to the X axis.

[0030] Figure 1A The illustrated partition 101A(2) includes an extended MP contact 124. With respect to partitions 101A(1) to 101A(3) relative to each other, reference lines 131(1), 131(2), 131(3), and 131(4) are shown at Figure 1A 1 and 108 (3). The upper left edge of each of the MG contacts 108 (1) of the partition 101A (1), the extended MP contacts 124 of the partition 101A (2), and the MG contacts 108 (3) of the partition 101A (3) is aligned with the reference line 131 (1). The lower right edge of each of the MG contacts 108 (1) of the partition 101A (1) and the MG contacts 108 (3) of the partition 101A (3) is aligned with the reference line 131 (2). The upper left edge of each of the MG contacts 108 (2) of the partition 101A (1) and the MG contacts 108 (4) of the partition 101A (3) is aligned with the reference line 131 (3). The lower right edge of each of the MG contact 108 ( 2 ) of partition 101A( 1 ), the extended MP contact 124 of partition 101A( 2 ), and the MG contact 108 ( 4 ) of partition 101A( 3 ) is aligned with reference line 131 ( 4 ).

[0031] When the lower right edge of each of MG contact 108(2), extended MP contact 124, and MG contact 108(4) is aligned with reference line 131(4), at least a portion of extended MP contact 124 substantially extends beyond each of the instances of AR 104 associated with MG contact 108(1) and the instances of AR 104 associated with MG contact 108(3), relative to the X-axis. In addition, at least a portion of extended MP contact 124 overlaps each of the instances of AR 104 associated with MG contact 108(2) and the instances of AR 104 associated with MG contact 108(4), relative to the X-axis.

[0032] In addition to the extended MP contact 124, partition 101A(2) further includes the following instances: an instance of an MV contact 126, located on and coupled to the extended MP contact 123; an instance of VG 130, located on and coupled to an instance of the MV contact 126; an instance of the M0 segment 116, located on and coupled to VG130; an instance of the V0 contact 120, located on and coupled to an instance of the M0 segment 116; and an instance of the M1 segment 122, located on and coupled to an instance of V0120.

[0033] In the discussion Figure 1B Before that, let’s briefly discuss Figure 1C . Figure 1C Similar to Figure 1A For the sake of brevity, the discussion will focus more on Figure 1C and Figure 1A The differences between Figure 1C , device 100(2) exhibits a M0VM1H architecture, and Figure 1A The device 100 (1) shown shows a M0HM1V architecture. Figure 1C The M0VM1H architecture of the device 100(2) shown in FIG. 1 includes a first metallization layer M0 having a segment whose long axis extends parallel to the Y axis, and a second metallization layer M1 having a segment whose long axis extends parallel to the X axis. The device 100(2) is divided into a partition 101C(1), a partition 101C(2), and a partition 101C(3) separated relative to the Y axis, wherein the partition 101C(2) is located between the partition 101C(1) and the partition 101C(3).

[0034] Figure 1B and Figure 1D According to some embodiments, Figure 1A and Figure 1C A simplified version of .

[0035] More specifically, according to some embodiments, Figure 1B and Figure 1D 1 is a three-quarter perspective view of corresponding stretch-coupling regions 132 ( 1 ) and 132 ( 2 ) coupled via the stretched MP contacts 124 of semiconductor devices 100 ( 1 ) and 100 ( 2 ), respectively.

[0036] Each of the extended coupling regions 132(1) and 132(2) includes: an extended MP contact 124; a corresponding instance of the MV contact 126; a corresponding instance of the VG 130; a corresponding instance of the M0 segment 116; a corresponding instance of the V0 contact 120; a corresponding instance of the M1 segment 122; and MG contacts 108(1)-108(4). Figure 1A The device 100(1) shown has a M0HM1V architecture, so Figure 1B The example of the M1 segment 122 in the extended coupling region 132(1) shown has a major axis extending parallel to the X-axis. Figure 1C The device 100(2) shown has a M0VM1H architecture, so Figure 1D The example of the M1 segment 122 in the extended coupling region 132(2) shown has a major axis extending parallel to the Y-axis.

[0037] exist Figure 1B and Figure 1D In each of the MG contacts 108(1) to 108(4), the extended MP contact 124 couples each of the MG contacts 108(1) to 108(4) to each other. The extended MP contact 124 provides coupling with respect to the Y axis, for example, by coupling the MG contact 108(1) to the MG contact 108(3), by coupling the MG contact 108(1) to the MG contact 108(4), by coupling the MG contact 108(3) to the MG contact 108(2), or by coupling the MG contact 108(2) to the MG contact 108(4). The extended MP contact 124 provides coupling relative to the X-axis, for example, by coupling the MG contact 108(1) to the MG contact 108(2), by coupling the MG contact 108(1) to the MG contact 108(4), by coupling the MG contact 108(3) to the MG contact 108(4), or by coupling the MG contact 108(3) to the MG contact 108(2).

[0038] FIG. 2A to FIG. 2B The invention includes the extended coupling regions 232I, 232T, 232P, 232L and 232Z according to some embodiments. Figure 2A ) and 232H, 232_4, 232U and 232F ( Figure 2B)’s corresponding layout diagram.

[0039] FIG. 2A to FIG. 2B Each of the extended coupling regions shown is Figure 1B The extended coupling region 132(1) or Figure 1D An example of an extended coupling region 132(2) is shown. FIG. 2A to FIG. 2B The layout diagram shown follows the Figure 1B and Figure 1D The numbering scheme is similar to the numbering scheme of . FIG. 2A to FIG. 2B It is assumed that the first orthogonal direction, the second orthogonal direction and the third orthogonal direction are, for example, parallel to the X-axis, the Y-axis and the Z-axis respectively.

[0040] The extended coupling region 232I includes: an extended MP contact 224I; and MG contacts 208 ( 1 ), 208 ( 2 ), 208 ( 3 ), and 208 ( 4 ) surrounding corresponding instances of the AR 204 .

[0041] The extended MP contact 224I has an I shape, i.e., a shape similar to the capital letter I. In some embodiments, the capital letter I is described as having only a stem. In some embodiments, the capital letter I is described as having a stem and a truncated upper arm and a lower arm, the central area of ​​the upper arm and the central area of ​​the lower arm intersecting the stem. In the default orientation of the capital letter I, the long axis of the stem of the capital letter I extends parallel to the Y axis. In the extended coupling region 232I, the long axis of the extended MP contact 224I (i.e., the long axis of the stem of the capital letter I) has been rotated 90 degrees (90°) clockwise or counterclockwise relative to the long axis of the stem of the capital letter I with the default orientation. In some embodiments, the extended MP contact 224I is referred to as a tetragon, a rectangle, or a quadrilateral polygon. The extended MP contact 224I is an example of a convex polygon.

[0042] The I-shaped extended MP contact 224I extends between the MG contact 208 ( 1 ) and the MG contact 208 ( 3 ); extends between the MG contact 208 ( 2 ) and the MG contact 208 ( 4 ); and couples the MG contacts 208 ( 1 ) to 208 ( 4 ) to each other.

[0043] With respect to the X-axis, the MG contact 208(1) is aligned with the MG contact 208(3). With respect to the X-axis, the MG contact 208(2) is aligned with the MG contact 208(4). With respect to the Y-axis, the MG contact 208(1) is aligned with the MG contact 208(2). With respect to the Y-axis, the MG contact 208(3) is aligned with the MG contact 208(4).

[0044] In the extended coupling region 232I, the centerlines of the instances of AR 204 are parallel to the Y axis. The centerline-to-centerline distance between the instances of AR 204 respectively surrounded by the MG contacts 208(3) and 208(4) (i.e., the pitch between the instances of AR 204 respectively surrounded by the MG contacts 208(3) and 208(4)) has a value of 1*P, where P represents the uniform centerline-to-centerline distance between adjacent instances of AR 204 for the corresponding semiconductor process technology node. The pitch between the instances of AR 204 respectively surrounded by the MG contacts 208(3) and 208(4) is 1*P. In some embodiments, the pitch between the instances of AR 204 respectively surrounded by the MG contacts 208(3) and 208(4) is N*P, where N is a positive integer and 2≤N.

[0045] With respect to the Y axis, the MG contact 208(1) is separated from the MG contact 208(3) by a gap 234. With respect to the Y axis, the MG contact 208(1) is separated from the MG contact 208(4) by a gap 234. With respect to the Y axis, the MG contact 208(2) is separated from the MG contact 208(4) by a gap 234. With respect to the Y axis, the MG contact 208(3) is separated from the MG contact 208(2) by a gap 234.

[0046] exist FIG. 2A to FIG. 2B In the embodiment, the gap 234 has a size W, which is a uniform distance of the corresponding semiconductor process technology node. In some embodiments, W represents the size of the minimum AR 204 produced by the corresponding semiconductor process technology node.

[0047] With respect to the X-axis, the MG contact 208(1) is separated from the MG contact 208(2) by a gap 236. With respect to the X-axis, the MG contact 208(1) is separated from the MG contact 208(4) by a gap 236. With respect to the X-axis, the MG contact 208(3) is separated from the MG contact 208(2) by a gap 236. With respect to the X-axis, the MG contact 208(3) is separated from the MG contact 208(4) by a gap 236.

[0048] exist Figure 2A , the extended coupling region 232T includes: an extended MP contact 224T; and MG contacts 208(1) and 208(3) surrounding corresponding instances of AR 204. Compared to the extended coupling region 232I, the extended coupling region 232T lacks the MG contacts 208(2) and 208(4) and the instances of AR 204 surrounded by the MG contacts 208(2) and 208(4).

[0049] The extended MP contact 224T has a T-shape, that is, a shape similar to a capital letter T. The capital letter T has a column that intersects a central region of the arm. In a preset orientation of the capital letter T, the long axis of the column of the capital letter T extends parallel to the Y axis, and the long axis of the arm extends parallel to the X axis. The arm intersects a first end of the column. In the extended coupling region 232T, the T-shape of the MP contact 224T has a first orientation that is rotated counterclockwise by approximately 90 degrees relative to the preset orientation of the T shape.

[0050] The arms of the T-shaped extended MP contact 224T couple the MG contact 208(1) with the MG contact 208(3). The posts of the T-shaped extended MP contact 224T substantially extend beyond each of the MG contacts 208(2) and 208(4) relative to the X-axis. In some embodiments, the extended MP contact 224T is described as an octagon. In some embodiments, the extended MP contact 224T is described as a concave polygon.

[0051] exist Figure 2A 2, the extended coupling region 232P includes: an extended MP contact 224P; MG contacts 208(1), 208(3), and 208(4) surrounding corresponding instances of AR 204; instances of base MP contact 223; and instances of MV contact 226 located above instances of base MP contact 223. Compared to the extended coupling region 232I, the extended coupling region 232T lacks MG contact 208(2) and instances of AR 204 surrounded by MG contact 208(2). Instances of base MP contact 223 utilize space not occupied by the missing MG contact 208(2).

[0052] The extended MP contact 224P has a P shape, i.e., a shape similar to a capital letter P. The capital letter P has a column and an arm. In the preset orientation of the capital letter P, the column is parallel to the Y axis, the arm is parallel to the X axis; and the arm extends to the right of the column relative to the X axis. The arm intersects with the first end of the opposite column. The P shape of the MP contact 224P has a first orientation that is rotated about 90 degrees clockwise relative to the preset orientation of the P shape. With respect to the symmetry axis of the P shape that is parallel to the long axis of the column of the P shape (i.e., parallel to the Y axis) in the preset orientation of the P shape, the first orientation of the P shape of the extended MP contact 224P is also mirror-symmetric with respect to the P shape with the preset orientation.

[0053] The P-shaped posts of the extended MP contact 224P are coupled to the MG contacts 208(3) and 208(4). The P-shaped arms of the extended MP contact 224P are coupled to the MG contacts 208(1) and 208(3). In some embodiments, the extended MP contact 224P is illustrated as a hexagon. In some embodiments, the extended MP contact 224P is illustrated as a concave polygon.

[0054] exist Figure 2A , the extended coupling region 232L includes: an extended MP contact 224L; MG contacts 208(1) and 208(4) surrounding corresponding instances of AR 204; an instance of base MP contact 223; and an instance of MV contact 226 located above the instance of base MP contact 223. Compared to the extended coupling region 232I, the extended coupling region 232L lacks MG contacts 208(2) and 208(3) and the instance of AR 204 surrounded by MG contacts 208(2) and 208(3). The instance of base MP contact 223 utilizes the space not occupied by the missing MG contact 208(2).

[0055] In extended coupling region 232L, the pitch between instances of AR 204 respectively surrounded by MG contacts 208(1) and 208(4) is 1*P. In some embodiments, the pitch between instances of AR 204 respectively surrounded by MG contacts 208(1) and 208(4) is N*P.

[0056] The extended MP contact 224L has an L shape, that is, a shape similar to a capital letter L. The capital letter L has a column and an arm. In the preset orientation of the capital letter L, the column is parallel to the Y axis, the arm is parallel to the X axis, and the arm extends from the first end of the column to the right side of the column relative to the X axis. In some embodiments, the silhouette of the L-shaped arm of the extended MP contact 224L is considered to include the arm of the extended MP contact 224L itself plus a borrowed portion 238 (1) of the MG contact 208 (4). The L shape of the MP contact 224L has a first orientation that is rotated about 90 degrees clockwise relative to the preset orientation. The first orientation of the extended MP contact 224L is mirror-symmetric about the preset orientation of the capital letter L relative to the symmetry axis that is parallel to the column of the capital letter L in the preset orientation of the capital letter L.

[0057] The L-shaped post of the extended MP contact 224L is coupled to the MG contact 208 (1). The L-shaped arm of the extended MP contact 224L is coupled to the MG contact 208 (4). Figure 2A2 , the extended coupling region 232Z includes: an extended MP contact 224Z; MG contacts 208(1) and 208(4) surrounding corresponding instances of AR 204; two instances of base MP contact 223; and two instances of MV contact 226 located above corresponding instances of base MP contact 223. Compared to the extended coupling region 232I, the extended coupling region 232Z lacks MG contacts 208(2) and 208(3) and instances of AR 204 surrounded by MG contacts 208(2) and 208(3). The instances of base MP contact 223 utilize space not occupied by the missing MG contacts 208(2) and 208(3).

[0058] In extended coupling region 232Z, the pitch between instances of AR 204 respectively surrounded by MG contacts 208(1) and 208(4) is 1*P. In some embodiments, the pitch between instances of AR 204 respectively surrounded by MG contacts 208(1) and 208(4) is N*P.

[0059] The extended MP contact 224Z has a Z shape, that is, a shape similar to a capital letter Z. The capital letter Z has a column and a first arm and a second arm. In the preset orientation of the Z shape: the column is parallel to the Y axis; the first arm and the second arm are parallel to the X axis; the first arm and the second arm intersect the corresponding first end and second end of the column; and relative to the third direction (X axis), the first arm extends to the left side of the column, and the second arm extends to the right side of the column.

[0060] The Z-shape of the MP contact 224Z has a first orientation that is rotated approximately 90 degrees counterclockwise relative to the preset orientation of the capital letter Z. The second arm of the Z-shaped extended MP contact 224Z is coupled to the MG contact 208(4). The first arm of the Z-shaped extended MP contact 224Z is coupled to the MG contact 208(1). In some embodiments, the extended MP contact 224Z is illustrated as an octagon. In some embodiments, the extended MP contact 224Z is illustrated as a concave polygon.

[0061] exist Figure 2A With respect to the extended coupling regions 232P, 232L and / or 232Z, in some embodiments, the MV contacts 226 are correspondingly replaced by BPD contacts (not shown).

[0062] exist Figure 2B , the extended coupling region 232H includes: an extended MP contact 224H; and MG contacts 208 ( 1 ), 208 ( 2 ), 208 ( 3 ), and 208 ( 4 ) surrounding corresponding instances of the AR 204 .

[0063] The extended MP contact 224H has an H shape, that is, a shape similar to a capital letter H. The capital letter H has a first column, a second column, and a crossbar. In the preset orientation of the H shape, the first column and the second column are parallel to the Y axis, the crossbar is parallel to the X axis, and the center area of ​​each of the first column and the second column intersects the crossbar.

[0064] The H-shape of MP contact 224H has a first orientation that is the same as the predetermined orientation of the capital letter H. The first column of the H-shape of stretched MP contact 224H is coupled to MG contacts 208(3) and 208(1). The second column of the H-shape of stretched MP contact 224H is coupled to MG contacts 208(4) and 208(2). In some embodiments, stretched MP contact 224H is described as a dodecagon. In some embodiments, stretched MP contact 224H is described as a concave polygon. The pitch relationship between MG contacts 208(1), 208(2), 208(3), and 208(4) in stretched coupling region 232H is the same as in stretched coupling region 232I.

[0065] exist Figure 2B , the extended coupling region 232_4 includes: an extended MP contact 224_4; MG contacts 208(1), 208(3), and 208(4) surrounding corresponding instances of AR 204; instances of base MP contact 223; and instances of MV contact 226 located above instances of base MP contact 223. Compared to the extended coupling region 232I, the extended coupling region 232_4 lacks MG contact 208(2) and instances of AR 204 surrounded by MG contact 208(2). The instances of base MP contact 223 utilize the space not occupied by the missing MG contact 208(2).

[0066] The extended MP contact 224_4 has an open-top shape, i.e., a shape similar to an open-top style number in contrast to the closed-top style number 4. The open-top style number has a column, a crossbar, and an ascender. In the preset orientation of the open-top style number: the column and the ascender are parallel to the Y axis; the crossbar is parallel to the X axis; and the center area of ​​the column intersects the first end of the crossbar; and the ascender extends from the second end of the crossbar to the upper side of the crossbar relative to the Y axis.

[0067] The shape of the stretched MP contact 224_4 has a first orientation, and the first orientation is mirror-symmetric about a top open digital having a predetermined orientation relative to a symmetry axis parallel to the Y axis. The pillar of the shape of the stretched MP contact 224_4 is coupled to the MG contacts 208 (1) and 208 (3). The rising portion of the shape of the stretched MP contact 224_4 is coupled to the MG contact 208 (4). In some embodiments, the stretched MP contact 224_4 is described as a decagon. In some embodiments, the stretched MP contact 224_4 is described as a concave polygon. The pitch relationship between the MG contacts 208 (1), 208 (3) and 208 (4) in the stretched coupling region 232_4 is the same as in the stretched coupling region 232P.

[0068] exist Figure 2B 2, the extended coupling region 232U includes: an extended MP contact 224U; MG contacts 208(1), 208(3), 208(4), and 208(5) surrounding corresponding instances of AR 204; an instance of an extended MP contact 224I, labeled 224U(2) in the extended coupling region 232U; a first instance of a base MP contact 223, labeled 224U(1) ​​in the extended coupling region 232U; a second instance of the base MP contact 223; and an instance of an MV contact 226, located above the instance of the base MP contact 223. Compared to the extended coupling region 232I, the extended coupling region 232U lacks the MG contact 208(2) and the instance of the AR 204 surrounded by the MG contact 208(2). The instance of the base MP contact 223 utilizes the space not occupied by the missing MG contact 208(2).

[0069] The pitch relationship between MG contacts 208(1), 208(3), and 208(4) in stretch coupling region 232U is the same as in stretch coupling region 232P. In stretch coupling region 232U, the pitch between instances of AR 204 respectively surrounded by MG contacts 208(1) and 208(5) is 2*P. In some embodiments, the pitch between instances of AR 204 respectively surrounded by MG contacts 208(1) and 208(5) is K*P, where K is a positive integer and 3≤K.

[0070] The extended MP contact 224U includes portions 224U(1), 224U(2), and 224U(3). Portion 224U(1) ​​is an example of an extended MP contact 224I that has been rotated approximately 90 degrees (90°) clockwise or counterclockwise and scaled to fit into a gap 234 between the MG contact 208(1) and the MG contact 208(3). Portion 224U(2) is an example of an extended MP contact 224I that has been scaled to fit into a gap 236 between the MG contact 208(3) and the MG contact 208(4). Portion 224U(3) is an example of an extended MP contact 224L having an L shape. The L shape of portion 224U(3) has a second orientation that is rotated approximately 180 degrees clockwise relative to a preset orientation of the capital letter L. The orientation of portion 224U(3) is mirror-symmetric relative to the preset orientation of the capital letter L with respect to an axis of symmetry that is parallel to the column of the capital letter L at the preset orientation of the capital letter L.

[0071] The outline including the borrowed portion 238(2) of the MG contact 208(3), the borrowed portion 238(3) of the MG contact 208(4), and the portions 224U(1) ​​to 224U(3) has a U-shape, i.e., a shape similar to the capital letter U. Therefore, the extended MP contact 224U is described as having a U-shape, i.e., a shape similar to the capital letter U. The capital letter U has a first column and a second column and a crossbar. In the preset orientation of the U-shape, the first column and the second column are parallel to the Y-axis, the crossbar is parallel to the X-axis, and the same end of each of the first column and the second column intersects the crossbar.

[0072] The portion 224U(1) ​​of the extended MP contact 224U is coupled to the MG contacts 208(1) and 208(3). The portion 224U(2) of the extended MP contact 224U is coupled to the MG contacts 208(3) and 208(4). The portion 224U(3) of the extended MP contact 224U is coupled to the MG contacts 208(4) and 208(5). Figure 2B2, the extended coupling region 232F includes: an extended MP contact 224F; MG contacts 208(1), 208(3), 208(4), 208(5), and 208(6) surrounding corresponding instances of AR 204; an instance of an extended MP contact 224I, labeled 224F(2) in the extended coupling region 232F; a first instance of a base MP contact 223, labeled 224F(1) in the extended coupling region 232F; a second instance of the base MP contact 223; and an instance of an MV contact 226, located above the instance of the base MP contact 223. Compared to the extended coupling region 232I, the extended coupling region 232F lacks the MG contact 208(2) and the instance of the AR 204 surrounded by the MG contact 208(2). The instance of the base MP contact 223 utilizes the space not occupied by the missing MG contact 208(2).

[0073] The pitch relationship between MG contacts 208(1), 208(3), 208(4), and 208(5) in stretch coupling region 232F is the same as in stretch coupling region 232U. In stretch coupling region 232F, the pitch between instances of AR 204 respectively surrounded by MG contacts 208(4) and 208(6) is 2*P. In some embodiments, the pitch between instances of AR 204 respectively surrounded by MG contacts 208(4) and 208(6) is K*P, where K is a positive integer and 3≤K.

[0074] The extended MP contact 224F includes portions 224F(1), 224F(2), and 224F(3). Portion 224F(1) is similar to portion 224U(1) ​​discussed above. Portion 224F(2) is similar to portion 224U(2) discussed above. Portion 224F(3) is an example of an extended MP contact 224T having a T shape. The T shape of portion 224F(3) is rotated approximately 90 degrees clockwise relative to extended MP contact 224T, i.e., has the same orientation as the preset orientation of the capital letter T.

[0075] The outline including the borrowed portion 238(2) of the MG contact 208(3), the borrowed portion 238(3) of the MG contact 208(4), the borrowed portion 238(4) of the MG contact 208(6), and the portions 224F(1) to 224F(3) has an F shape, i.e., a shape similar to the capital letter F. Therefore, the extended MP contact 224F is described as having an F shape, i.e., a shape similar to the capital letter F. The capital letter F has a first column and a second column, a crossbar, and an arm. In the preset orientation of the F shape, the first column and the second column are parallel to the Y axis, the crossbar and the arm are collinear with each other and parallel to the X axis, the same first end of each of the first column and the second column intersects with the crossbar, and the end of the arm intersects with the first end of the second column.

[0076] Portion 224F(1) of extended MP contact 224F is coupled to MG contacts 208(1) and 208(3). Portion 224F(2) of extended MP contact 224F is coupled to MG contacts 208(3) and 208(4). Portion 224F(3) of extended MP contact 224F is coupled to MG contacts 208(4), 208(5), and 208(6).

[0077] exist Figure 2B With respect to the extended coupling regions 232_4, 232U and / or 232F, in some embodiments, the MV contacts 226 are correspondingly replaced by BPD contacts (not shown).

[0078] exist FIG. 2A to FIG. 2B In some embodiments, various combinations of extended coupling regions 232I, 232T, 232P, 232L, 232Z, 232H, 232_4, 232U and / or 232F are implemented to facilitate coupling various instances of MG contacts (shown or not shown), MV contacts (shown or not shown) and / or BPD contacts (shown).

[0079] FIG. 3A to FIG. 3H is a layout diagram of a corresponding semiconductor device including one or more stretched MP contacts according to some embodiments.

[0080] Figure 3A340A. Inverter 340A is an INVD2 type inverter, where "INVD2" is an acronym for "an inverter (INV) having current-driving (alternatively, current-sourcing) strength of 2*D", where "D" is the unit of drive strength for the corresponding process node for manufacturing devices based on inverter 340A. Inverter 340A includes an example of extended MP contact 224H. Inverter 340A exhibits a M0VM1H architecture.

[0081] Figure 3B 2 is a layout diagram of inverter 340B. Inverter 340B is an INVD2 type inverter. Inverter 340B includes an example of extended MP contact 224H. Inverter 340B exhibits a M0HM1V architecture.

[0082] FIG. 3C to FIG. 3H is a layout diagram of a corresponding semiconductor device including one or more stretched MP contacts according to some embodiments.

[0083] More specifically, FIG. 3C to FIG. 3H Layout diagram of a corresponding scan-D flip-flop with a single output (SDFQD1) 342C, 342D, 342E, 342F, 342G, and 342H. SDFQD1342C includes an instance of a stretched MP contact 224_4 and an instance of a stretched MP contact 224Z. SDFQD1342D includes an instance of a stretched MP contact 224U. SDFQD1342E includes an instance of a stretched MP contact 224H. SDFQD1342F includes an instance of a stretched MP contact 224H and an instance of a stretched MP contact 224L. SDFQD1342G includes an instance of a stretched MP contact 224H, an instance of a stretched MP contact 224L, an instance of a stretched MP contact 224_4, and an instance of a stretched MP contact 224Z. SDFQD1342H includes an instance of an extended MP contact 224H, an instance of an extended MP contact 224U, and an instance of an extended MP contact 224L.

[0084] Figure 4 is a layout diagram of a corresponding region 450 of a semiconductor device according to some embodiments.

[0085] exist Figure 4, assuming that the first, second, and third orthogonal directions are, for example, parallel to the X-axis, the Y-axis, and the Z-axis, respectively. Region 450 is a condensed region of a semiconductor device for reducing space that would otherwise be wasted (i.e., unused space). As discussed below, region 450 is compressed relative to the X-axis (e.g., with respect to an M0 segment (which is adjacent to an M0 on the X-axis) that includes approximately 1 times the size of a contacted polypitch (CPP)). As discussed below, region 450 is compressed relative to the Y-axis (e.g., with respect to adjacent α track spacings of V0).

[0086] Region 450 includes: MD contacts 410(11), 410(12), 410(13), and 410(14); MG contacts 408(11), 408(12), 408(13), 408(14), and 408(15), surrounding corresponding instances of AR comprised of instances of nanowire 406; base MP contacts 423(1), 423(2), and 423(3); an instance of MV contact 426; an instance of VG contact 430; M0 segments 416(1), 416(2), 416(3), 416(4), 416(5), and 416(6); an instance of V0 contact 420; and M1 segments 422(1) and 422(2). In some cases, each instance of AR is comprised of one or more instances of a nanosheet.

[0087] Zones 450 are arranged according to alpha tracks α1, α2, α3, α4, α5, α6, α7, α8, and α9 extending in a direction parallel to the X axis and according to beta tracks β1, β2, β3, β4, β5, β6, β7, β8, and β9 extending in a direction parallel to the Y axis. The beta tracks have a pitch of 1*S, as discussed below.

[0088] M0 segments 416(3), 416(4), and 416(5) have been obtained by cutting longer precursor M0 segments separated by a distance of 1*S relative to the X-axis (i.e., applying a 1-S separation cut), where S represents a uniform distance between adjacent instances of AR (composed of instances of nanowires 406 of AR 204) of a corresponding semiconductor process technology node. In some embodiments, the uniform distance S represents a contact polysilicon pitch (CPP) of the corresponding semiconductor process technology node. Here, the word "poly" in the term "CPP" does not necessarily imply a corresponding CPP based on Figure 4The gate structures in semiconductor devices of the present invention are not intended to be formed of polycrystalline silicon, but rather represent historical convenience, that is, this is because the gate structures in ICs manufactured according to previous semiconductor process technology nodes are often formed of polycrystalline silicon. Relative to the X-axis, each of M0 segments 416(3), 416(4) and 416(5) has a length T≈(1*S) but T<(1*S). Therefore, relative to the X-axis, M0 segments 416(3), 416(4) and 416(5) fit together between β track β2 and β track β8. Therefore, region 450 is compressed relative to the X-axis.

[0089] With respect to the Y axis, M1 segment 422(1) has a minimum length sufficient to accommodate the following instances: an instance of V0 contact 420 located at the intersection of alpha track α4 and beta track β3, that is, at the intersection (α4, β3); and an instance of V0 contact 420 located at the intersection of alpha track α5 and beta track β3, that is, at the intersection (α5, β3). With respect to the Y axis, alpha track α4 is adjacent to alpha track α5. The instances of V0 contact 420 located at the intersections (α4, β3) and (α5, β3) are adjacent to the alpha tracks. Therefore, region 450 is compressed with respect to the Y axis (e.g., with respect to the adjacent alpha track spacing of V0).

[0090] FIG. 5A to FIG. 5D is a layout diagram of a corresponding semiconductor device including one or more instances of a compression region according to some embodiments.

[0091] exist FIG. 5A to FIG. 5D , it is assumed that the first orthogonal direction, the second orthogonal direction, and the third orthogonal direction are, for example, parallel to the X-axis, the Y-axis, and the Z-axis, respectively. FIG. 5A to FIG. 5D The compression zone shown is similar to Figure 4 Compression zone 450 is shown.

[0092] Figure 5A 4 is a layout diagram of a NAND gate 452. NAND gate 452 is a NAND gate of type ND2D1, where "ND2D1" is an acronym for "a NAND gate having two inputs and a current-driving (alternatively, current-sourcing) strength of 1*D". With respect to the X-axis, each of the M0 segments has a length T≈(1*S) but T<(1*S). Two of the M0 segments are co-linear and aligned with adjacent α tracks. Therefore, NAND gate 452 is compressed with respect to the X-axis.

[0093] Figure 5B4 is a layout diagram of inverter 454. Inverter 454 is an INVD1 type inverter, where "INVD1" is an acronym for "inverter having a current-driving (alternatively, current-sourcing) strength of 1*D". With respect to the X-axis, each of the M0 segments has a length T≈(1*S) but T<(1*S). Therefore, inverter 454 is compressed with respect to the X-axis.

[0094] Figure 5C 4 is a layout diagram of an AND-OR-Invert (AOI) gate 456. AOI gate 456 is an AOI22D1 type AOI gate, where "AOI22D1" is an acronym for "an AOI gate having two inputs and a current-driving (alternatively, current-sourcing) strength of 1*D". With respect to the X-axis, each of the M0 segments has a length T≈(1*S) but T<(1*S). Four of the M0 segments are collinear. Two pairs of M0 segments are aligned with adjacent α tracks, respectively. Therefore, AOI gate 456 is compressed with respect to the X-axis.

[0095] Figure 5D is a layout diagram of SDFQD1458. With respect to the X-axis, the lengths of the 21 M0 segments are T≈(1*S) but T<(1*S), and 19 of the 21 M0 segments are collinear. Thirteen pairs of M0 segments are aligned with adjacent α orbitals, respectively. Therefore, SDFQD1458 is compressed with respect to the X-axis.

[0096] Figure 6 is a flow chart 600 of a method of manufacturing a memory device according to some embodiments.

[0097] According to some embodiments, the method of flowchart (flow diagram) 600 may be implemented, for example, using an electronic design automation (EDA) system 800 ( Figure 8 , discussed below) and IC manufacturing system 900 ( Fig. 9 Examples of semiconductor devices that can be manufactured according to the method shown in flowchart 600 include Figures 1A to 1DThe semiconductor device shown, the semiconductor device based on the layout diagram disclosed in this document, or the like.

[0098] exist Figure 6 In the method shown in flowchart 600, blocks 602 to 604 are included. At block 602, a layout diagram is generated that includes, among other things, one or more of the layout diagrams disclosed herein. According to some embodiments, block 602 may be generated, for example, using EDA system 800 ( Figure 8 , discussed below). Flow proceeds from block 602 to block 604.

[0099] At block 604, based on the layout diagram, at least one of the following operations is performed: (A) performing one or more lithography exposures or (B) fabricating one or more semiconductor masks or (C) fabricating one or more components in a semiconductor device layer. Fig. 9 The following discussion of the IC manufacturing system 900 in FIG.

[0100] Figure 7 is a flow chart 700 of a method of fabricating a semiconductor device, and more particularly, a memory device, according to some embodiments.

[0101] Flowchart 700 is Figure 6 6. The flowchart 700 includes blocks 702 to 710. The examples provided in the context of the discussion of blocks 702 to 710 assume that the first, second, and third orthogonal directions are parallel to the X-axis, Y-axis, and Z-axis, respectively, for example. According to some embodiments, the method shown in flowchart 700 may be performed, for example, using IC manufacturing system 900 ( Fig. 9 , discussed below). Examples of semiconductor devices that can be manufactured according to the method shown in flowchart 700 include Figures 1A to 1D The semiconductor device shown, the semiconductor device based on the layout diagram disclosed in this document, or the like.

[0102] exist Figure 7 In the embodiment of the present invention, at block 702, buried MD (BMD) contacts are formed, including a first buried MD (BMD) contact and a second buried MD (BMD) contact. Examples of BMD contacts include BMD contacts 112 corresponding to MG contacts 108 (3) and 108 (1), etc. Flow proceeds from block 702 to block 704.

[0103] At block 704 , a lower portion of an active region (AR) is formed on selected portions of corresponding BMD contacts, the lower portion including a lower portion of a first AR and a lower portion of a second AR.

[0104] With respect to the lower portion of the first AR and the lower portion of the second AR, and relative to the Z-axis, the upper portion of the lower portion of the first AR and the upper portion of the lower portion of the second AR represent a channel region, and the end of the lower portion of the lower portion of the first AR and the end of the lower portion of the lower portion of the second AR represent instances of first source / drain (S / D) regions coupled to the first BMD contact and the second BMD contact, respectively. The instances of the lower portion of the first AR and the instances of the lower portion of the second AR include lower portions of instances of AR 104 that are respectively surrounded by MG contacts 108(3) and 108(1), the MG contacts 108(3) and 108(1) being separated relative to the Y-axis, each such AR having a channel axis extending parallel to the Z-axis, etc. Flow proceeds from block 704 to block 706.

[0105] At block 706, metal-to-gate (MG) contacts are formed adjacent to the channel region of the first AR and the channel region of the second AR, respectively. The MG contacts include a first MG contact and a second MG contact. Examples of the first MG contact and examples of the second MG contact include MG contacts 108(3) and 108(1), etc. From block 706, the flow proceeds to block 708.

[0106] At block 708, a metal-to-polysilicon (MP) contact is formed at the same level as the first MG contact and the second MG contact relative to the Z axis, the MP contact extends between the first MG contact and the second MG contact relative to the Y axis, and the MP contact couples the first MG contact and the second MG contact together. An example of the MP contact is the stretched MP contact 124, etc. Flow proceeds from block 708 to block 710.

[0107] At block 710, an upper portion of the AR is formed correspondingly on the lower portion of the AR, the upper portion including the upper portion of the first AR and the upper portion of the second AR. The upper end of the upper portion of the AR represents an instance of the second S / D region. The example of the upper portion of the AR includes the upper portion of the instance of the AR 104 surrounded by the MG contacts 108(3) and 108(1), respectively.

[0108] Figure 8 is a block diagram of an electronic design automation (EDA) system 800 according to some embodiments.

[0109] In some embodiments, EDA system 800 includes an automatic placement and routing (APR) system. In some embodiments, EDA system 800 is a general purpose computing device including a hardware processor 802 and a non-transitory computer-readable storage medium 804. Storage medium 804 is encoded with (i.e., stores) computer program code 806 (i.e., a set of executable instructions), among other things. Execution of instructions 806 by hardware processor 802 (at least in part) represents implementation of, for example, one or more embodiments of the present invention. Figure 6 The method shown (block 602), generates e.g. FIG. 2A to FIG. 2B Methods for layout diagrams, generation and e.g. Figures 1A to 1D The storage medium 804 stores, among other things, a layout diagram 811, such as the layout diagram disclosed herein or a similar layout diagram.

[0110] The processor 802 is electrically coupled to a computer-readable storage medium 804 via a bus 808. The processor 802 is further electrically coupled to an input / output (I / O) interface 810 via the bus 808. A network interface 812 is further electrically connected to the processor 802 via the bus 808. The network interface 812 is connected to a network 814, so that the processor 802 and the computer-readable storage medium 804 can be connected to external components via the network 814. The processor 802 is configured to execute a computer program code 806 encoded in the computer-readable storage medium 804 so that the system 800 can be used to implement part or all of the proposed process and / or method. In one or more embodiments, the processor 802 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0111] In one or more embodiments, the computer-readable storage medium 804 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable storage medium 804 includes semiconductor memory or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In one or more embodiments using optical disks, the computer-readable storage medium 804 includes compact disk-read only memory (CD-ROM), compact disk-read / write (CD-R / W), and / or digital video disc (DVD).

[0112] In one or more embodiments, the storage medium 804 stores computer program code 806, which is configured to enable the system 800 (where such execution (at least in part) represents an EDA tool) to be used to implement part or all of the proposed process and / or method. In one or more embodiments, the storage medium 804 further stores information that facilitates the implementation of part or all of the proposed process and / or method. In one or more embodiments, the storage medium 804 stores a standard cell library 807 including such standard cells disclosed herein. In some embodiments, the storage medium 804 stores one or more layout drawings 811.

[0113] The EDA system 800 includes an I / O interface 810. The I / O interface 810 is coupled to an external circuit system. In one or more embodiments, the I / O interface 810 includes a keyboard, a keypad, a mouse, a trackball, a trackpad, a touch screen, and / or cursor arrow keys for transmitting information and commands to the processor 802.

[0114] The EDA system 800 further includes a network interface 812 coupled to the processor 802. The network interface 812 enables the system 800 to communicate with a network 814 connected to one or more other computer systems. The network interface 812 includes a wireless network interface, such as BLUETOOTH, wireless fidelity (WIFI), Worldwide Interoperability for Microwave Access (WIMAX), General Packet Radio Service (GPRS), or wideband code division multiple access (WCDMA); or a wired network interface, such as Ethernet (ETHERNET), universal serial bus (USB), or Institute of Electrical and Electronic Engineers-1364 (IEEE-1364). In one or more embodiments, part or all of the proposed process and / or method is implemented in two or more systems 800.

[0115] The system 800 is configured to receive information via an I / O interface 810. The information received via the I / O interface 810 includes one or more of instructions, data, design rules, standard cell libraries, and / or other parameters for processing by the processor 802. The information is transmitted to the processor 802 via a bus 808. The EDA system 800 is configured to receive information related to a user interface (UI) via the I / O interface 810. The information is stored in a computer readable medium 804 as a UI 842.

[0116] In some embodiments, part or all of the proposed process and / or method is implemented in the form of a stand-alone software application executed by a processor. In some embodiments, part or all of the proposed process and / or method is implemented in the form of a software application that is part of an additional software application. In some embodiments, part or all of the proposed process and / or method is implemented in the form of a plug-in to a software application. In some embodiments, at least one of the proposed process and / or method is implemented in the form of a software application that is part of an EDA tool. In some embodiments, part or all of the proposed process and / or method is implemented in the form of a software application used by an EDA system 800. In some embodiments, a tool (e.g., a software application available from Cadence Design Systems, Inc.) is used to implement the proposed process and / or method. or another suitable layout generation tool) to generate a layout including standard cells.

[0117] In some embodiments, the process is implemented in the functional form of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage units or memory units, such as one or more of optical disks (e.g., DVDs), magnetic disks (e.g., hard disks), semiconductor memories (e.g., ROM, RAM), memory cards, and the like.

[0118] Fig. 9 is a block diagram of an integrated circuit (IC) manufacturing system 900 and an IC manufacturing flow associated with the IC manufacturing system 900 according to some embodiments.

[0119] Based on Figure 6 The layout diagram generated by block 602 is implemented by the IC manufacturing system 900 Figure 6 As shown in block 604 , at block 604 , fabrication system 900 is used to fabricate at least one of: (A) one or more semiconductor masks or (B) at least one component in a layer of an early semiconductor integrated circuit.

[0120] exist Fig. 9In the present invention, the IC manufacturing system 900 includes entities that interact with each other in the design, development and manufacturing cycle and / or services related to manufacturing IC devices 960, such as a design division 920, a mask division 930, and an IC manufacturing plant / fab ("fab") 950. The entities in the system 900 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired communication channels and / or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to one or more of the other entities and / or receives services from one or more of the other entities. In some embodiments, a single larger company owns two or more of the design division 920, the mask division 930, and the IC fabrication plant 950. In some embodiments, two or more of the design division 920, the mask division 930, and the IC fabrication plant 950 coexist in a common facility and use common resources.

[0121] The design division (or design team) 920 generates an IC design layout 922. The IC design layout 922 includes various geometric patterns designed for the IC device 960. The geometric patterns correspond to the patterns of the metal layers, oxide layers, or semiconductor layers that constitute the various components of the IC device 960 to be manufactured. The various layers are combined to form various IC features. For example, a portion of the IC design layout 922 includes various IC features to be formed in a semiconductor substrate (such as a silicon wafer) (such as active regions, gate electrodes, sources and drains, metal lines or vias for interconnects between layers, and openings for bonding pads) and various material layers disposed on the semiconductor substrate. Depending on the context, the source / drain region may refer to the source or drain individually or collectively. The design division 920 implements an appropriate design program to form the IC design layout 922. The design program includes one or more of a logical design, a physical design, or a layout and routing. The IC design layout 922 is presented in the form of one or more data files having information of the geometric pattern. For example, IC design layout 922 is expressed in a GDSII file format or a DFII file format.

[0122] The mask division 930 includes data preparation 932 and mask production 934. The mask division 930 uses the IC design layout 922 to manufacture one or more masks 935 according to the IC design layout 922 for use in manufacturing various layers of the IC device 960. The mask division 930 performs mask data preparation 932, and translates the IC design layout 922 into a representative data file ("representative data file, RDF") when performing the mask data preparation 932. The mask data preparation 932 supplies the RDF to the mask production 934. The mask production 934 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (reticle) or a semiconductor wafer. The mask data preparation 932 manipulates the design layout to comply with the specific characteristics of the mask writer and / or the requirements of the IC manufacturing plant 950. In Fig. 9 , mask data preparation 932, mask production 934, and mask 935 are shown as separate elements. In some embodiments, mask data preparation 932 and mask production 934 may be collectively referred to as mask data preparation.

[0123] In some embodiments, mask data preparation 932 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors (e.g., image errors that may be caused by diffraction, interference, other process effects, and the like). OPC adjusts IC design layout 922. In some embodiments, mask data preparation 932 further includes resolution enhancement techniques (RET), such as off-axis illumination, secondary resolution adjustment features, phase shift masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is further used to treat OPC as an inverse imaging problem.

[0124] In some embodiments, mask data preparation 932 includes a mask rule checker (MRC) that checks the IC design layout that has been through the process in OPC using a set of mask creation rules that include certain geometric constraints and / or connectivity constraints to ensure that sufficient margins are in place to account for variability in semiconductor manufacturing processes and the like. In some embodiments, the MRC modifies the IC design layout to compensate for the constraints during mask creation 934, which may cancel a portion of the modifications performed by OPC to satisfy the mask creation rules.

[0125] In some embodiments, mask data preparation 932 includes lithography process checking (LPC), which simulates the process to be performed by IC fabrication facility 950 to fabricate IC device 960. LPC simulates such process based on IC design layout 922 to fabricate simulated finished device, such as IC device 960. Process parameters in LPC simulation may include parameters associated with various processes of IC manufacturing cycle, parameters associated with tools used to fabricate IC, and / or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and the like, or combinations thereof. In some embodiments, after the simulated finished device has been fabricated by LPC, if the shape of the simulated device is not close enough to meet the design rules, OPC and / or MRC are repeated to further improve IC design layout 922.

[0126] For the sake of clarity, the above description of mask data preparation 932 has been simplified. In some embodiments, mask data preparation 932 includes additional features, such as modifying logic operations (LOP) of IC design layout according to manufacturing rules. In addition, the processes applied to IC design layout 922 during data preparation 932 can be performed in a variety of different orders.

[0127] After mask data preparation 932 and during mask fabrication 934, a mask 935 or a group of masks 935 are fabricated based on the modified IC design layout. In some embodiments, an electron-beam (e-beam) or a mechanism consisting of multiple electron beams is used to form a pattern on a mask (photomask or stencil) based on the modified IC design layout. The mask is formed with various techniques. In some embodiments, the mask is formed using a binary technique. In some embodiments, the mask pattern includes an opaque area and a transparent area. A radiation beam (e.g., an ultraviolet (UV) beam) used to expose an image sensitive material layer (e.g., photoresist) coated on a wafer is blocked by the opaque area and transmitted through the transparent area. In one example, the binary mask includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chrome) coated in the opaque area of ​​the mask. In another example, the mask is formed using a phase shift technique. In a phase shift mask (PSM), various features in a pattern formed on the mask are configured to have an appropriate phase difference to enhance resolution and image quality. In various examples, the phase shift mask is an attenuated PSM or an alternating PSM. The mask produced by mask making 934 is used in various processes. For example, such a mask is used in an ion implantation process to form various doped regions in a semiconductor wafer, in an etching process to form various etched regions in a semiconductor wafer, and / or in other suitable processes.

[0128] IC fabrication plant 950 is an IC fabrication enterprise that includes one or more fabrication facilities for fabricating various IC products. In some embodiments, IC fabrication plant 950 is a semiconductor foundry. For example, there may be a fabrication facility for front-end fabrication (front-end-of-line, FEOL) fabrication of multiple IC products, while a second fabrication facility may be used for back-end fabrication (back-end-of-line, BEOL) fabrication of interconnects and packaging for IC products, and a third fabrication facility may provide other services for the foundry enterprise.

[0129] IC fabrication facility 950 uses mask (or masks) 935 fabricated by mask division 930 to fabricate IC device 960 using fabrication tool 952. Therefore, IC fabrication facility 950 at least indirectly uses IC design layout 922 to fabricate IC device 960. In some embodiments, IC fabrication facility 950 uses mask (or masks) 935 to fabricate semiconductor wafer 953 to form IC device 960. Semiconductor wafer 953 includes a silicon substrate or other appropriate substrate with material layers formed thereon. The semiconductor wafer further includes one or more of various doped regions, dielectric features, multi-level interconnects, and the like (formed at subsequent fabrication steps).

[0130] In some embodiments, a semiconductor device (having a vertical field effect transistor (VFET) architecture) includes: an active region (AR), including a first active region (AR) and a second active region (AR) separated relative to a first direction, the first AR and the second AR each having a channel axis extending in a second direction perpendicular to the first direction, and each having a channel region located between a selected portion of an overlying first source / drain (S / D) region and a selected portion of an underlying second S / D region relative to the second direction; a metal-to-gate (MG) contact, including a first MG contact and a second MG contact respectively adjacent to the channel region of the first AR and the channel region of the second AR and separated relative to the first direction; a metal-to-source / drain (MD) contact and a buried MD (BMD) contact, which is correspondingly coupled to the corresponding first S / D region and the second S / D region of the first AR and the corresponding first S / D region and the second S / D region of the second AR with respect to the second direction; and a metal-to-polysilicon (MP) contact, which is located at the same level as the MG contact with respect to the second direction, and extends between the first MG contact and the second MG contact with respect to the first direction and couples the first MG contact and the second MG contact together; with respect to a third direction perpendicular to each of the first direction and the second direction, the first AR and the second AR are substantially aligned; and with respect to the third direction, at least a portion of the MP contact substantially extends beyond each of the first AR and the second AR.

[0131] In some embodiments, the AR further includes a third active region (AR), the third AR having a channel axis extending in the second direction and having a channel region located between an overlying first source / drain (S / D) region and an underlying second S / D region relative to the second direction; and the third AR is separated from the first AR relative to the third direction; and at least a portion of the MP contact at least partially overlaps with the third AR relative to the third direction.

[0132] In some embodiments, the shape of the MP contact is an irregular polygon relative to a reference plane defined by the first direction and a third direction perpendicular to each of the first direction and the second direction.

[0133] In some embodiments, the shape of the MP contact is a concave polygon relative to a reference plane defined by the first direction and a third direction perpendicular to each of the first direction and the second direction.

[0134] In some embodiments, the MP contact is shaped like a convex polygon.

[0135] In some embodiments, with respect to a reference plane defined by the first direction and the third direction, the shape of the MP contact is a polygon with N sides, where N is an even number and 4≦N.

[0136] In some embodiments, N=4, so that the shape of the MP contact is rectangular.

[0137] In some embodiments, N=6, so that the shape of the MP contact is hexagonal.

[0138] In some embodiments, the shape of the MP contact is an L-shape.

[0139] In some embodiments, the L-shape has a column and an arm, wherein a preset orientation of the L-shape causes the column to be parallel to a first direction, the arm to be parallel to a third direction perpendicular to each of the first direction and the second direction, and the arm to extend to the right side of the column relative to the third direction; the arm intersects with the first end of the column relative to the first direction with respect to a first end of the column of the L-shape relative to the first direction; and the L-shape of the MP contact has a first orientation or a second orientation; the first orientation of the L-shape of the MP contact is rotated approximately 90 degrees clockwise relative to the preset orientation; and the second orientation of the L-shape of the MP contact is mirror-symmetric about the L-shape having the preset orientation with respect to an axis of symmetry of the L-shape of the MP contact parallel to the third direction in the preset orientation.

[0140] In some embodiments, the first AR is separated from the second AR relative to the third direction; the first MG contact is separated from the second MG contact relative to the third direction; the L-shaped column of the MP contact is coupled to the second MG contact; and the L-shaped arm of the MP contact is coupled to the third MG contact.

[0141] In some embodiments, the shape of the MP contact is a P-shape.

[0142] In some embodiments, the P-shape has a column and an arm, wherein a preset orientation of the P-shape causes the column to be parallel to a first direction, the arm to be parallel to a third direction perpendicular to each of the first direction and the second direction, and the arm to extend to the right side of the column relative to the third direction; with respect to a first end of the L-shaped column relative to the first direction, the arm intersects with the first end of the column relative to the first direction; and the P-shape of the MP contact has a first orientation; the first orientation of the P-shape of the MP contact is: rotated approximately 90 degrees clockwise relative to the preset orientation of the P-shape, and with respect to an axis of symmetry of the P-shape parallel to the first direction in the preset orientation of the P-shape, the first orientation of the P-shape of the MP contact is mirror-symmetric with respect to the P-shape having the preset orientation.

[0143] In some embodiments, the AR further includes a third AR, the third AR having a channel axis extending in the second direction and having a channel region located between an overlying first source / drain (S / D) region and an underlying second S / D region relative to the second direction; the third AR is separated from the first AR relative to the third direction; the MG contact further includes a third MG contact adjacent to the channel region of the third AR; the first MG contact is substantially aligned with the second MG contact relative to the first direction; the third MG contact is separated from the first MG contact relative to the third direction; the P-shaped column of the MP contact is coupled to the first MG contact and the third MG contact; and the P-shaped arm of the MP contact is coupled to the first MP contact and the second MP contact.

[0144] In some embodiments, N=8, so that the shape of the MP contact is an octagon.

[0145] In some embodiments, the shape of the MP contact is a T-shape or a Z-shape.

[0146] In some embodiments, the T-shape has a column and an arm, wherein a preset orientation of the T-shape causes the column to be parallel to a first direction, and the arm to be parallel to a third direction perpendicular to each of the first direction and the second direction, so that a center region of the arm intersects the column; the arm intersects the first end of the column relative to the first direction; the T-shape of the MP contact has a first orientation; and the first orientation of the T-shape of the MP contact is rotated approximately 90 degrees counterclockwise relative to the preset orientation of the T-shape.

[0147] In some embodiments, the arm of the T-shape is coupled to the first MG contact and the second MG contact; and the post of the T-shape substantially extends beyond each of the first MG contact and the second MG contact relative to the third direction. In some embodiments, the Z-shape has a post and a first arm and a second arm, wherein a preset orientation of the Z-shape makes the post parallel to the first direction, makes the first arm and the second arm parallel to a third direction perpendicular to each of the first direction and the second direction, makes the first arm and the second arm intersect the corresponding first end and second end of the post, and makes the first arm extend to the left side of the post and the second arm extend to the right side of the post relative to the third direction; the Z-shape of the MP contact has a first orientation; and the first orientation of the Z-shape of the MP contact is rotated counterclockwise by about 90 degrees relative to the preset orientation.

[0148] In some embodiments, with respect to the third direction: the second MG contact is spaced apart from the first MG contact with respect to the third direction; the second arm is coupled to the first MG contact; and the first arm is coupled to the second MG contact.

[0149] In some embodiments, N=12, so that the shape of the MP contact is a dodecagon.

[0150] In some embodiments, the shape of the MP contact is an H shape or a 4 shape.

[0151] In some embodiments, the H-shape has a first column and a second column and a cross bar, wherein a preset orientation of the H-shape makes the first column and the second column parallel to a first direction, makes the cross bar parallel to a third direction perpendicular to each of the first direction and the second direction, and makes a central area of ​​each of the first column and the second column intersect with the cross bar; the H-shape of the MP contact has a first orientation; and the first orientation of the H-shape of the MP contact is a preset orientation of the H-shape.

[0152] In some embodiments, the AR further includes a third AR and a fourth AR, the third AR and the fourth AR are separated relative to the third direction, each has a channel axis extending in the second direction, and each has a channel region located between the overlying first S / D region and the underlying S / D region relative to the second direction; the MG contact further includes a third MG contact and a fourth MG contact adjacent to the channel region of the third AR and the channel region of the fourth AR; the third MG contact and the fourth MG contact are separated from the first MG contact and the second MG contact respectively; the H-shaped first column of the MP contact is coupled to the first MG contact and the second MG contact; the H-shaped second column of the MP contact is coupled to the third MG contact and the fourth MG contact.

[0153] In some embodiments, the 4-shape has a column, a crossbar, and a rising portion, wherein a preset orientation of the 4-shape makes the column and the rising portion parallel to a first direction, makes the crossbar parallel to a third direction perpendicular to each of the first direction and the second direction, makes the central area of ​​the column intersect with the first end of the crossbar, and makes the rising portion extend from the second end of the crossbar to the upper side of the crossbar relative to the first direction; and the 4-shape of the MP contact has a first orientation; and relative to an axis of symmetry parallel to the first direction, the first orientation of the 4-shape of the MP contact is mirror-symmetric about the 4-shape having the preset orientation.

[0154] In some embodiments, the AR further includes a third AR, the third AR having a channel axis extending in the second direction and having a channel region located between an overlying first source / drain (S / D) region and an underlying second S / D region relative to the second direction; and the MG contact further includes a third MG contact adjacent to the channel region of the third AR; the first MG contact is substantially aligned with the second MG contact relative to the third direction; the third MG contact is separated from the first MG contact relative to the third direction; the first MG contact is substantially aligned with the third MG contact relative to the first direction; the 4-shaped column of the MP contact is coupled to the first MG contact and the second MG contact; and the 4-shaped rising portion of the MP contact is coupled to the third MG contact.

[0155] In some embodiments, each of the first AR and the second AR is composed of a corresponding nanowire.

[0156] In some embodiments, a method (of forming a semiconductor device having a vertical field effect transistor (VFET) architecture) includes: forming buried metal source / drain (MD) contacts, the buried MD contacts including a first buried MD (BMD) contact and a second BMD contact; forming a lower portion of an active region (AR) on selected portions of corresponding BMD contacts, the lower portion including a lower portion of a first AR and a lower portion of a second AR, the first AR and the second AR being separated relative to a first direction and each having a channel axis extending in a second direction perpendicular to the first direction; and with respect to the lower portion of the first AR and the lower portion of the second AR, and relative to the second direction. In the embodiment of the present invention, the upper portion of the lower portion of the first AR and the upper portion of the lower portion of the second AR represent a channel region, and the end of the lower portion of the lower portion of the first AR and the end of the lower portion of the second AR represent an example of a first source / drain (S / D) region coupled to the first BMD contact and the second BMD contact, respectively; a metal-to-gate (MG) contact including a first metal-to-gate (MG) contact and a second metal-to-gate (MG) contact is formed, the first MG contact and the second MG contact are respectively adjacent to the channel region of the first AR and the channel region of the second AR and are separated with respect to the first direction; and the first MG contact and the second MG contact are at the same position as the first MG contact and the second MG contact with respect to the second direction. a first metal-to-source / drain (MD) contact and a second metal-to-source / drain (MD) contact; and The buried metal-to-source / drain (MD) contacts are provided in the form of a first MD contact and a second MD contact, the first MD contact and the second MD contact are respectively located on and coupled to the instances of the corresponding second S / D regions of the first AR and the second AR; forming the buried metal-to-source / drain (MD) contacts includes: substantially aligning a selected portion of the first BMD contact with a selected portion of the second BMD contact relative to a third direction perpendicular to each of the first direction and the second direction; forming the lower portion includes: substantially aligning the first AR and the second AR with a selected portion of the first BMD contact and a selected portion of the second BMD contact respectively relative to the third direction;and forming a metal-to-polysilicon (MP) contact includes: with respect to at least a portion of the MP contact relative to the first direction, extending the at least a portion of the MP contact substantially beyond each of the first AR and the second AR relative to a third direction.;

[0157] In some embodiments, the BMD contact further includes a third BMD contact; the lower portion of the AR further includes a lower portion of the third AR, the third AR has a channel axis extending in the second direction, the upper portion of the lower portion of the third AR represents a channel region, and the lower end of the lower portion of the third AR represents an example of the first S / D region; forming the lower portion includes: positioning the lower portion of the third AR above a selected portion of the third BMD contact; and separating the third BMD contact from the first BMD contact relative to the third direction; the MG contact further includes a channel region of the third AR. an adjacent third MG contact; forming a metal-to-polysilicon (MP) contact comprising: extending at least a portion of the MP contact to at least partially overlap with the third AR relative to a third direction; the upper portion of the AR further comprises an upper portion of the third AR, the upper portion of the third AR is correspondingly located on the lower portion of the third AR, the upper end of the upper portion of the third AR represents an instance of the second S / D region; and the MD contact further comprises a third MD contact, the third MD contact is located on an instance of the second S / D region of the third AR and coupled to an instance of the second S / D region of the third AR.

[0158] In some embodiments, forming a metal-to-polysilicon (MP) contact includes configuring a shape of the MP contact into an irregular polygon relative to a reference plane defined by a first direction and a third direction perpendicular to each of the first direction and the second direction.

[0159] In some embodiments, forming a metal-to-polysilicon (MP) contact includes shaping the MP contact into a concave polygon relative to a reference plane defined by a first direction and a third direction perpendicular to each of the first and second directions.

[0160] In some embodiments, the MP contact is shaped like a convex polygon.

[0161] In some embodiments, forming a metal-to-polysilicon (MP) contact includes: configuring a shape of the MP contact into a polygon with N sides relative to a reference plane defined by a first direction and a third direction, where N is an even number and 4≤N.

[0162] In some embodiments, forming the lower portion includes configuring the lower portion to include a lower portion of a corresponding nanowire; and forming the upper portion includes configuring the upper portion to include an upper portion of a corresponding nanowire.

[0163] In some embodiments, a semiconductor device includes: an active region (AR) including a first AR, a second AR, and a third AR, the first AR, the second AR, and the third AR each having a channel axis extending in a first direction, and each having a channel region located between a selected portion of an overlying first source / drain (S / D) region and a selected portion of an underlying second S / D region relative to the first direction, each of the ARs having a width axis extending in a second direction perpendicular to the first direction, and a thickness axis extending in a third direction perpendicular to the first direction and the second direction, and the width axis of the AR is aligned with a corresponding β reference track (β track) extending parallel to the second direction, such that The first AR is aligned with the first β track, and each of the second AR and the third AR is aligned with the second β track; a metal-to-gate (MG) contact, including a first MG contact, a second MG contact, and a second MG contact adjacent to the channel region of the first AR, the channel region of the second AR, and the channel region of the third AR, respectively; a metal-to-source / drain (MD) contact, including a first MD contact and a second MD contact, the first MD contact and the second MD contact being located above the first S / D region of the first AR and the first S / D region of the second AR and being coupled to the first S / D region of the first AR and the first S / D region of the second AR, respectively; a buried MD (BMD) contact A member, including a first BMD contact and a second BMD contact, the first BMD contact and the second BMD contact are located below the second S / D region of the first AR and the second S / D region of the second AR and are coupled to the second S / D region of the first AR and the second S / D region of the second AR respectively; a metal-to-polycrystalline silicon (MP) contact, located at the same level as the MG contact relative to the second direction, the MP contact including a first metal-to-polycrystalline silicon (MP) contact and a second metal-to-polycrystalline silicon (MP) contact extending between the first MG contact and the second MG contact relative to the first direction and coupling the first MG contact and the second MG contact together; M_ The M_1st segment in the 1st metallization layer has a long axis extending in the third direction and is aligned correspondingly with the α reference track (α track) extending in the third direction, the M_1st segment includes a first M_1st segment and a second M_1st segment aligned correspondingly with the adjacent first α track and second α track; and a through-hole pair M_1st (V_1st) contact, including a first V_1st contact and a second V_1st contact, the first V_1st contact and the second V_1st contact are located on the first M_1st segment and the second M_1st segment, aligned correspondingly with the first α track and the second α track and aligned with the first of the β tracks (the first β track).

[0164] In some embodiments, the AR further includes a fourth active region (AR) and a fifth active region (AR), each of the fourth AR and the fifth AR being aligned with the third β track; the MG contact further includes a fourth MG contact and a fifth MG contact respectively adjacent to the channel region of the fourth AR and the channel region of the fifth AR; the MD contact further includes a third MD contact and a fourth MD contact, the third MD contact and the fourth MD contact are located above the first S / D region of the fourth AR and the first S / D region of the fifth AR and are correspondingly coupled to the first S / D region of the fourth AR and the first S / D region of the fifth AR; a buried MD (BMD) contact includes a third BMD contact and a fourth BMD contact, the third BMD contact and the fourth BMD contact are located below the second S / D region of the fourth AR and the second S / D region of the fifth AR and are correspondingly coupled to the second S / D region of the fourth AR. D region and the second S / D region of the fifth AR; the MP contact further includes a third MP contact, which extends between the fourth MG contact and the fifth MG contact relative to the first direction and couples the fourth MG contact and the fifth MG contact together; the M_1st segment includes a third M_1st segment and a fourth M_1st segment respectively aligned with the second α track; each of the third M_1st segment and the fourth M_1st segment does not intersect with any of the β tracks except the corresponding second and third of the β tracks (the second β track and the third β track); and the V_1st contact further includes a third V_1st contact and a fourth V_1st contact, which are located on the third M_1st segment and the fourth M_1st segment, aligned with the second α track and corresponding to the second β track and the third β track.

[0165] In some embodiments, the first M_1st segment intersects the first β track and at least another of the β track; and the second M_1st segment does not intersect any of the β track other than the first β track.

[0166] In some embodiments, each of the first AR, the second AR, and the third AR is composed of a corresponding nanowire.

[0167] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the utility model, rather than to limit it. Although the utility model has been described in detail with reference to the aforementioned embodiments, ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the utility model.

Claims

1. A semiconductor device, characterized in that: The semiconductor device comprises: an active region (AR) comprising a first active region and a second active region separated relative to a first direction, the first active region and the second active region each having a channel axis extending in a second direction perpendicular to the first direction, and each having a channel region located between a selected portion of an overlying first source / drain (S / D) region and a selected portion of an underlying second source / drain (S / D) region relative to the second direction; a metal-to-gate (MG) contact, comprising a first metal-to-gate contact and a second metal-to-gate contact, the first metal-to-gate contact and the second metal-to-gate contact being respectively adjacent to the channel region of the first active region and the channel region of the second active region and being separated relative to the first direction; Metal-to-source / drain (MD) contacts and buried metal-to-source / drain (BMD) contacts, respectively coupled to the first source / drain region and the second source / drain region of the first active region and the first source / drain region and the second source / drain region of the second active region with respect to the second direction; and a metal-to-polysilicon (MP) contact located at the same level as the metal-to-gate contact relative to the second direction and extending between and coupling the first metal-to-gate contact and the second metal-to-gate contact relative to the first direction; and The first active region is substantially aligned with the second active region with respect to a third direction perpendicular to each of the first direction and the second direction; and Relative to the third direction, at least a portion of the metal-to-polysilicon contact substantially extends beyond each of the first active region and the second active region.

2. The semiconductor device according to claim 1, wherein: in: The active region further includes a third active region having a channel axis extending in the second direction and having a channel region located between the overlying first source / drain (S / D) region and the underlying second source / drain (S / D) region relative to the second direction; and With respect to the third direction, the third active area is separated from the first active area; and With respect to the third direction, the at least a portion of the metal-to-polysilicon contact at least partially overlaps the third active region.

3. The semiconductor device according to claim 1, wherein: in: The shape of the metal-to-polysilicon contact is an irregular polygon with respect to a reference plane defined by the first direction and the third direction perpendicular to each of the first direction and the second direction.

4. The semiconductor device according to claim 1, wherein: in: The shape of the metal-to-polysilicon contact is a concave polygon with respect to a reference plane defined by the first direction and the third direction perpendicular to each of the first direction and the second direction.

5. The semiconductor device according to claim 1, wherein: in: The shape of the metal-to-polysilicon contact is a convex polygon.

6. The semiconductor device according to claim 1, wherein: in: Relative to a reference plane defined by the first direction and the third direction, the shape of the metal-to-polysilicon contact is a polygon with N sides, where N is an even number and 4≤N.

7. The semiconductor device according to claim 6, wherein: in: N=4, so that the shape of the metal-to-polysilicon contact is a rectangle.

8. The semiconductor device according to claim 1, wherein: in: Each of the first active region and the second active region is composed of a corresponding nanowire.

9. A semiconductor device, characterized in that: include: an active region (AR) comprising a first active region, a second active region, and a third active region, wherein the first active region, the second active region, and the third active region each have a channel axis extending in a first direction and each have a channel region located between a selected portion of an overlying first source / drain (S / D) region and a selected portion of an underlying second source / drain (S / D) region relative to the first direction, Each of the active regions has a width axis extending in a second direction perpendicular to the first direction and a thickness axis extending in a third direction perpendicular to the first direction and the second direction, and the width axis of the active region is aligned with a corresponding beta reference track (beta track) extending parallel to the second direction, such that the first active region is aligned with a first beta track and each of the second and third active regions is aligned with a second beta track; Metal-to-gate (MG) contacts, including a first metal-to-gate contact, a second metal-to-gate contact, and a third metal-to-gate contact, wherein the first metal-to-gate contact, the second metal-to-gate contact, and the third metal-to-gate contact are respectively adjacent to the channel region of the first active region, the channel region of the second active region, and the channel region of the third active region; Metal-to-source / drain (MD) contacts, including a first metal-to-source / drain contact and a second metal-to-source / drain contact, the first metal-to-source / drain contact and the second metal-to-source / drain contact being located above the first source / drain region of the first active region and the first source / drain region of the second active region and being coupled to the first source / drain region of the first active region and the first source / drain region of the second active region, respectively; a buried metal-to-source / drain (BMD) contact, comprising a first buried metal-to-source / drain contact and a second buried metal-to-source / drain contact, the first buried metal-to-source / drain contact and the second buried metal-to-source / drain contact being located below the second source / drain region of the first active region and the second source / drain region of the second active region and being coupled to the second source / drain region of the first active region and the second source / drain region of the second active region, respectively; a metal-to-polysilicon (MP) contact located at the same level as the metal-to-gate contact relative to the second direction, the metal-to-polysilicon contact comprising a first metal-to-polysilicon (MP) contact and a second metal-to-polysilicon (MP) contact, the first metal-to-polysilicon (MP) contact and the second metal-to-polysilicon (MP) contact extending between the first metal-to-gate contact and the second metal-to-gate contact relative to the first direction and coupling the first metal-to-gate contact and the second metal-to-gate contact together; an M_1st segment in the M_1st metallization layer having a major axis extending in the third direction and aligned correspondingly with an α reference track (α track) extending in the third direction, the M_1st segment comprising a first M_1st segment and a second M_1st segment aligned correspondingly with adjacent first α track and second α track; and The through hole pair M_1st (V_1st) contact includes a first V_1st contact and a second V_1st contact, the first V_1st contact and the second V_1st contact are located on the first M_1st segment and the second M_1st segment, aligned with the first α track and the second α track respectively, and aligned with the first β track.

10. The semiconductor device according to claim 9, wherein: in: The active region further includes a fourth active region and a fifth active region, Each of the fourth active region and the fifth active region is aligned with a third β orbital; The metal-to-gate contact further includes a fourth metal-to-gate contact and a fifth metal-to-gate contact, wherein the fourth metal-to-gate contact and the fifth metal-to-gate contact are respectively adjacent to the channel region of the fourth active region and the channel region of the fifth active region; The metal-to-source / drain contact further includes a third metal-to-source / drain contact and a fourth metal-to-source / drain contact, wherein the third metal-to-source / drain contact and the fourth metal-to-source / drain contact are located above the first source / drain region of the fourth active region and the first source / drain region of the fifth active region and are coupled to the first source / drain region of the fourth active region and the first source / drain region of the fifth active region respectively; The buried metal to source / drain (BMD) contacts include a third buried metal to source / drain contact and a fourth buried metal to source / drain contact, the third buried metal to source / drain contact and the fourth buried metal to source / drain contact being located below the second source / drain region of the fourth active region and the second source / drain region of the fifth active region and being coupled to the second source / drain region of the fourth active region and the second source / drain region of the fifth active region, respectively; The metal-to-polysilicon contact further includes a third metal-to-polysilicon contact, the third metal-to-polysilicon contact extending between the fourth metal-to-gate contact and the fifth metal-to-gate contact relative to the first direction and coupling the fourth metal-to-gate contact and the fifth metal-to-gate contact together; The M_1st segment includes a third M_1st segment and a fourth M_1st segment, and the third M_1st segment and the fourth M_1st segment are aligned with the second α track correspondingly; Each of the third M_1st segment and the fourth M_1st segment does not intersect any of the β orbits except the corresponding second β orbit and the third β orbit; and The V_1st contact further includes a third V_1st contact and a fourth V_1st contact, and the third V_1st contact and the fourth V_1st contact are located on the third M_1st segment and the fourth M_1st segment, aligned with the second α track and correspondingly aligned with the second β track and the third β track.

Images