Current mirror layout structure

By compactly placing and matching transistors side by side, using substrate rings to surround the Mos tubes, the problems of poor matching performance and insufficient latch resistance are solved, and more stable output current and higher latch resistance are achieved.

CN222869307UActive Publication Date: 2025-05-13BEIJING GALLERIC ELECTRONICS CO LTD
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Patent Information

Application Number
CN202421634677.6
Authority / Receiving Office
CN · China
Patent Type
Utility models(China)
Current Assignee / Owner
Filing Date
2024-07-11
Publication Date
2025-05-13
Estimated Expiration
2034-07-11

AI Technical Summary

Technical Problem

The matching performance of the existing current mirror layout is poor, resulting in unstable output current, affecting the performance of subsequent circuits. At the same time, the latch resistance is insufficient and excessive power supply current is consumed, which may cause circuit failure.

Method used

By compactly placing the transistors that make up the current mirror, other transistors are placed on the outside, transistors of the same structure are matched side by side, and the MOS tubes are arranged in a consistent orientation, surrounding the mos tubes with a substrate ring, and the substrates with the same potential overlap part to ensure the matching performance and latch resistance of the current mirror layout.

Benefits of technology

It improves the matching performance of the mirror current source, enhances the latch resistance of the layout structure, and reduces the layout area and improves the compactness of the overall layout.

✦ Generated by Eureka AI based on patent content.

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Abstract

The utility model provides a current mirror layout structure. Grid electrodes of PM14, PM15, PM16, PM17, PM21 and PM22 are connected and then connected with an ENP port net1, a grid electrode of PM20 is connected with a drain electrode of PM16 and then connected with an ENP port net2, and a grid electrode of PM19 is connected with a drain electrode of PM15 and then connected with an ENP port net3. The grid electrode of the PM18 is connected with the ENP port, and the drain electrode of the PM18 is connected with the grid electrodes of the PM14, the PM15, the PM16, the PM17, the PM21 and the PM22; and PM18 is an enabling tube. According to the utility model, the enabling tube PM18 and the PM22 serving as the capacitor are placed independently, so that the matching performance of the current mirror main body is prevented from being damaged; pM20 and PM16 are regarded as a unit A, PM19 and PM15 are regarded as another unit B, and the unit A and the unit B are symmetrically placed; pM22, PM21, PM17 and PM14 are horizontally placed so as to ensure that the transistor orientations of the PM22, PM21, PM17 and PM14 are consistent with those of the unit A and the unit B, and the influence of the change of carrier mobility caused by stress and inclination of the transistor is avoided; a current mirror layout is surrounded by a substrate ring, an MOS capacitor PM22 is placed on the outermost side, and a substrate of an enabling tube PM18 and a substrate of a current mirror are partially overlapped.
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Description

Technical Field

[0001] The utility model relates to the technical field of electrical components, in particular to a structure of a current mirror layout. Background Art

[0002] The mirror current source (also called current mirror) can realize the mirroring and amplification functions of current. It is a widely used structure in integrated circuits (especially in the design of analog circuits and amplifiers). According to the adopted process, it can be divided into bipolar current mirror and MOS current mirror. The area required for MOS current mirror is about 1 / 4 of that of bipolar current mirror, and the production of MOS tube is easy to realize. With the advantages of high integration and high feasibility, MOS current mirror is more widely used in circuits.

[0003] The principle of the current mirror is to make the MOS tube work in the same working environment to output the same current. First of all, the process must meet the requirements that the intrinsic conductivity factor and threshold voltage of each MOS tube are the same and the width and length are proportional. Secondly, the MOS tube needs to work in the saturation region so that the conduction current of the MOS tube at this time satisfies the square law. Finally, the interference needs to be reduced on the layout to ensure the matching performance of the MOS tube as much as possible. The main function of the current mirror is to make the output current relatively stable and not affected by the external input voltage. However, poor matching performance of the current mirror will affect the output current, and then affect the performance of subsequent circuits.

[0004] Figure 1 is the current mirror circuit diagram, Figure 2 is the corresponding layout structure. Figure 1 There are 9 Pmos transistors in total, of which the gates of PM20 and PM19 are connected to the drains of PM16 and PM15 respectively; the gate of PM18 is connected to the ENP port; the gates of the remaining 6 Pmos transistors are connected together to the net1 port. PM18 is an enable transistor, and PM22 acts like a capacitor.

[0005] This structure has many disadvantages:

[0006] One is that the overall integration is poor and the area utilization is low.

[0007] The second is that the enabling tube and the MOS tube used as a capacitor are placed in the middle of the current mirror, which causes the MOS tubes constituting the current mirror to work in different environments, affecting the matching performance of the current mirror.

[0008] The third is that the distance between the substrate and some MOS tubes is relatively far, the anti-latch capability is poor, excessive power supply current is consumed, and circuit failure may also be caused.

[0009] Therefore, a well-matched current mirror layout structure is needed. Summary of the invention

[0010] The utility model aims to solve the matching problem of the current mirror layout, provide a structure of the current mirror layout, improve the matching performance of the mirror current source, improve the anti-latch capability of the layout structure, and minimize the layout area.

[0011] The utility model provides a structure of a current mirror layout, including PMOS tubes PM14, PM15, PM16, PM17, PM18, PM19, PM20, PM21, and PM22;

[0012] The gates of PM14, PM15, PM16, PM17, PM21, and PM22 are connected to ENP port net1, the gate of PM20 is connected to the drain of PM16 and then connected to ENP port net2, the gate of PM19 is connected to the drain of PM15 and then connected to ENP port net3; the gate of PM18 is connected to the ENP port, and the drain is connected to the gates of PM14, PM15, PM16, PM17, PM21, and PM22; PM18 is an enable tube;

[0013] The drain of PM14 is connected to the ENP port net1, and the source is connected to the drain of PM17. The source of PM17 is connected to the drain of PM21, and the source of PM21 is connected to the power supply VDD.

[0014] The source of PM18 is connected to the power supply VDD;

[0015] The source of PM15 is connected to the drain of PM19, the source of PM19 is connected to the power supply VDD, the source of PM16 is connected to the drain of PM20, and the source of PM20 is connected to the power supply VDD;

[0016] The source and drain of PM22 are both grounded;

[0017] In the layout structure, PM20 and PM16 form unit A, PM19 and PM15 form unit B, unit A and unit B are placed axially symmetrically, and unit A is located on the left side of unit B.

[0018] The structure of a current mirror layout described in the utility model is, as a preferred embodiment, PM14, PM17, PM21 and PM22 are arranged horizontally, PM20 is located above PM16, and PM19 is located above PM15.

[0019] The structure of a current mirror layout described in the utility model is, as a preferred embodiment, PM14, PM15, PM16, PM17, PM19, PM20, PM21, and PM22 share a common substrate, and PM22 is located on the left side inside the substrate.

[0020] The structure of a current mirror layout described in the present invention, as a preferred embodiment, enables the tube PM18 to be provided with a substrate separately.

[0021] The structure of a current mirror layout described in the present invention, as a preferred embodiment, enables the substrate of tube PM18 to partially overlap with the substrates of PM14, PM15, PM16, PM17, PM19, PM20, PM21, and PM22.

[0022] The structure of a current mirror layout described in the utility model, as a preferred method, enables the left side of the substrate of tube PM18 to partially overlap with the right side of the substrates of PM14, PM15, PM16, PM17, PM19, PM20, PM21, and PM22.

[0023] In the structure of a current mirror layout described in the present invention, as a preferred embodiment, the transistor orientations of unit A, unit B, PM14, PM17, PM21 and PM22 are all the same.

[0024] The structure of a current mirror layout described in the present invention is, as a preferred embodiment, poly is placed on the upper and lower parts of PM22, and virtual poly is set for unit A and unit B.

[0025] The structure of a current mirror layout described in the utility model is, as a preferred embodiment, the gates of PM14, PM15, PM16, PM17, PM21 and PM22 are connected by poly and pass through the M2 metal layer across the substrate.

[0026] In the structure of a current mirror layout described in the utility model, as a preferred embodiment, PM22 is used as a capacitor.

[0027] The utility model places transistors constituting the current mirror compactly, and places other transistors on the outside; transistors with the same structure are matched side by side, the orientations of adjacent MOS tubes are kept consistent, the MOS tubes are surrounded by substrate rings, and substrates with the same potential overlap a part, which not only ensures the matching performance of the current mirror layout, but also reduces the area of ​​the layout as much as possible, making the overall layout more compact.

[0028] The utility model has the following advantages:

[0029] (1) Considering the stability of signal transmission, the present invention places the enabling tube PM18 and PM22 acting as a capacitor separately to prevent them from destroying the matching performance of the current mirror body.

[0030] (2) In order to ensure that the environment around PM20 and PM19, PM15 and PM16 is consistent, the utility model regards PM20 and PM16 as unit A, PM19 and PM15 as another unit B, and places A and B symmetrically. A and B are placed in two rows, relative to Figure 2 The row structure is more compact. At the same time, a virtual poly is added to protect the MOS tube from corrosion.

[0031] (3) Considering that the orientation of transistors should be consistent, the utility model places PM22, PM21, PM17 and PM14 horizontally to ensure that the orientation is consistent with the transistors of unit A and unit B, thereby avoiding the influence of changes in carrier mobility caused by stress and tilt of the transistors.

[0032] (4) The utility model uses a substrate ring to surround the current mirror layout, places the MOS capacitor PM22 on the outermost side, and overlaps a portion of the substrate of the enabling transistor PM18 with the substrate of the current mirror. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A circuit diagram of an embodiment of a current mirror layout is provided as background technology and a circuit diagram;

[0034] Figure 2 A layout for background technology;

[0035] Figure 3 It is a structural layout of a current mirror layout. DETAILED DESCRIPTION

[0036] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments.

[0037] Example 1

[0038] like Figure 1 , 3 As shown, a structure of a current mirror layout includes PMOS tubes PM14, PM15, PM16, PM17, PM18, PM19, PM20, PM21, and PM22;

[0039] The gates of PM14, PM15, PM16, PM17, PM21, and PM22 are connected to ENP port net1, the gate of PM20 is connected to the drain of PM16 and then connected to ENP port net2, the gate of PM19 is connected to the drain of PM15 and then connected to ENP port net3; the gate of PM18 is connected to the ENP port, and the drain is connected to the gates of PM14, PM15, PM16, PM17, PM21, and PM22; PM18 is an enable tube;

[0040] The drain of PM14 is connected to the ENP port net1, and the source is connected to the drain of PM17. The source of PM17 is connected to the drain of PM21, and the source of PM21 is connected to the power supply VDD.

[0041] The source of PM18 is connected to the power supply VDD;

[0042] The source of PM15 is connected to the drain of PM19, the source of PM19 is connected to the power supply VDD, the source of PM16 is connected to the drain of PM20, and the source of PM20 is connected to the power supply VDD;

[0043] The source and drain of PM22 are both grounded;

[0044] In the layout structure, PM20 and PM16 form unit A, PM19 and PM15 form unit B, unit A and unit B are placed axially symmetrically, and unit A is located on the left side of unit B;

[0045] PM14, PM17, PM21, and PM22 are arranged horizontally, with PM20 located above PM16 and PM19 located above PM15;

[0046] PM14, PM15, PM16, PM17, PM19, PM20, PM21, and PM22 share a common substrate, with PM22 located on the left side inside the substrate;

[0047] The enabling tube PM18 is provided with a substrate separately;

[0048] The substrate of the enabling tube PM18 partially overlaps with the substrates of PM14, PM15, PM16, PM17, PM19, PM20, PM21, and PM22;

[0049] The left side of the substrate of the enabling tube PM18 partially overlaps with the right side of the substrates of PM14, PM15, PM16, PM17, PM19, PM20, PM21, and PM22;

[0050] The transistor orientations of cells A, B, PM14, PM17, PM21, and PM22 are all the same; polys are placed on the upper and lower parts of PM22, and dummy polys are set for cells A and B;

[0051] The gates of PM14, PM15, PM16, PM17, PM21, and PM22 are connected with poly and pass through the substrate through the M2 metal layer;

[0052] PM22 is used as a capacitor.

[0053] The utility model places the enabling tube PM18 and the PM22 acting as a capacitor separately to prevent them from damaging the matching performance of the current mirror body;

[0054] In this embodiment, A and B are as follows Figure 3 As shown, they are placed in two rows, relative to Figure 2 The row structure is more compact. At the same time, virtual poly is added to protect the MOS tube from corrosion;

[0055] PM22, PM21, PM17 and PM14 are placed horizontally to ensure consistency with the transistor orientation of units A and B, thereby preventing the transistors from being affected by changes in carrier mobility caused by stress and tilt.

[0056] The current mirror layout is surrounded by a substrate ring, the MOS capacitor PM22 is placed on the outermost side, and a portion of the substrate of the enabling transistor PM18 overlaps with the substrate of the current mirror.

[0057] Circuit diagram Figure 1 As shown, the layout is as Figure 3 As shown. Among them, the PMOS tubes with a length of 2 microns and a width of 1 micron include PM22, PM21, PM17, PM14, PM20 and PM19; the PMOS tubes with a length of 0.5 microns and a width of 1 micron include PM16 and PM15; the PMOS tubes with a length of 0.5 microns and a width of 0.5 microns include PM18.

[0058] The minimum spacing between MOS tubes is maintained, and the orientation is consistent. M20 and PM19, PM15 and PM16 are placed axially symmetrically, and the gates of the MOS tubes that form the current mirror are connected with poly and pass through M2 across the substrate. MOS capacitor PM22 is placed on the left, and poly is placed on the top and bottom to protect the transistor. Finally, a substrate ring is placed around it so that the substrate of the enable tube PM18 partially overlaps with the substrates of the other MOS tubes to reduce the area.

[0059] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes within the technical scope disclosed by the present invention according to the technical scheme and the utility model concept of the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A structure of a current mirror layout, characterized in that: Including PMOS tubes PM14, PM15, PM16, PM17, PM18, PM19, PM20, PM21, PM22; The gates of PM14, PM15, PM16, PM17, PM21, and PM22 are connected to ENP port net1, the gate of PM20 is connected to the drain of PM16 and then connected to ENP port net2, the gate of PM19 is connected to the drain of PM15 and then connected to ENP port net3; the gate of PM18 is connected to the ENP port, and the drain is connected to the gates of PM14, PM15, PM16, PM17, PM21, and PM22; PM18 is an enable tube; The drain of PM14 is connected to the ENP port net1, and the source is connected to the drain of PM17. The source of PM17 is connected to the drain of PM21, and the source of PM21 is connected to the power supply VDD. The source of PM18 is connected to the power supply VDD; The source of PM15 is connected to the drain of PM19, the source of PM19 is connected to the power supply VDD, the source of PM16 is connected to the drain of PM20, and the source of PM20 is connected to the power supply VDD; The source and drain of PM22 are both grounded; In the layout structure, PM20 and PM16 form unit A, PM19 and PM15 form unit B, unit A and unit B are placed axially symmetrically, and unit A is located on the left side of unit B.

2. The structure of a current mirror layout according to claim 1, characterized in that: PM14, PM17, PM21 and PM22 are arranged horizontally, PM20 is above PM16, and PM19 is above PM15.

3. The structure of a current mirror layout according to claim 2, characterized in that: PM14, PM15, PM16, PM17, PM19, PM20, PM21, and PM22 share a common substrate, and PM22 is located on the left side inside the substrate.

4. The structure of a current mirror layout according to claim 1, characterized in that: The enabling tube PM18 is provided with a separate substrate.

5. The structure of a current mirror layout according to claim 1, characterized in that: The substrate of the enabling tube PM18 partially overlaps with the substrates of PM14, PM15, PM16, PM17, PM19, PM20, PM21, and PM22.

6. The structure of a current mirror layout according to claim 5, characterized in that: The left side of the substrate of enabling tube PM18 partially overlaps with the right side of the substrates of PM14, PM15, PM16, PM17, PM19, PM20, PM21, and PM22.

7. The structure of a current mirror layout according to claim 1, characterized in that: The transistor orientations of unit A, unit B, PM14, PM17, PM21, and PM22 are all the same.

8. The structure of a current mirror layout according to claim 1, characterized in that: Poly is placed on the upper and lower parts of PM22, and virtual poly is set for unit A and unit B.

9. The structure of a current mirror layout according to claim 1, characterized in that: The gates of PM14, PM15, PM16, PM17, PM21, and PM22 are connected with poly and pass through the M2 metal layer across the substrate.

10. The structure of a current mirror layout according to claim 1, characterized in that: PM22 is used as a capacitor.