Array substrate, display panel and display device

Abstract

The utility model discloses an array substrate, a display panel and a display device. The array substrate comprises a plurality of pixel units, a plurality of scanning lines and a plurality of data lines which are arranged in an array mode. Each pixel unit comprises a transistor, a common electrode and a pixel electrode, the first end of the transistor is electrically connected with the pixel electrode, one scanning line is electrically connected with the control ends of the transistors in two adjacent rows of pixel units, and the second end of the transistor in one pixel unit is electrically connected with the adjacent data line; each pixel electrode comprises at least one hollow area extending in the array column direction, and the hollow areas are overlapped with the data lines in the direction perpendicular to the plane where the array substrate is located. According to the array substrate provided by the utility model, the contradiction between the capacitive load of the data line and the ITO Gap between the pixels is eliminated by optimizing the position relationship between the data line and the pixel electrode in the HG2D pixel architecture, and small data line capacitance and small ITO Gap are realized at the same time on the premise of not influencing the display effect.

Description

Technical Field

[0001] The utility model relates to the field of display technology, and in particular to an array substrate, a display panel and a display device. Background Art

[0002] An electronic paper screen is a display screen made using electrophoretic display technology. The control circuit on the array substrate applies a driving voltage to each pixel to achieve the effect of displaying an image. As a reflective display screen, the electronic paper screen can maintain the image for a long time without continuous refreshing after the image is updated, so the power consumption is very low. Due to its low power consumption, wide viewing angle, high contrast, eye protection and many other features, electronic paper screens are increasingly widely used in many fields such as electronic price tags, e-books, billboards, etc.

[0003] For strip electronic paper screens, the resolution difference between the long side and the short side is very large. Taking a strip electronic paper screen with a resolution of 1600×160 as an example, the resolution of the long side is ten times that of the short side, which makes it difficult to drive with a single driver chip. In order to achieve the driving of a strip electronic paper screen with a single driver chip, a pixel architecture of HG2D (Half Gate 2Data) is usually adopted, in which two rows of pixels share one scan line and each column of pixels contains two data lines, so that the number of scan lines on the long side is halved to 800 and the number of data lines on the short side is doubled to 320. In this way, you only need to select a driver chip with a resolution greater than or equal to 800×320 to achieve the driving of a strip electronic paper screen with a single chip.

[0004] For the strip electronic paper screen using the HG2D pixel architecture, since the length of the data line is close to the length of the long side of the electronic paper screen, there is the following contradiction between the data line capacitance load and the pixel electrode spacing (ITO Gap) between pixels in the existing pixel design: 1. If the data line and the pixel electrode layer (usually using indium tin oxide ITO) are overlapped, the ITO Gap between pixels will not increase, but the capacitance load of the data line will increase significantly, about two to five times, resulting in serious insufficient pixel charging and the screen cannot display normally; 2. If the data line and the pixel electrode of the ITO layer are not overlapped, the capacitance load of the data line will not increase, but the ITO Gap between pixels will increase significantly, about two to three times, resulting in poor display of horizontal stripes between pixels.

[0005] Therefore, for the HG2D pixel architecture, how to optimize the pixel design and eliminate the contradiction between the data line capacitance load and the ITOGap between pixels has become an urgent problem to be solved. Utility Model Content

[0006] The utility model provides an array substrate, a display panel and a display device. The array substrate is suitable for an electronic paper screen with an HG2D structure. By optimizing the positional relationship between data lines and pixel electrodes in the HG2D pixel architecture, the contradiction between the data line capacitance load and the ITO Gap between pixels is eliminated. Under the premise of not affecting the display effect, a small data line capacitance and a small ITO Gap are simultaneously achieved.

[0007] According to one aspect of the utility model, an array substrate is provided, comprising a plurality of pixel units arranged in an array, a plurality of scan lines extending along the row direction of the array, and a plurality of data lines extending along the column direction of the array;

[0008] The pixel unit comprises a transistor, a common electrode and a pixel electrode, a first end of the transistor is electrically connected to the pixel electrode, one of the scan lines is electrically connected to the control ends of the transistors in two adjacent rows of the pixel units, and a second end of the transistor in one of the pixel units is electrically connected to the adjacent data line;

[0009] The pixel electrode includes at least one hollow area extending along the array column direction, the size of the hollow area in the extension direction is smaller than the size of the pixel electrode in the array column direction, and the hollow area overlaps the data line along the direction perpendicular to the plane where the array substrate is located.

[0010] Optionally, the pixel electrode includes a block-shaped first electrode and a strip-shaped second electrode, the hollow area is located between the first electrode and the second electrode, and the first electrode and the second electrode are electrically connected via a connecting portion extending along the array row direction.

[0011] Optionally, along the array column direction, the sum of the size of the hollow area and the size of the connecting portion is equal to the size of the first electrode.

[0012] Optionally, the hollow area includes a first hollow area and a second hollow area, the first hollow area is located on a first side of the first electrode, and the second hollow area is located on a second side of the first electrode;

[0013] The second electrode includes a first branch electrode and a second branch electrode. The first branch electrode is located on a side of the first hollow region away from the first electrode, and the second branch electrode is located on a side of the second hollow region away from the first electrode.

[0014] Optionally, the connecting portion includes a first connecting portion and a second connecting portion, the first branch electrode is connected to the first electrode through the first connecting portion, and the second branch electrode is connected to the first electrode through the second connecting portion;

[0015] The first connecting portion and the second connecting portion are located on the same side or different sides of the first electrode.

[0016] Optionally, the hollow area is located on a first side of the first electrode or on a second side of the first electrode.

[0017] Optionally, in the pixel units in the same row, the hollow area is located on the same side of the first electrode in the same pixel electrode;

[0018] In the same column of the pixel units, the hollow regions of the pixel electrodes in two adjacent pixel units are located on different sides of the first electrode in the same pixel electrode.

[0019] According to another aspect of the present invention, a display panel is provided, comprising the above array substrate.

[0020] Optionally, it further includes an opposing substrate arranged opposite to the array substrate, and an electronic paper film is arranged between the array substrate and the opposing substrate.

[0021] According to another aspect of the present invention, a display device is provided, comprising the above-mentioned display panel.

[0022] The array substrate provided by the embodiment of the utility model comprises a plurality of pixel units arranged in an array, a plurality of scanning lines extending in the row direction of the array, and a plurality of data lines extending in the column direction of the array; the pixel unit comprises a transistor, a common electrode and a pixel electrode, a first end of the transistor is electrically connected to the pixel electrode, a scanning line is electrically connected to the control end of the transistor in two adjacent rows of pixel units, and a second end of the transistor in one pixel unit is electrically connected to the adjacent data line, thereby forming an HG2D pixel architecture; by setting the pixel electrode to include at least one hollow area extending in the column direction of the array, the size of the hollow area in the extension direction is smaller than the size of the pixel electrode in the column direction of the array, and the hollow area overlaps with the data line in a direction perpendicular to the plane where the array substrate is located, thereby optimizing the positional relationship between the data line and the pixel electrode in the HG2D pixel architecture, and setting a strip pixel electrode (located outside the hollow area) between two data lines of adjacent pixels, and connecting the strip pixel electrode to the main pixel electrode, so as to achieve neither increasing the data line capacitance load nor increasing the ITO Gap, thereby eliminating the contradiction between the data line capacitance load and the ITO Gap between pixels, and ensuring the normal display of the strip electronic paper screen.

[0023] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present utility model, nor are they intended to limit the scope of the present utility model. Other features of the present utility model will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0025] Figure 1 A schematic diagram of a pixel structure of an array substrate in the prior art;

[0026] Figure 2 A schematic diagram of a pixel structure of another array substrate in the prior art;

[0027] Figure 3 For Figure 1 The corresponding 2×2 pixel array schematic diagram;

[0028] Figure 4 For Figure 2 The corresponding 2×2 pixel array schematic diagram;

[0029] Figure 5 For Figure 3 Schematic diagram of the topological structure of the corresponding HG2D pixel array;

[0030] Figure 6 For Figure 4 Schematic diagram of the topological structure of the corresponding HG2D pixel array;

[0031] Figure 7 It is a schematic diagram of a film layer structure of an array substrate in the prior art;

[0032] Figure 8 For along Figure 1 Schematic diagram of the cross-section structure along the middle section line AA′;

[0033] Fig. 9 For along Figure 2 Schematic diagram of the cross-sectional structure along the middle section line BB′;

[0034] Fig.10 For along Figure 5 Schematic diagram of the cross-sectional structure along the center section line CC′;

[0035] Fig.11 For along Figure 6 Schematic diagram of the cross-sectional structure along the median section line DD′;

[0036] Fig.12 A schematic diagram of a pixel structure of an array substrate provided in an embodiment of the utility model;

[0037] Fig.13 For Fig.12 Schematic diagram corresponding to a 2×2 pixel array;

[0038] Fig.14 For Fig.13 Schematic diagram of the topological structure of the corresponding HG2D pixel array;

[0039] Fig.15 along Fig.12 Schematic diagram of the cross-sectional structure along the middle section line EE′;

[0040] Fig.16 For along Fig.14 Schematic diagram of the cross-sectional structure along the middle section line FF′;

[0041] Fig.17 A schematic diagram of a pixel structure of another array substrate provided in an embodiment of the utility model;

[0042] Fig.18 For Fig.17 Schematic diagram corresponding to a 2×2 pixel array;

[0043] Fig.19 For Fig.18 Schematic diagram of the topological structure of the corresponding HG2D pixel array;

[0044] Fig. 20 along Fig.17 Schematic diagram of the cross-sectional structure along the middle section line GG′;

[0045] Fig.21 For along Fig.19 Schematic diagram of the cross-sectional structure along the center line HH′. DETAILED DESCRIPTION

[0046] In order to enable those skilled in the art to better understand the solution of the utility model, the technical solution in the embodiment of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiment of the utility model. Obviously, the described embodiment is only a part of the embodiment of the utility model, not all of the embodiments. Based on the embodiment of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the utility model.

[0047] It should be noted that the terms "first", "second", etc. in the specification and claims of the utility model and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the utility model described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0048] Figure 1 is a schematic diagram of a pixel structure of an array substrate in the prior art. Figure 2 Schematic diagram of the pixel structure of another array substrate in the prior art. The array substrates in the embodiments of the present utility model can be used in electronic paper screens. The following description will be made by taking the electronic paper screen as an example. Figure 1 and Figure 2 , Figure 1 and Figure 2 Two HG2D pixel designs for existing strip-shaped e-paper screens were demonstrated. Figure 1 The pixel unit in the embodiment adopts the method of overlapping the data line 1 and the pixel electrode 2 of the ITO layer. Figure 2 The pixel unit in the embodiment adopts a method in which the data line 1 and the pixel electrode 2 of the ITO layer do not overlap. A pixel unit mainly includes a horizontal scan line 3, a vertical data line 1 (including the left data line 1-1 and the right data line 1-2), a transistor (TFT) 4, a common electrode (VCOM) 5, a pixel electrode 2 (including the ITO layer pixel electrode 2-1 and the source and drain SD layer pixel electrode 2-2) and a connection hole 6. The scan line 3 is connected to the gate of TFT4 and is responsible for controlling the switch of TFT4; the left data line 1-1 is connected to the source of the current pixel unit TFT4, and the right data line 1-2 is connected to the TFT4 of the next row of pixels ( Figure 1 and Figure 2The source electrode (not shown) of TFT4 is responsible for transmitting voltage signals to pixel electrode 2; the gate electrode, source electrode and drain electrode of TFT4 are respectively connected to scan line 3, data line 1 and pixel electrode 2, and are responsible for transmitting the voltage signal in data line 1 to pixel electrode 2 in sequence; the VCOM electrode formed by the gate layer is responsible for providing VCOM voltage; the overlapping part between pixel electrode 2-2 formed by SD layer and VCOM electrode formed by gate layer forms storage capacitor Cst, which is used to store pixel driving voltage transmitted by data line 1 to drive particle movement in electronic paper film; connection hole 6 includes via hole 6-1 formed by flat layer (Over Cover, OC) and via hole 6-2 formed by passivation layer (Passivation, PVX), which is responsible for connecting pixel electrode 2-2 formed by SD layer and pixel electrode 2-1 formed by ITO. In the existing pixel design, TFT4 used as control switch adopts double-gate structure. Similarly, single-gate TFT structure or multi-gate TFT structure can also be used, which is not limited here.

[0049] In a 1G1D (1Gate 1Data) pixel structure in which one scan line and one data line are set in each pixel unit, in order to realize the driving and control of the pixel unit, each pixel unit includes one horizontal scan line and one vertical data line. Therefore, a 2×2 pixel array also includes two horizontal scan lines and two vertical data lines.

[0050] Figure 3 For Figure 1 The corresponding 2×2 pixel array diagram, Figure 4 For Figure 2 The corresponding 2×2 pixel array diagram. Figure 3 or Figure 4 It can be seen that in the 2×2 HG2D pixel array, there is one horizontal scan line 3 and four vertical data lines 1. One horizontal scan line 3 connects the TFT gates of the upper and lower rows of pixels at the same time, and the two data lines 1 on the left and right of a column of pixels are used to connect the TFT sources of the odd and even rows of pixels in a column of pixels. Compared with the 1G1D pixel architecture, the HG2D pixel architecture can halve the number of gate lines and double the number of data lines.

[0051] Figure 5 For Figure 3 The corresponding topological structure diagram of the HG2D pixel array, Figure 6 For Figure 4 The corresponding topological structure diagram of the HG2D pixel array is shown in Figure 1. Figure 5 and Figure 6 Only the topological structure of the data line 1 and the ITO layer pixel electrode 2-1 is shown. Figure 5It can be seen that: 1. The pixel electrodes 2-1 between two adjacent pixel units are separated from each other, the distance between the pixel electrodes 2-1 is ITO Gap, and the ITO Gap of the pixel units in the horizontal and vertical directions are equal; 2. Inside each pixel unit, the data line 1 and the pixel electrode 2-1 overlap each other, and the overlapping part will form a coupling capacitor, causing the capacitive load on the data line 1 to increase significantly, about two to five times. Figure 6 It can be seen that: 1. The pixel electrodes 2-1 between two adjacent pixel units are separated from each other, and the distance between the pixel electrodes 2-1 is ITO Gap. The horizontal ITO Gap of the pixel unit is much larger than the vertical ITO Gap, and the horizontal ITO Gap is about two to three times the vertical ITO Gap; 2. Inside each pixel unit, the data line and the pixel electrode 2-1 do not overlap, and there is no overlapping coupling capacitance between the data line 1 and the pixel electrode 2-1.

[0052] Figure 7 is a schematic diagram of a film layer structure of an array substrate in the prior art, referring to Figure 7 , showing that the film layers are arranged on a glass substrate (Glass) 10, from bottom to top, they are a gate layer (Gate) 20, a gate insulation layer (Gate insulation, GI) 30, an active layer (Active) 40, a source and drain layer (SD) 50, a flat layer (OC) 60, a passivation layer (PVX) 70 and an ITO layer 80. The Gate layer is used to form the scan line, the gate of the TFT and the VCOM electrode, and is usually made of conductive materials such as Mo, Al, Nd, and Cu; the GI layer is used to isolate the Gate layer and the SD layer, and is usually made of SiNx or SiO 2 The Active layer is used to form the conductive channel of the TFT, and is usually made of a-Si, p-Si, IGZO or other semiconductor materials; the SD layer is used to form the data line, the source, drain and pixel electrode of the TFT, and is usually made of conductive materials such as Mo, Al, Nd, and Cu; the OC layer and the PVX layer are used to isolate the SD layer from the ITO layer, and the OC layer is usually made of organic resin materials, and the PVX layer is usually made of SiNx or SiO 2 Insulating materials such as ITO; the ITO layer is used to form pixel electrodes, and transparent conductive materials such as ITO are usually used.

[0053] Figure 8 For along Figure 1 Schematic diagram of the cross-section structure along the middle section line AA′. Fig. 9 For along Figure 2 Schematic diagram of the cross-section structure of the middle section line BB′, refer to Figure 8 and Fig. 9 , from left to right are data line 1-1, TFT-1, TFT-2, connection hole 6, common electrode 5, storage capacitor Cst and data line 1-2. Figure 8 and Fig. 9 It can be seen that: 1. Data line 1-1 is connected to the source of TFT-1; 2. The drain of TFT-1 is connected to the source of TFT-2; 3. The drain of TFT-2 is connected to the pixel electrode 2-2 of the SD layer; 4. The pixel electrode 2-2 of the SD layer is connected to the pixel electrode 2-1 of the ITO layer through the connection hole 6 of the OC layer and the PVX layer; 5. The VCOM electrode 5 of the Gate layer and the pixel electrode 2-2 of the SD layer form a storage capacitor Cst. Figure 8 In the example, the data line and the pixel electrode of the ITO layer overlap each other. Fig. 9 In the embodiment, the data line and the pixel electrode of the ITO layer do not overlap each other.

[0054] Fig.10 For along Figure 5 Schematic diagram of the cross-section structure along the center section line CC′. Fig.11 For along Figure 6 Schematic diagram of the cross-section structure of the middle section line DD′, refer to Fig.10 and Fig.11 , the figure shows the positional relationship between the data line 1 and the pixel electrode 2-1 of the ITO layer. Fig.10 It can be seen that: 1. The line width of data line 1 is W1, which is usually about 6μm. Data line 1 and pixel electrode 2-1 of the ITO layer overlap with each other, and the overlap width is W1. This overlap width will cause a significant increase in the capacitance load of data line 1; 2. The width of the pixel electrode 2-1 of the ITO layer wrapping around data line 1 is S1, which is usually about 3μm. S1 is to ensure that the pixel electrode 2-1 wraps around the data line 1 during process fluctuations; 3. The ITO Gap is G1, which is usually about 12μm. Reference Fig.11 It can be seen that: 1. The line width of data line 1 is W1, which is usually about 6μm, and the data line 1 and the pixel electrode 2-1 of the ITO layer do not overlap with each other; 2. The distance between data lines 1 is S2, which is usually about 6μm; 3. The distance between the pixel electrode 2-1 of the ITO layer and the data line 1 is S3, which is usually about 3μm. S3 is to ensure that the pixel electrode 2-1 and the data line 1 do not overlap during process fluctuations; 4. ITO Gap is G2, where G2=W1×2+S2+S3×2. Calculation shows that G2 is about 24μm. An ITO Gap greater than 14μm will cause horizontal stripes between pixels.

[0055] For the strip electronic paper screen using the HG2D pixel architecture, since the length of the data line is close to the length of the long side of the electronic paper screen, there is the following contradiction between the data line capacitance load and the ITO Gap between pixels in the existing pixels: 1. If the data line and the pixel electrode of the ITO layer overlap, the ITO Gap between pixels will not increase, but the capacitance load of the data line will increase significantly, about two to five times, resulting in serious insufficient pixel charging and the screen cannot display normally; 2. If the data line and the pixel electrode of the ITO layer do not overlap, the capacitance load of the data line will not increase, but the ITO Gap between pixels will increase significantly, about two to three times, resulting in poor display of horizontal stripes between pixels.

[0056] In order to solve the above problems, an embodiment of the utility model provides an array substrate, including a plurality of pixel units arranged in an array, a plurality of scan lines extending along the row direction of the array, and a plurality of data lines extending along the column direction of the array; the pixel unit includes a transistor, a common electrode and a pixel electrode, a first end of the transistor is electrically connected to the pixel electrode, a scan line is electrically connected to the control end of the transistor in two adjacent rows of pixel units, and a second end of the transistor in a pixel unit is electrically connected to the adjacent data line; the pixel electrode includes at least one hollow area extending along the column direction of the array, the size of the hollow area in the extension direction is smaller than the size of the pixel electrode in the column direction of the array, and the hollow area overlaps with the data line along a direction perpendicular to the plane where the array substrate is located.

[0057] The technical solution of the embodiment of the utility model is to set the pixel electrode to include at least one hollow area extending along the array column direction, the size of the hollow area in the extension direction is smaller than the size of the pixel electrode in the array column direction, and the hollow area overlaps with the data line in the direction perpendicular to the plane where the array substrate is located, thereby optimizing the positional relationship between the data line and the pixel electrode in the HG2D pixel architecture, and setting a strip pixel electrode (located outside the hollow area) between two data lines of adjacent pixels, and connecting the strip pixel electrode to the main pixel electrode, so as to achieve neither increasing the data line capacitance load nor increasing the ITO Gap, thereby eliminating the contradiction between the data line capacitance load and the ITO Gap between pixels, and ensuring the normal display of the strip electronic paper screen.

[0058] The above is the core idea of ​​the present invention. The following describes the specific embodiments of the present invention in conjunction with the accompanying drawings.

[0059] Fig.12 A schematic diagram of a pixel structure of an array substrate provided in an embodiment of the utility model, Fig.12A new type of HG2D pixel design is shown. The pixel unit mainly includes a horizontal scan line 300, a vertical data line 100 (including a data line 100-1 and a data line 100-2, a TFT 400, a VCOM electrode 500, a pixel electrode 200 (including an ITO layer pixel electrode 200-1 and an SD layer pixel electrode 200-2) and a connection hole 600. The scan line 300 is connected to the gate (control end) of the TFT 400 and is responsible for controlling the switch of the TFT 400; the data line 100-1 is connected to the source (second end) of the current pixel unit TFT, and the data line 100-2 is connected to the next pixel unit TFT ( Fig.12 The source electrode of the TFT 400 (not shown) is responsible for transmitting a voltage signal to the pixel electrode 200; the gate, source, and drain (first end) of the TFT 400 are respectively connected to the scan line 300, the data line 100, and the pixel electrode 200, and are responsible for transmitting the voltage signal in the data line 100 to the pixel electrode 200 in sequence; the VCOM electrode 500 formed by the Gate layer is responsible for providing the VCOM voltage; the overlapping portion between the pixel electrode 200-2 formed by the SD layer and the VCOM electrode 500 formed by the Gate layer forms a storage capacitor Cst, which is used to store the pixel driving voltage transmitted by the data line 100 to drive the electronic paper film; the connection hole 600 includes a via 600-1 formed by the OC layer and a via 600-2 formed by the PVX layer, which is responsible for connecting the pixel electrode 200-2 formed by the SD layer and the pixel electrode 200-1 formed by ITO. In the existing pixel unit design, the TFT control switch adopts a dual-gate TFT structure. Similarly, a single-gate TFT structure or a multi-gate TFT structure can also be used, which is not limited here.

[0060] In this embodiment, a hollow region 201 is provided on the pixel electrode 200-1 of the ITO layer, and the hollow region 201 overlaps with the data line 100 in a direction perpendicular to the plane where the array substrate is located, thereby effectively reducing the coupling capacitance on the data line 100. Fig.12 The pixel electrode 200-1 includes a block-shaped first electrode 202 and a strip-shaped second electrode 203. The hollow area 201 is located between the first electrode 202 and the second electrode 203. The first electrode 202 and the second electrode 203 are electrically connected through a connecting portion 204 extending along the array row direction.

[0061] Optional, continue to refer to Fig.12 The hollow region 201 includes a first hollow region 201-1 and a second hollow region 201-2. The first hollow region 201-1 is located on a first side of the first electrode 202 ( Fig.12 The second hollow region 201-2 is located on the second side of the first electrode 202 ( Fig.12The second electrode 203 includes a first branch electrode 203-1 and a second branch electrode 203-2, the first branch electrode 203-1 is located on a side of the first hollow area 201-1 away from the first electrode 202, and the second branch electrode 203-2 is located on a side of the second hollow area 201-2 away from the first electrode 202. Optionally, the connecting portion 204 includes a first connecting portion 204-1 and a second connecting portion 204-2, the first branch electrode 203-1 is connected to the first electrode 202 through the first connecting portion 204-1, and the second branch electrode 203-2 is connected to the first electrode 202 through the second connecting portion 204-2; wherein the first connecting portion 204-1 and the second connecting portion 204-2 are located on the same side or different sides of the first electrode 202.

[0062] Understandably, Fig.12 The first connection portion 204-1 is shown to be located on the upper side of the first electrode 202, and the second connection portion 204-2 is located on the lower side of the first electrode 202, that is, the first connection portion 204-1 and the second connection portion 204-2 are located on different sides of the first electrode 202. This is only for illustration. In other embodiments, the first connection portion 204-1 and the second connection portion 204-2 may be located on the same side of the first electrode 202, for example, at the upper side or the lower side at the same time. The specific implementation may be designed according to actual conditions. In other embodiments, the number of connection portions between the first electrode and the second electrode is not limited to one, and the specific implementation may be designed according to actual conditions.

[0063] Exemplarily, in this embodiment, according to the shape of the pixel electrode 200-1 of the ITO layer, the pixel electrode 200-1 can be divided into five parts: 1. The first electrode 202 between the data line 100-1 and the data line 100-2; 2. The first branch electrode 203-1 in the shape of a strip on the left side of the data line 101-1; 3. The first connecting portion 204-1 connecting the first electrode 202 and the first branch electrode 203-1; 4. The second branch electrode 203-2 in the shape of a strip on the right side of the data line 100-2; 5. The second connecting portion 204-2 connecting the first electrode 202 and the second branch electrode 203-2. Optionally, along the direction of the array column (i.e. Fig.12 In the vertical direction), the sum of the size of the hollow area 201 and the size of the connecting portion 204 is equal to the size of the first electrode 202.

[0064] In the above pixel structure, only the connection portion 204 overlaps with the data line 100. By setting the width of the connection portion 204 to the minimum width that can be guaranteed by the process, the increase in the capacitance load on the data line can be effectively controlled, with an increase rate of about 6%.

[0065] Fig.13 For Fig.12 Corresponding to the schematic diagram of the 2×2 pixel array, refer to Fig.13 , showing Fig.12The 2×2 array diagram corresponding to the pixel unit in . Fig.13 It can be seen that in the 2×2 HG2D pixel array, there is a horizontal scan line 300 and four vertical data lines 100. One horizontal scan line 300 connects the TFT gates of the upper and lower rows of pixel units at the same time, and the two data lines 100 on the left and right of a column of pixel units are used to connect the TFT source electrodes of the odd and even rows of pixel units in a column of pixel units respectively. Compared with the 1G1D pixel architecture, the HG2D pixel architecture can halve the number of gate lines and double the number of data lines.

[0066] Fig.14 For Fig.13 The corresponding topological structure diagram of the HG2D pixel array is shown in Figure 1. Fig.14 Only the topological structure of the data line 100 and the pixel electrode 200-1 of the ITO layer is shown. Fig.14 It can be seen that: 1. The pixel electrodes 200-1 between two adjacent pixel units are separated from each other, the distance between the pixel electrodes 200-1 is ITO Gap, and the ITO Gap of the pixel unit is equal in the horizontal and vertical directions; 2. Inside each pixel unit, the pixel electrode 200-1 and the data line 100 are arranged at intervals, and there is a small overlap between the pixel electrode 200-1 and the two data lines 100, and the overlap area is about 60μm 2 about.

[0067] Fig.15 along Fig.12 Schematic diagram of the cross-section structure along the middle section line EE′, see Fig.15 , from left to right are the data line 100 - 1 , TFT- 1 , TFT- 2 , the connection hole 600 , the common electrode 500 , the storage capacitor Cst and the data line 100 - 2 . Fig.15 It can be seen that: 1. Data line 100-1 is connected to the source of TFT-1; 2. The drain of TFT-1 is connected to the source of TFT-2; 3. The drain of TFT-2 is connected to the pixel electrode 200-2 of the SD layer; 4. The pixel electrode 200-2 of the SD layer is connected to the pixel electrode 200-1 of the ITO layer through the connection hole 600 of the OC layer and the PVX layer; 5. The VCOM electrode 500 of the Gate layer and the pixel electrode 200-2 of the SD layer form a storage capacitor Cst. Fig.15 In the example, two strip pixel electrodes ( Fig.12 As shown in the first branch electrode 203-1 and the second branch electrode 203-2, the data line 100-1 and the data line 100-2 are located at the hollow position of the pixel electrode 200-1, and most of the data line area does not overlap with the pixel electrode of the ITO layer.

[0068] Fig.16 For along Fig.14 Schematic diagram of the cross-section structure along the middle section line FF′. Fig.16 The positional relationship between the data line 100 and the pixel electrode 200-1 of the ITO layer is shown in FIG. Fig.16 It can be seen that: 1. The line width of the data line 100 is W1, which is usually about 6μm, and the data line 100 and the pixel electrode 200-1 of the ITO layer do not overlap; 2. The distance between the pixel electrode 200-1 of the ITO layer and the data line 100 is S3, which is usually about 3μm. S3 is to ensure that the pixel electrode and the data line do not overlap during process fluctuations; 3. The width of the strip pixel branch electrode is W2, which is usually more than 10μm; 4. The ITO Gap is G3, which is usually about 12μm. Due to process errors, the above width of ±2μm is acceptable.

[0069] In the present embodiment, two strip-shaped pixel branch electrodes are arranged between the data lines of two pixel units, so there are three ITO Gaps. However, since the width of the three ITO Gaps is about 12 μm, which is equivalent to the ITO Gap of the existing 1G1D pixel architecture, it will neither significantly increase the capacitive load of the data routing nor increase the ITO Gap to affect the display effect.

[0070] Fig.17 A schematic diagram of a pixel structure of another array substrate provided in an embodiment of the utility model is shown. Fig.17 Another new type of HG2D pixel design is shown. The pixel unit mainly includes a horizontal scan line 300, a vertical data line 100 (including a data line 100-1 and a data line 100-2), a TFT 400, a VCOM electrode 500, a pixel electrode 200 (including an ITO layer pixel electrode 200-1 and an SD layer pixel electrode 200-2) and a connection hole 600. Other basic structures and connection relationships can refer to the above embodiments and will not be described in detail here.

[0071] In this embodiment, a hollow region 201 is provided on the pixel electrode 200-1 of the ITO layer, and the hollow region 201 overlaps with the data line 100 in a direction perpendicular to the plane where the array substrate is located, thereby effectively reducing the coupling capacitance on the data line 100. Fig.17 The pixel electrode 200-1 includes a block-shaped first electrode 202 and a strip-shaped second electrode 203. The hollow region 201 is located between the first electrode 202 and the second electrode 203. The first electrode 202 and the second electrode 203 are electrically connected through a connecting portion 204 extending along the array row direction. Optionally, the hollow region 201 is located on the first side of the first electrode 202 or on the second side of the first electrode 202. Exemplarily, Fig.172 shows that the second electrode 203 is disposed on the left side of the first electrode 202. However, in actual applications, the second electrode 203 can be disposed on the left side or the right side of the first electrode 202, which is not limited here.

[0072] For example, in this embodiment, according to the form of the pixel electrode 200-1 of the ITO layer, the pixel electrode 200-1 can be divided into three parts: 1. The first electrode 202 between the data line 100-1 and the data line 100-2; 2. The first branch electrode 203 in the shape of a strip on the left side of the data line 101-1; 3. The connecting portion 204 connecting the first electrode 202 and the second electrode 203. In the above pixel structure, only the connecting portion 204 overlaps with the data line 100. By setting the width of the connecting portion 204 to the minimum width that can be guaranteed by the process, the increase in the capacitance load on the data line can be effectively controlled, and the increase ratio is about 3%.

[0073] Fig.18 For Fig.17 Corresponding to the schematic diagram of the 2×2 pixel array, refer to Fig.18 , showing Fig.17 2×2 array diagram corresponding to the pixels in . Optionally, in the same row of pixel units, the hollow region 201 is located on the same side of the first electrode 202 in the same pixel electrode; in the same column of pixel units, the hollow regions 201 of the pixel electrodes in two adjacent pixel units are located on different sides of the first electrode 202 in the same pixel electrode. Fig.18 It can be seen that in the 2×2 HG2D pixel array, there is a horizontal scan line 300 and four vertical data lines 100. One horizontal scan line 300 connects the TFT gates of the upper and lower rows of pixels at the same time, and the two data lines 100 on the left and right of a column of pixels are used to connect the TFT sources of the odd and even rows of pixels in a column of pixels respectively. Compared with the 1G1D pixel architecture, the HG2D pixel architecture can halve the number of gate lines and double the number of data lines.

[0074] Fig.19 For Fig.18 The corresponding topological structure diagram of the HG2D pixel array is shown in Figure 1. Fig.19 Only the topological structure of the data line 100 and the pixel electrode 200-1 of the ITO layer is shown. Fig.19 It can be seen that: 1. The pixel electrodes 200-1 between two adjacent pixel units are separated from each other, the distance between the pixel electrodes 200-1 is ITO Gap, and the ITO Gap of the pixel unit is equal in the horizontal and vertical directions; 2. Inside each pixel unit, the pixel electrode 200-1 and the data line 100 are arranged at intervals, and the pixel electrode 200-1 only has a small overlap with a single data line 100, and the overlap area is about 60μm 2 about.

[0075] Fig. 20 along Fig.17 Schematic diagram of the cross-section structure of the middle section line GG′, refer to Fig. 20 , from left to right are the data line 100-1, TFT-1, TFT-2, the connection hole 600, the common electrode 500, the storage capacitor Cst and the data line 100-2. Fig. 20 It can be seen that: 1. Data line 100-1 is connected to the source of TFT-1; 2. The drain of TFT-1 is connected to the source of TFT-2; 3. The drain of TFT-2 is connected to the pixel electrode 200-2 of the SD layer; 4. The pixel electrode 200-2 of the SD layer is connected to the pixel electrode 200-1 of the ITO layer through the connection hole 600 of the OC layer and the PVX layer; 5. The VCOM electrode 500 of the Gate layer and the pixel electrode 200-2 of the SD layer form a storage capacitor Cst. Fig. 20 In the example, a strip pixel electrode ( Fig.17 The second electrode 203 is formed in the middle, the data line 100-1 and the data line 100-2 are located at the hollow position of the pixel electrode 200-1, and most areas of the data lines do not overlap with the pixel electrode of the ITO layer.

[0076] Fig.21 For along Fig.19 Schematic diagram of the cross-section structure along the middle section line HH′. Fig.21 The positional relationship between the data line 100 and the pixel electrode 200-1 of the ITO layer is shown in FIG. Fig.21 It can be seen that: 1. The line width of the data line 100 is W1, which is usually about 6μm, and the data line 100 and the pixel electrode 200-1 of the ITO layer do not overlap; 2. The distance between the pixel electrode 200-1 of the ITO layer and the data line 100 is S3, which is usually about 3μm. S3 is to ensure that the pixel electrode and the data line do not overlap during process fluctuations; 3. The width of the strip pixel electrode (second electrode) is W2, which is usually more than 10μm; 4. The ITO Gap is G3, which is usually about 12μm. Due to process errors, the above width of ±2μm is acceptable.

[0077] In the present embodiment, a strip pixel electrode is arranged between the data lines of the two pixel units, and thus there are two ITO Gaps. However, since the widths of the two ITO Gaps are both about 12 μm, which is equivalent to the ITO Gap of the existing 1G1D pixel architecture, the capacitive load of the data wiring will not be significantly increased, and the increase in the ITO Gap will not affect the display effect.

[0078] Based on the same concept, an embodiment of the utility model further provides a display panel, comprising any array substrate provided in the above embodiments.

[0079] Since the display panel provided by the embodiment of the utility model includes any one of the array substrates provided by the above embodiments and has the same or corresponding technical effects as the array substrate, it will not be described in detail here.

[0080] Optionally, the display panel may be an electronic paper screen, and the display panel further includes an opposing substrate disposed opposite to the array substrate, and an electronic paper film is disposed between the array substrate and the opposing substrate.

[0081] Based on the same concept, the embodiment of the utility model further provides a display device, including the above-mentioned display panel. The display device can be an electronic price tag, an electronic book, a billboard, etc.

[0082] The above specific implementations do not constitute a limitation on the protection scope of the present utility model. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present utility model shall be included in the protection scope of the present utility model.

Claims

1. An array substrate, characterized in that: It includes a plurality of pixel units arranged in an array, a plurality of scanning lines extending along the row direction of the array, and a plurality of data lines extending along the column direction of the array; The pixel unit comprises a transistor, a common electrode and a pixel electrode, a first end of the transistor is electrically connected to the pixel electrode, one of the scan lines is electrically connected to the control ends of the transistors in two adjacent rows of the pixel units, and a second end of the transistor in one of the pixel units is electrically connected to the adjacent data line; The pixel electrode includes at least one hollow area extending along the array column direction, the size of the hollow area in the extension direction is smaller than the size of the pixel electrode in the array column direction, and the hollow area overlaps the data line along the direction perpendicular to the plane where the array substrate is located.

2. The array substrate according to claim 1, characterized in that: The pixel electrode includes a block-shaped first electrode and a strip-shaped second electrode. The hollow area is located between the first electrode and the second electrode. The first electrode and the second electrode are electrically connected via a connecting portion extending along the array row direction.

3. The array substrate according to claim 2, characterized in that: Along the array column direction, the sum of the size of the hollow area and the size of the connecting portion is equal to the size of the first electrode.

4. The array substrate according to claim 2, characterized in that: The hollow area includes a first hollow area and a second hollow area, the first hollow area is located on a first side of the first electrode, and the second hollow area is located on a second side of the first electrode; The second electrode includes a first branch electrode and a second branch electrode. The first branch electrode is located on a side of the first hollow region away from the first electrode, and the second branch electrode is located on a side of the second hollow region away from the first electrode.

5. The array substrate according to claim 4, characterized in that: The connecting portion includes a first connecting portion and a second connecting portion, the first branch electrode is connected to the first electrode through the first connecting portion, and the second branch electrode is connected to the first electrode through the second connecting portion; The first connecting portion and the second connecting portion are located on the same side or different sides of the first electrode.

6. The array substrate according to claim 2, characterized in that: The hollow area is located on a first side of the first electrode or on a second side of the first electrode.

7. The array substrate according to claim 6, characterized in that: In the pixel units in the same row, the hollow regions are located on the same side of the first electrode in the same pixel electrode; In the same column of the pixel units, the hollow regions of the pixel electrodes in two adjacent pixel units are located on different sides of the first electrode in the same pixel electrode.

8. A display panel, characterized in that: It comprises the array substrate according to any one of claims 1 to 7.

9. The display panel according to claim 8, characterized in that: It also includes an opposing substrate arranged opposite to the array substrate, and an electronic paper film is arranged between the array substrate and the opposing substrate.

10. A display device, characterized in that: Comprising the display panel according to claim 8 or 9.

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