Driving circuit for inverter power supply

Abstract

The utility model discloses a drive circuit for an inverter power supply, which is characterized by comprising a control chip for sending a drive signal, the output end of the control chip is connected with an enable circuit, the output end of the enable circuit is connected with an anti-straight-through logic circuit, and the output end of the anti-straight-through logic circuit is connected with an inverter power supply. The output end of the control chip is connected with an enabling circuit, the output end of the direct connection prevention logic circuit is connected with an isolation driving circuit, and a driving signal sent by the control chip is output after passing through the enabling circuit, the direct connection prevention logic circuit and the isolation driving circuit and is used for driving a power switch tube. Or after the whole machine is abnormal, the PWM is sealed at the first time, and the whole machine is protected; meanwhile, the anti-straight-through circuit is arranged, the anti-straight-through circuit is composed of a logic chip, the cost is low, the structure is simple, the function is stable, and when the MCU chip is abnormal and all pins output high level, the circuit can effectively prevent the switch tube from straight through, and a good protection effect is achieved.

Description

Technical Field

[0001] The utility model relates to the technical field of drive circuits, in particular to a drive circuit for an inverter power supply. Background Art

[0002] In inverter power supplies, full-bridge circuits are widely used. Each bridge arm includes a power switch tube. The power switch tube is an important part of the inverter power supply and is very expensive. However, the inverter circuit usually causes the bridge arm to be directly connected due to chip reset, level conversion chip failure, or power supply abnormality, resulting in failures such as power tube explosion, and even disasters such as fire. In the existing method, the drive circuit is usually driven and controlled by logic chips such as CPLD or FPGA after DSP output, and then through the level conversion chip, and then through the driving optical coupler to drive the power tube. However, logic chips such as CPLD or FPGA are particularly expensive, complex in function, and have problems such as functional redundancy. Utility Model Content

[0003] The purpose of the utility model is to provide a driving circuit for an inverter power supply to solve the problems raised in the above background technology.

[0004] In order to achieve the above purpose, the utility model provides the following technical solutions:

[0005] A drive circuit for an inverter power supply includes a control chip for sending a drive signal, wherein the output end of the control chip is connected to an enable circuit, the output end of the enable circuit is connected to an anti-straight-through logic circuit, the output end of the anti-straight-through logic circuit is connected to an isolation drive circuit, and the drive signal sent by the control chip is output after passing through the enable circuit, the anti-straight-through logic circuit, and the isolation drive circuit and is used to drive a power switch tube.

[0006] As a further solution of the utility model: the control chip is an MCU control chip, which is used to send complementary PWM signals PMW1 and PWM2.

[0007] As a further solution of the utility model: the enabling circuit includes AND gate circuits IC1A and IC1B for receiving control chip drive signals PMW1 and PWM2, and an input enable signal EN. The AND gate circuit IC1A outputs a PWM1 EN signal after receiving the drive signal PWM1 and the enable signal EN, and the AND gate circuit IC1B outputs a PWM2 EN signal after receiving the drive signal PWM2 and the enable signal EN.

[0008] As a further solution of the utility model: the enabling circuit adopts the MC74LVXC3245 chip, and the PWM signal is converted from a low level to a high level after passing through the enabling circuit.

[0009] As a further solution of the utility model: the anti-straight-through logic circuit includes NOT gate circuits IC2C, IC2D and AND gate circuits IC1C, IC1D; the PWM1 EN signal passes through the NOT gate circuit IC2C and is input into the AND gate circuit IC1C with the PWM2 EN signal, passes through the gate circuit IC1C and outputs the PWM2 LDRV signal to the isolation drive circuit; the PWM2 EN signal passes through the NOT gate circuit IC2D and is input into the AND gate circuit ICID with the PWM1 EN signal, passes through the AND gate circuit IC1D and outputs the PWM1LDRV signal to the isolation drive circuit.

[0010] As a further solution of the utility model: the isolation driving circuit includes an amplifier Q3 connected to the PWM1 LEDRV signal, and an isolation optocoupler U1 connected to the output end of the amplifier Q3, and the output end of the isolation optocoupler U1 is connected to the driving power switch.

[0011] As a further solution of the utility model: the isolation driving circuit includes an amplifier Q4 connected to the PWM2 LEDRV signal, and an isolation optocoupler U2 connected to the output end of the amplifier Q4, and the output end of the isolation optocoupler U2 is connected to the driving power switch.

[0012] Compared with the prior art, the beneficial effects of the utility model are:

[0013] 1. This application introduces an enable signal by arranging an enable circuit to ensure that it becomes a high level after power-on stabilization, or when an abnormal situation occurs in the whole machine, PWM is immediately turned off to protect the whole machine;

[0014] 2. The present application sets up an anti-straight-through logic circuit. The anti-straight-through logic circuit of the present application is composed of a logic chip, which has low cost, simple structure, and stable function. When the MCU chip is abnormal and all pins output a high level, the circuit can effectively prevent the switch tube from being straight-through, and play a good protective role;

[0015] 3. This application also has an isolation drive circuit to isolate the high voltage from the control circuit, and separate the high voltage from the low voltage, making the system safer. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a principle block diagram of the driving circuit of this embodiment;

[0017] Figure 2 This is the enabling circuit diagram for this embodiment;

[0018] Figure 3 This is the anti-through logic circuit diagram of this embodiment;

[0019] Figure 4This is the isolation driving circuit diagram of this embodiment;

[0020] Figure 5 FIG. 4 is another enabling circuit diagram of this embodiment. DETAILED DESCRIPTION

[0021] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0022] Example 1

[0023] See also Figure 1-4 In an embodiment of the utility model, a driving circuit for an inverter power supply includes a control chip for sending a driving signal, the output end of the control chip is connected to an enabling circuit, the output end of the enabling circuit is connected to an anti-straight-through logic circuit, the output end of the anti-straight-through logic circuit is connected to an isolation driving circuit, and the driving signal sent by the control chip is output after passing through the enabling circuit, the anti-straight-through logic circuit, and the isolation driving circuit and is used to drive a power switch tube.

[0024] The control chip is an MCU control chip, which is used to send complementary PWM signals PMW1 and PWM2.

[0025] The enabling circuit includes AND gate circuits IC1A and IC1B for receiving driving signals PMW1 and PWM2 of the control chip, and an input enabling signal EN. The AND gate circuit IC1A outputs a PWM1 EN signal after receiving the driving signal PWM1 and the enabling signal EN, and the AND gate circuit IC1B outputs a PWM2 EN signal after receiving the driving signal PWM2 and the enabling signal EN. The driving signals PMW1 and PWM2 respectively pass through resistors R1 and R2 and the enabling signal EN passing through resistor R7 and enter the AND gate circuit. In this embodiment, the enabling signal is powered on for a period of time, and the MCU control chip is stable, enters the normal program, and after the whole machine self-check is completed, a high level is input again, so that the PWM signal can be output normally. When an abnormal situation occurs in the whole machine, the enabling signal is immediately changed to a low level, and the PWM signal is blocked in hardware to protect the whole machine.

[0026] The anti-shoot-through logic circuit includes NOT gate circuits IC2C and IC2D and AND gate circuits IC1C and IC1D; the PWM1 EN signal passes through the NOT gate circuit IC2C and is input into the AND gate circuit IC1C with the PWM2 EN signal, passes through the gate circuit IC1C and outputs the PWM2 LDRV signal to the isolation drive circuit; the PWM2 EN signal passes through the NOT gate circuit IC2D and is input into the AND gate circuit ICID with the PWM1 EN signal, passes through the AND gate circuit IC1D and outputs the PWM1 LDRV signal to the isolation drive circuit. In this embodiment, the NOT gate circuit is SN74HC14DR and the AND gate circuit is U74AHCT08G.

[0027] The isolation drive circuit includes an amplifier Q3 connected to the PWM1 LEDRV signal, and an isolation optocoupler U1 connected to the output end of the amplifier Q3. The output end of the isolation optocoupler U1 is connected to the driving power switch tube. The isolation drive circuit includes an amplifier Q4 connected to the PWM2LDRV signal, and an isolation optocoupler U2 connected to the output end of the amplifier Q4. The output end of the isolation optocoupler U2 is connected to the driving power switch. After the drive signal is amplified by amplifiers Q3 and Q4, it drives the isolation optocouplers U1 and U2, the core components of this circuit. As shown in the figure above, the isolation optocoupler further amplifies the power and isolates it to give a +15V level and -10V level to drive the power switch tube. The power switch tube outputs the PWM level, which is output after passing through the filter circuit composed of inductors L1 and C2.

[0028] During use of this embodiment, the MCU control chip sends out complementary PWM signals PMW1 and PWM2, and the AND gate circuits IC1A and IC1B of the enable circuit receive the complementary PMW1 and PWM2 and the enable signal EN sent by the MCU control chip. The AND gate circuit IC1A receives the drive signal PWM1 and the enable signal EN and then outputs the PWM1 EN signal. The AND gate circuit IC1B receives the drive signal PWM2 and the enable signal EN and then outputs the PWM2 EN signal. The drive signals PMW1 and PWM2 pass through the resistors R1 and R2 respectively and enter the AND gate circuit with the enable signal EN passing through the resistor R7. The PWM1 EN signal passes through the NOT gate circuit IC2C and then inputs into the AND gate circuit IC1C with the PWM2 EN signal. After passing through the gate circuit IC1C, the PWM2 LDRV signal is output to the isolation drive circuit. The PWM2 EN signal passes through the NOT gate circuit IC2D and then inputs into the AND gate circuit ICID with the PWM1 EN signal. After passing through the AND gate circuit IC1D, the PWM1 LDRV signal is output to the isolation drive circuit. The LEDRV signal passes through the amplifier Q3 and the isolation optocoupler U1, and the output end of the isolation optocoupler U1 is connected to the driving power switch tube. The PWM2 LDRV signal passes through the amplifier Q4 and the isolation optocoupler U2, and the output end of the isolation optocoupler U2 is connected to the driving power switch. After the drive signal is amplified by amplifiers Q3 and Q4, it drives the isolation optocouplers U1 and U2, the core components of this circuit. As shown in the figure above, the isolation optocoupler further amplifies the power and isolates it, giving a +15V level and -10V level to drive the power switch tube. The power switch tube outputs the PWM level, which is output after passing through the filter circuit composed of inductors L1 and C2.

[0029] During the operation of the whole machine, the switch tubes are complementary and turned on, and the complementary signals can be transmitted to the switch tubes quickly and safely. The switch tubes are orderly and complementary and turned on, and the power conversion is safe and reliable. When the MCU is disturbed by external factors, or resets or restarts due to abnormal conditions such as overheating, the two PWM signals may output high levels at the same time. In this case, the anti-straight-through logic circuit will turn off the two switch tubes, so that both output switch tubes are turned off, effectively preventing the straight-through situation, and the system is safer and more reliable.

[0030] Example 2

[0031] See also Figure 5 In the embodiment of the utility model, the power supply model of the enabling circuit is composed of a MC74LVXC3245 chip. After the PWM signal passes through the chip, the high and low levels are converted from 3.3V to 5V levels, realizing the level conversion while enabling. The rest of the circuits and usage process are the same as those in Example 1.

[0032] It is obvious to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential features of the present invention. Therefore, the embodiments should be regarded as exemplary and non-restrictive from any point of view, and the scope of the present invention is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims be included in the present invention. Any reference numeral in a claim should not be regarded as limiting the claim to which it relates.

[0033] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A drive circuit for an inverter power supply, characterized in that: It includes a control chip for sending a driving signal, the output end of the control chip is connected to an enabling circuit, the output end of the enabling circuit is connected to an anti-straight-through logic circuit, the output end of the anti-straight-through logic circuit is connected to an isolation driving circuit, and the driving signal sent by the control chip is output after passing through the enabling circuit, the anti-straight-through logic circuit, and the isolation driving circuit and is used to drive a power switch tube.

2. A drive circuit for an inverter power supply according to claim 1, characterized in that: The control chip is an MCU control chip, which is used to send complementary PWM signals PMW1 and PWM2.

3. A drive circuit for an inverter power supply according to claim 2, characterized in that: The enabling circuit includes AND gate circuits IC1A and IC1B for receiving control chip drive signals PMW1 and PWM2, and an input enable signal EN. The AND gate circuit IC1A outputs a PWM1 EN signal after receiving the drive signal PWM1 and the enable signal EN, and the AND gate circuit IC1B outputs a PWM2 EN signal after receiving the drive signal PWM2 and the enable signal EN.

4. A drive circuit for an inverter power supply according to claim 2, characterized in that: The enabling circuit adopts the MC74LVXC3245 chip, and the PWM signal is converted from a low level to a high level after passing through the enabling circuit.

5. A drive circuit for an inverter power supply according to claim 3, characterized in that: The anti-straight-through logic circuit includes NOT gate circuits IC2C and IC2D and AND gate circuits IC1C and IC1D; the PWM1 EN signal passes through the NOT gate circuit IC2C and is input into the AND gate circuit IC1C with the PWM2 EN signal, passes through the gate circuit IC1C and outputs the PWM2 LDRV signal to the isolation drive circuit; the PWM2 EN signal passes through the NOT gate circuit IC2D and is input into the AND gate circuit ICID with the PWM1 EN signal, passes through the AND gate circuit IC1D and outputs the PWM1 LDRV signal to the isolation drive circuit.

6. A drive circuit for an inverter power supply according to claim 5, characterized in that: The isolation driving circuit includes an amplifier Q3 connected to the PWM1 LEDRV signal, and an isolation optocoupler U1 connected to the output end of the amplifier Q3, and the output end of the isolation optocoupler U1 is connected to the driving power switch.

7. A drive circuit for an inverter power supply according to claim 5, characterized in that: The isolation driving circuit includes an amplifier Q4 connected to the PWM2 LEDRV signal, and an isolation optocoupler U2 connected to the output end of the amplifier Q4, and the output end of the isolation optocoupler U2 is connected to the driving power switch.

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