Frequency detection circuit and image sensor

Abstract

The utility model provides a frequency detection circuit and an image sensor, and the circuit comprises a frequency conversion module which receives a clock signal, and converts the clock frequency of the clock signal into an analog electric signal, so as to carry out the detection of the clock frequency; wherein the frequency conversion module comprises a resistance acquisition unit, and the resistance acquisition unit receives a clock signal and converts the clock frequency of the clock signal into a clock resistance signal so as to acquire an analog electric signal. According to the frequency detection circuit and the image sensor provided by the utility model, the problem that an additional crystal oscillator is needed to provide reference time in the existing frequency detection scheme is solved.

Description

Technical Field

[0001] The utility model relates to the technical field of image sensors, in particular to a frequency detection circuit and an image sensor. Background Art

[0002] In CMOS image sensors, the clock signal is an indispensable and important component, but the abnormality of the clock frequency will have a serious impact on the working state of the image sensor; therefore, in image sensors with higher security and stability, it is necessary to integrate a clock frequency detection circuit. The traditional approach is to connect the clock signal to be detected as input to a counter, and count the count results of the counter within a fixed time as output. The faster the clock frequency, the more the counter counts; however, the generation of the fixed time of the counter requires an additional crystal oscillator to provide, resulting in high circuit design overhead. Based on this, providing a frequency detection circuit that does not rely on an additional crystal oscillator is a technical problem that technicians in this field are eager to solve.

[0003] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the utility model and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology section of the utility model. Utility Model Content

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a frequency detection circuit and an image sensor, which are used to solve the problem that the existing frequency detection solution requires an additional crystal oscillator to provide a reference time.

[0005] In order to achieve the above-mentioned object and other related objects, the utility model provides a frequency detection circuit, the frequency detection circuit comprising:

[0006] A frequency conversion module receives a clock signal and converts the clock frequency of the clock signal into an analog electrical signal for clock frequency detection; wherein the frequency conversion module includes a resistance acquisition unit, which receives the clock signal and converts the clock frequency of the clock signal into a clock resistance signal to obtain the analog electrical signal.

[0007] Optionally, the resistance acquisition unit includes a first transmission gate, a second transmission gate, a first MOS transistor, a second MOS transistor, a first capacitor and a second capacitor, the input end of the first transmission gate is connected to the input end of the second transmission gate and serves as an access end of the resistance acquisition unit, the output end of the first transmission gate is connected to the first end of the first MOS transistor and is connected to a reference ground via the first capacitor, the first control end of the first transmission gate is connected to the control end of the second MOS transistor and receives the clock signal, the second control end of the first transmission gate receives an inverted signal of the clock signal, the output end of the second transmission gate is connected to the first end of the second MOS transistor and is connected to the reference ground via the second capacitor, the first control end of the second transmission gate receives the inverted signal of the clock signal, the second control end of the second transmission gate is connected to the control end of the first MOS transistor and receives the clock signal, and the second ends of the first MOS transistor and the second MOS transistor are connected to the reference ground.

[0008] Optionally, the frequency conversion module includes:

[0009] A voltage amplifying unit, connected to the access end of the resistance acquiring unit, receives a first voltage signal, and amplifies the first voltage signal to obtain a second voltage signal;

[0010] a current generating unit connected to the voltage amplifying unit, generating a clock current signal based on the second voltage signal and the clock resistance signal and outputting the clock current signal as the analog electrical signal;

[0011] Alternatively, the frequency conversion module further includes: a Miller compensation unit connected between the resistance acquisition unit and the voltage amplification unit.

[0012] Optionally, the voltage amplification unit includes a first operational amplifier, a third MOS tube and a fourth MOS tube, the first input end of the first operational amplifier is connected to a first voltage signal, the second input end of the first operational amplifier is connected to an access end of the resistance acquisition unit, the output end of the first operational amplifier is connected to a control end of the third MOS tube and connected to an access end of the resistance acquisition unit, the first end of the third MOS tube is connected to a second end of the fourth MOS tube, the second end of the third MOS tube is connected to a power supply voltage signal, the control end of the fourth MOS tube is connected to a first bias signal, and the first end of the fourth MOS tube is connected to an access end of the resistance acquisition unit; wherein, when the frequency conversion module further includes a Miller compensation unit, the output end of the first operational amplifier is connected to the access end of the resistance acquisition unit via the Miller compensation unit;

[0013] The current generating unit includes a fifth MOS tube and a sixth MOS tube, the control end of the fifth MOS tube is connected to the output end of the first operational amplifier, the first end of the fifth MOS tube is connected to the second end of the sixth MOS tube, the second end of the fifth MOS tube is connected to the power supply voltage signal, the control end of the sixth MOS tube is connected to the first bias signal, and the first end of the sixth MOS tube serves as the output end of the current generating unit.

[0014] Optionally, the frequency conversion module further includes:

[0015] The voltage generating unit is connected to the current generating unit and is used to convert the clock current signal into a clock voltage signal and replace the clock current signal as the analog electrical signal output.

[0016] Optionally, the voltage generating unit is implemented by a first resistor.

[0017] Optionally, the first resistor and the resistance acquisition unit are interchanged, wherein the current generating unit generates a fixed current signal based on the second voltage signal and the first resistance signal, and generates the clock voltage signal through the resistance acquisition unit.

[0018] Optionally, the frequency detection circuit further includes:

[0019] The signal quantization module is connected to the frequency conversion module and quantizes the analog electrical signal into a digital signal without using an additional clock signal.

[0020] Optionally, when the analog electrical signal includes a clock current signal, the signal quantization module includes:

[0021] a charge-discharge unit connected to the frequency conversion module, performing a charging operation based on a difference between a first current signal and a second current signal within a first time and performing a discharging operation based on the second current signal within a second time to obtain a capacitor voltage signal, wherein the second current signal is a sum of the clock current signal and the third current signal;

[0022] A comparison output unit is connected to the charge and discharge unit, and obtains an output signal by comparing the capacitor voltage signal with a reference voltage signal, so as to quantize the clock current signal based on the duty cycle of the output signal.

[0023] Optionally, the charging and discharging unit includes:

[0024] A first current part, used to generate the first current signal to perform a charging operation;

[0025] A clock current part, connected to the frequency conversion module, for transmitting the clock current signal for discharging operation;

[0026] A third current part, used for generating the third current signal to perform a discharge operation;

[0027] The charge and discharge control part is respectively connected to the first current part, the clock current part and the third current part, and is used to simultaneously start the charging operation and the discharging operation within a first time under the control of the output signal, and to close the charging operation and continue the discharging operation within a second time.

[0028] Optionally, the first current part includes a seventh MOS tube and an eighth MOS tube, the control end of the seventh MOS tube is connected to the first control voltage signal, the first end of the seventh MOS tube is connected to the second end of the eighth MOS tube, the second end of the seventh MOS tube is connected to the power supply voltage signal, the control end of the eighth MOS tube is connected to the first bias signal, and the first end of the eighth MOS tube serves as the current supply end of the first current part;

[0029] And / or, the clock current part includes a ninth MOS tube, a tenth MOS tube, an eleventh MOS tube and a twelfth MOS tube, the control end of the ninth MOS tube is connected to the control end of the tenth MOS tube and connected to the second bias signal, the first end of the ninth MOS tube is connected to the output end of the frequency conversion module, the second end of the ninth MOS tube is connected to the first end of the eleventh MOS tube, the first end of the tenth MOS tube serves as the current supply end of the clock current part, the second end of the tenth MOS tube is connected to the first end of the twelfth MOS tube, the control end of the eleventh MOS tube is connected to the control end of the twelfth MOS tube and connected to the first end of the ninth MOS tube, and the second ends of the eleventh MOS tube and the twelfth MOS tube are connected to the reference ground;

[0030] And / or, the third current part includes a thirteenth MOS tube and a fourteenth MOS tube, the control end of the thirteenth MOS tube is connected to the second bias signal, the first end of the thirteenth MOS tube serves as the current supply end of the third current part, the second end of the thirteenth MOS tube is connected to the first end of the fourteenth MOS tube, the control end of the fourteenth MOS tube is connected to the second control voltage signal, and the second end of the fourteenth MOS tube is connected to the reference ground;

[0031] And / or, the charge and discharge control part includes a fifteenth MOS tube, a sixteenth MOS tube, a seventeenth MOS tube and a third capacitor, the control end of the fifteenth MOS tube is connected to the output signal, the first end of the fifteenth MOS tube is connected to the first end of the sixteenth MOS tube, the second end of the fifteenth MOS tube is connected to the second end of the seventeenth MOS tube and connected to the current supply end of the first current part, the control end of the sixteenth MOS tube is connected to its first end, the second end of the sixteenth MOS tube is connected to the reference ground, the control end of the seventeenth MOS tube is connected to the inverted signal of the output signal, the first end of the seventeenth MOS tube is connected to the first end of the third capacitor and connected to the clock current part and the current supply end of the third current part, the first end of the third capacitor serves as the output end of the charge and discharge unit, and the second end of the third capacitor is connected to the reference ground.

[0032] Optionally, the charge and discharge unit further includes a voltage control providing part, which is used to provide a first voltage control signal to the first current part and a second voltage control signal to the third current part.

[0033] Optionally, the voltage control providing part includes a second operational amplifier, an eighteenth MOS tube, a nineteenth MOS tube, a twentieth MOS tube, a twenty-first MOS tube, a twenty-second MOS tube, a twenty-third MOS tube and a second resistor, the first input end of the second operational amplifier is connected to the third voltage signal, the second input end of the second operational amplifier is connected to the first end of the second resistor, the output end of the second operational amplifier is connected to the control end of the eighteenth MOS tube and the nineteenth MOS tube, the output end of the second operational amplifier is also connected to the first end of the second resistor and serves as the first output end of the voltage control providing part, the first end of the eighteenth MOS tube is connected to the second end of the twentieth MOS tube, the second end of the eighteenth MOS tube is connected to the power supply voltage signal, the first end of the nineteenth MOS tube is connected to the twenty-first MO The second end of the 19th MOS tube is connected to the power supply voltage signal, the control end of the 20th MOS tube is connected to the control end of the 21st MOS tube and connected to the first bias signal, the first end of the 20th MOS tube is connected to the first end of the second resistor, the first end of the 21st MOS tube is connected to the first end of the 22nd MOS tube and the control end of the 23rd MOS tube and serves as the second output end of the control voltage providing part, the control end of the 22nd MOS tube is connected to the second bias signal, the second end of the 22nd MOS tube is connected to the first end of the 23rd MOS tube, and the second ends of the 23rd MOS tube and the second resistor are connected to the reference ground; or, the control voltage providing part also includes a Miller capacitor connected between the output end of the second operational amplifier and the first end of the second resistor.

[0034] Optionally, the comparison output unit includes a comparator, an inverter and a D flip-flop, the first input end of the comparator is connected to a reference voltage signal, the second input end of the comparator is connected to the output end of the charge and discharge unit, the output end of the comparator is connected to the input end of the inverter, the output end of the inverter is connected to the data end of the D flip-flop, the clock end of the D flip-flop is connected to the clock signal, and the output end of the D flip-flop serves as the output end of the comparison output unit.

[0035] Optionally, when a clock voltage signal is used to replace a clock current signal as the analog electrical signal, the signal quantization module further includes: an input conversion unit connected between the frequency conversion module and the charge and discharge unit, for converting the clock voltage signal into the clock current signal.

[0036] Optionally, the input conversion unit includes:

[0037] an amplifier part, connected to the frequency conversion module, and configured to amplify the clock voltage signal to obtain a fourth voltage signal;

[0038] a voltage-current conversion part, connected to the amplifier part, for converting the fourth voltage signal into the clock current signal;

[0039] Alternatively, the input conversion unit further includes a Miller compensation part connected between the amplifier part and the voltage-current conversion part.

[0040] Optionally, the amplifier part includes a two-stage operational amplifier connected in a unit gain negative feedback; and / or, the voltage-current conversion part includes a twenty-fourth MOS tube, a twenty-fifth MOS tube, a twenty-sixth MOS tube, a twenty-seventh MOS tube and a third resistor, the control end of the twenty-fourth MOS tube is connected to the control end of the twenty-fifth MOS tube and connected to the fourth voltage signal, the first end of the twenty-fourth MOS tube is connected to the second end of the twenty-sixth MOS tube, the second end of the twenty-fourth MOS tube is connected to the power supply voltage signal, the first end of the twenty-fifth MOS tube is connected to the second end of the twenty-seventh MOS tube, the second end of the twenty-fifth MOS tube is connected to the power supply voltage signal, the control end of the twenty-sixth MOS tube is connected to the control end of the twenty-seventh MOS tube and connected to the first bias signal, the first end of the twenty-sixth MOS tube is connected to the first end of the third resistor, the first end of the twenty-seventh MOS tube serves as the output end of the input conversion unit, the first end of the third resistor is connected to the output end of the amplifier part, and the second end of the third resistor is connected to the reference ground; wherein, when the input conversion unit includes a Miller compensation part, the first end of the third resistor is connected to the output end of the amplifier part via the Miller compensation part.

[0041] Optionally, the signal quantization module is implemented by a flash memory analog-to-digital converter, a successive approximation analog-to-digital converter, or a pipeline analog-to-digital converter.

[0042] The utility model also provides an image sensor, comprising the frequency detection circuit as described in any one of the above solutions.

[0043] As described above, the frequency detection circuit and image sensor of the present invention convert the clock frequency of the clock signal into a current signal or a voltage signal in the analog domain and then quantize it. No additional crystal oscillator is required to provide the main frequency, which saves chip area, facilitates circuit integration, and reduces design overhead. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 Shown is a structural schematic diagram of the frequency detection circuit of the utility model.

[0045] Figure 2 Shown is a circuit diagram of the frequency conversion module of the utility model.

[0046] Figure 3 Shown is a circuit diagram of the resistance acquisition unit of the utility model.

[0047] Figure 4 Shown is another circuit schematic diagram of the frequency conversion module of the present invention.

[0048] Figure 5 Shown is another circuit diagram of the frequency conversion module of the utility model.

[0049] Figure 6 Shown is a circuit schematic diagram of the signal quantization module of the utility model.

[0050] Figure 7 Shown is a circuit diagram of the voltage control providing part of the utility model.

[0051] Figure 8 Shown is another circuit schematic diagram of the signal quantization module of the utility model.

[0052] Fig. 9 Shown is another circuit schematic diagram of the signal quantization module of the utility model.

[0053] Component number description

[0054] 10 Frequency detection circuit

[0055] 100 Frequency conversion module

[0056] 110 resistance acquisition unit

[0057] 120 Voltage amplifier unit

[0058] 130 Current generating unit

[0059] 140 Miller compensation unit

[0060] 150 Voltage generation unit

[0061] 200 Signal Quantization Module

[0062] 210 charging and discharging unit

[0063] 211 First Current Section

[0064] 212 Clock Current Section

[0065] 213 Third Current Section

[0066] 214 Charge and discharge control part

[0067] 215 Pressure control supply part

[0068] 220 Comparison output unit

[0069] 230 Input conversion unit

[0070] 231 Amplifier Section

[0071] 232 Voltage-current conversion section

[0072] 233 Miller compensation part

[0073] 240 resistor string

[0074] 250 Comparator Array

[0075] 260 Decoder DETAILED DESCRIPTION

[0076] The following is an explanation of the implementation of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific implementations, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0077] See also Figures 1 to 9 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the utility model in a schematic manner, and the illustrations only show the components related to the utility model rather than the number, shape and size of the components in actual implementation. The form, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.

[0078] like Figure 1 As shown, this embodiment provides a frequency detection circuit 10 , including a frequency conversion module 100 , and further including a signal quantization module 200 .

[0079] The frequency conversion module 100 receives the clock signal clk and converts the clock frequency fclk of the clock signal into an analog electrical signal for clock frequency detection; wherein the analog electrical signal includes a current signal or a voltage signal, but whether it is a current signal or a voltage signal, it is related to the clock frequency, therefore, the above current signal is recorded as a clock current signal, and the above voltage signal is recorded as a clock voltage signal to avoid confusion with other current signals or other voltage signals in the following text.

[0080] For the case where the analog electrical signal includes a clock current signal:

[0081] In one embodiment, if Figure 2 As shown, the frequency conversion module 100 includes a resistance acquisition unit 110 , further includes a voltage amplification unit 120 and a current generation unit 130 , and further includes a Miller compensation unit 140 .

[0082] The resistance acquisition unit 110 receives the clock signal clk and converts the clock frequency fclk of the clock signal into a clock resistance signal Rclk to obtain a clock current signal (ie, an analog electrical signal). Figure 3 As shown, the resistance acquisition unit 110 includes a first transmission gate TG1, a second transmission gate TG2, a first MOS transistor M1, a second MOS transistor M2, a first capacitor C1 and a second capacitor C2, wherein the input end of the first transmission gate TG1 is connected to the input end of the second transmission gate TG2 and serves as the access end of the resistance acquisition unit 110, the output end of the first transmission gate TG1 is connected to the first end of the first MOS transistor M1 and is connected to the reference ground via the first capacitor C1, the first control end of the first transmission gate TG1 is connected to the control end of the second MOS transistor M2 and receives the clock signal clk, the second control end of the first transmission gate TG1 receives the inverted signal clkb of the clock signal, the output end of the second transmission gate TG2 is connected to the first end of the second MOS transistor M2 and is connected to the reference ground via the second capacitor C2, the first control end of the second transmission gate TG2 receives the inverted signal clkb of the clock signal, the second control end of the second transmission gate TG2 is connected to the control end of the first MOS transistor M1 and receives the clock signal clk, and the second ends of the first MOS transistor M1 and the second MOS transistor M2 are connected to the reference ground; according to the number of charge transfers per unit time, it can be obtained that the clock resistance signal satisfies Formula 3: Wherein, Rclk is the value of the clock resistance signal, fclk is the clock frequency of the clock signal, C1 is the value of the first capacitor, and C2 is the value of the second capacitor.

[0083] The voltage amplifying unit 120 is connected to the access end of the resistance acquisition unit 110, receives the first voltage signal V1 and amplifies the first voltage signal V1 to obtain the second voltage signal V2. Figure 2 As shown, the voltage amplification unit 120 includes a first operational amplifier AMP1, a third MOS tube M3 and a fourth MOS tube M4, wherein the first input end of the first operational amplifier AMP1 is connected to the first voltage signal V1, the second input end of the first operational amplifier AMP1 is connected to the access end of the resistance acquisition unit 110, the output end of the first operational amplifier AMP1 is connected to the control end of the third MOS tube M3 and the access end of the resistance acquisition unit 110, the first end of the third MOS tube M3 is connected to the second end of the fourth MOS tube M4, the second end of the third MOS tube M3 is connected to the power supply voltage signal AVDD, the control end of the fourth MOS tube M4 is connected to the first bias signal Vb1, and the first end of the fourth MOS tube M4 is connected to the access end of the resistance acquisition unit 110. In the above example, the first operational amplifier AMP1 is a two-stage operational amplifier connected to unit gain negative feedback. Wherein, the closed-loop system gain of the two-stage operational amplifier satisfies Formula 1: V2 is the value of the second voltage signal, V1 is the value of the first voltage signal, A0 is the gain of the two-stage operational amplifier, and β is the feedback coefficient; since the voltage at the output end is completely fed back to the input end, β is 1, and since the gain A0 of the two-stage operational amplifier is very large, Formula 2 can be approximated: In practical applications, in order to obtain a precise voltage signal, a reference voltage signal provided by a bandgap reference circuit may be used as the first voltage signal V1.

[0084] The current generating unit 130 is connected to the voltage amplifying unit 120, and generates a clock current signal Iclk based on the second voltage signal V2 and the clock resistance signal Rclk and outputs it as an analog electrical signal. Figure 2As shown, the current generating unit 130 includes a fifth MOS transistor M5 and a sixth MOS transistor M6, wherein the control end of the fifth MOS transistor M5 is connected to the output end of the first operational amplifier AMP1, the first end of the fifth MOS transistor M5 is connected to the second end of the sixth MOS transistor M6, the second end of the fifth MOS transistor M5 is connected to the power supply voltage signal AVDD, the control end of the sixth MOS transistor M6 is connected to the first bias signal Vb1, and the first end of the sixth MOS transistor M6 serves as the output end of the current generating unit 130. In the above example, the fifth MOS tube M5 and the sixth MOS tube M6 form a common-source common-gate current mirror with the third MOS tube M3 and the fourth MOS tube M4 in the voltage amplification unit 120 to obtain high mirroring accuracy. Of course, it is also feasible to use other structure current mirrors. For example, the common-gate tube is removed and only the common-source tube is retained, sacrificing accuracy in exchange for saving area overhead; wherein the width-to-length ratio of the third MOS tube M3 is consistent with the width-to-length ratio of the fifth MOS tube M5, therefore, the current mirror ratio of the common-source common-gate current mirror is 1:1, that is, the output clock current signal is equal to the current flowing through the resistor acquisition unit 110, and according to Ohm's theorem, Formula 4 is obtained: Iclk is the value of the clock current signal, IRclk is the value of the current flowing through the resistor acquisition unit 110, and Formula 5 can be obtained by combining Formula 2 and Formula 3: In this way, the conversion from frequency to current is completed. It can be seen from the above formula that the clock current signal Iclk is in direct proportion to the clock frequency fclk of the clock signal.

[0085] The Miller compensation unit 140 is connected between the resistance acquisition unit 110 and the voltage amplification unit 120, and is used to compensate for the frequency characteristics of the first operational amplifier AMP1 in the voltage amplification unit 120; at this time, the output end of the first operational amplifier AMP1 in the voltage amplification unit 120 is connected to the access end of the resistance acquisition unit 110 via the Miller compensation unit 140. In one example, the Miller compensation unit 140 includes a Miller capacitor (not shown in the figure), and of course, in other examples, the Miller compensation unit 140 also includes a compensation resistor (not shown in the figure), and at this time, the Miller capacitor and the compensation resistor are connected in series between the resistance acquisition unit 110 and the voltage amplification unit 120.

[0086] For the case where the analog electrical signal includes a clock voltage signal:

[0087] In one embodiment, if Figure 4 As shown, the frequency conversion module 100 includes a voltage generating unit 150 in addition to the various units described above.

[0088] The voltage generating unit 150 is connected to the current generating unit 130, and is used to convert the clock current signal Iclk into a clock voltage signal Vclk, and use the clock voltage signal Vclk to replace the clock current signal Iclk as an analog electrical signal output. Figure 4 As shown, the voltage generating unit 150 is implemented by a first resistor R1. For example, a first end of the first resistor R1 is connected to the output end of the current generating unit 130 and serves as the output end of the voltage generating unit 150, and a second end of the first resistor R1 is connected to the reference ground. The clock current signal Iclk is converted into a clock voltage signal Vclk through the first resistor R1, satisfying Formula 6: Vclk=Iclk·R1=V1·R1·fclk·(C1+C2), Vclk is the value of the clock voltage signal, and R1 is the value of the first resistor. In this way, the frequency-to-voltage conversion is completed. It can be seen from the above formula that the clock voltage signal Vclk is in direct proportion to the clock frequency fclk of the clock signal.

[0089] In another embodiment, if Figure 5 As shown, the first resistor R1 and the resistor acquisition unit 110 are swapped. At this time, the current generating unit 130 generates a fixed current signal based on the second voltage signal V2 and the first resistance signal, and generates a clock voltage signal Vclk through the resistor acquisition unit 110; wherein the clock voltage signal Vclk satisfies Formula 7: In this way, the conversion from frequency to voltage is completed. It can be seen from the above formula that the clock voltage signal Vclk is inversely proportional to the clock frequency fclk of the clock signal.

[0090] The signal quantization module 200 is connected to the frequency conversion module 100 and quantizes the analog electrical signal into a digital signal without using an additional clock signal.

[0091] For the case where the analog electrical signal includes a clock current signal:

[0092] In one embodiment, if Figure 6 As shown, the signal quantization module 200 includes a charge and discharge unit 210 and a comparison and output unit 220 .

[0093] The charge and discharge unit 210 is connected to the frequency conversion module 100, and performs a charging operation based on the difference between the first current signal I1 and the second current signal I2 within the first time T1, and performs a discharging operation based on the second current signal I2 within the second time T2 to obtain a capacitor voltage signal Vcap, wherein the second current signal I2 is the sum of the clock current signal Iclk and the third current signal I3. In one example, Figure 6 and Figure 7As shown, the charge and discharge unit 210 includes a first current part 211 , a clock current part 212 , a third current part 213 and a charge and discharge control part 214 , and further includes a control voltage providing part 215 .

[0094] The first current part 211 is used to generate a first current signal I1 for charging operation. Figure 6 As shown, the first current part 211 includes a seventh MOS transistor M7 and an eighth MOS transistor M8, wherein the control end of the seventh MOS transistor M7 is connected to the first control voltage signal Vc1, the first end of the seventh MOS transistor M7 is connected to the second end of the eighth MOS transistor M8, the second end of the seventh MOS transistor M7 is connected to the power supply voltage signal AVDD, the control end of the eighth MOS transistor M8 is connected to the first bias signal Vb1, and the first end of the eighth MOS transistor M8 serves as the current supply end of the first current part 211.

[0095] The clock current part 212 is connected to the frequency conversion module 100 and is used to transmit the clock current signal Iclk for the discharge operation. Figure 6 As shown, the clock current part 212 includes a ninth MOS transistor M9, a tenth MOS transistor M10, an eleventh MOS transistor M11 and a twelfth MOS transistor M12, wherein the control end of the ninth MOS transistor M9 is connected to the control end of the tenth MOS transistor M10 and is connected to the second bias signal Vb2, the first end of the ninth MOS transistor M9 is connected to the output end of the frequency conversion module 100, the second end of the ninth MOS transistor M9 is connected to the first end of the eleventh MOS transistor M11, the first end of the tenth MOS transistor M10 serves as a current supply end of the clock current part 212, the second end of the tenth MOS transistor M10 is connected to the first end of the twelfth MOS transistor M12, the control end of the eleventh MOS transistor M11 is connected to the control end of the twelfth MOS transistor M12 and is connected to the first end of the ninth MOS transistor M9, and the second ends of the eleventh MOS transistor M11 and the twelfth MOS transistor M12 are connected to the reference ground.

[0096] The third current portion 213 is used to generate a third current signal I3 for performing a discharge operation. Figure 6 As shown, the third current part 213 includes a thirteenth MOS transistor M13 and a fourteenth MOS transistor M14, wherein the control end of the thirteenth MOS transistor M13 is connected to the second bias signal Vb2, the first end of the thirteenth MOS transistor M13 serves as the current supply end of the third current part 213, the second end of the thirteenth MOS transistor M13 is connected to the first end of the fourteenth MOS transistor M14, the control end of the fourteenth MOS transistor M14 is connected to the second control voltage signal Vc2, and the second end of the fourteenth MOS transistor M14 is connected to the reference ground.

[0097] The charge and discharge control part 214 is connected to the first current part 211, the clock current part 212 and the third current part 213 respectively, and is used to start the charging operation and the discharging operation at the same time within the first time T1 under the control of the output signal OUT to perform the charging operation based on the difference between the first current signal I1 and the second current signal I2, and to close the charging operation and continue the discharging operation within the second time T2 to perform the discharging operation based on the second current signal I2. Specifically, Figure 6 As shown, the charge and discharge control part 214 includes a fifteenth MOS transistor M15, a sixteenth MOS transistor M16, a seventeenth MOS transistor M17 and a third capacitor C3, wherein the control end of the fifteenth MOS transistor M15 is connected to the output signal OUT, the first end of the fifteenth MOS transistor M15 is connected to the first end of the sixteenth MOS transistor M16, the second end of the fifteenth MOS transistor M15 is connected to the second end of the seventeenth MOS transistor M17 and connected to the current supply end of the first current part 211, the control end of the sixteenth MOS transistor M16 is connected to the first end thereof, the second end of the sixteenth MOS transistor M16 is connected to the reference ground, the control end of the seventeenth MOS transistor M17 is connected to the inverted signal OUTb of the output signal, the first end of the seventeenth MOS transistor M17 is connected to the first end of the third capacitor C3 and connected to the current supply ends of the clock current part 212 and the third current part 213, the first end of the third capacitor C3 serves as the output end of the charge and discharge unit 210, and the second end of the third capacitor C3 is connected to the reference ground.

[0098] The control voltage providing part 215 is used to provide a first control voltage signal Vc1 to the first current part 211 and a second control voltage signal Vc2 to the third current part 213. Specifically, Figure 7As shown, the control voltage providing part 215 includes a second operational amplifier AMP2, an eighteenth MOS tube M18, a nineteenth MOS tube M19, a twentieth MOS tube M20, a twenty-first MOS tube M21, a twenty-second MOS tube M22, a twenty-third MOS tube M23 and a second resistor R2, and further includes a Miller capacitor Cm, and even includes a compensation resistor (not shown in the figure); wherein, a first input end (for example, a negative input end) of the second operational amplifier AMP2 is connected to the third voltage signal V3, a second input end (for example, a positive input end) of the second operational amplifier AMP2 is connected to a first end of the second resistor R2, an output end of the second operational amplifier AMP2 is connected to the control ends of the eighteenth MOS tube M18 and the nineteenth MOS tube M19, an output end of the second operational amplifier AMP2 is also connected to a first end of the second resistor R2 and serves as a first output end of the control voltage providing part 215, a first end of the eighteenth MOS tube M18 is connected to a second end of the twentieth MOS tube M20, and a second end of the eighteenth MOS tube M18 is connected to a The power supply voltage signal AVDD is connected, the first end of the nineteenth MOS tube M19 is connected to the second end of the twenty-first MOS tube M21, the second end of the nineteenth MOS tube M19 is connected to the power supply voltage signal AVDD, the control end of the twentieth MOS tube M20 is connected to the control end of the twenty-first MOS tube M21 and connected to the first bias signal Vb1, the first end of the twentieth MOS tube M20 is connected to the first end of the second resistor R2, the first end of the twenty-first MOS tube M21 is connected to the first end of the twenty-second MOS tube M22 and the control end of the twenty-third MOS tube M23 and serves as the second output end of the control voltage providing part 215, the control end of the twenty-second MOS tube M22 is connected to the second bias signal Vb2, the second end of the twenty-second MOS tube M22 is connected to the first end of the twenty-third MOS tube M23, and the second ends of the twenty-third MOS tube M23 and the second resistor R2 are connected to the reference ground; the Miller capacitor Cm or the compensation resistor and the Miller capacitor Cm are connected in series between the output end of the second operational amplifier AMP2 and the first end of the second resistor R1. In practical applications, the second operational amplifier AMP2 is a two-stage operational amplifier connected to form a unity gain negative feedback. In addition, in order to obtain a precise voltage signal, a reference voltage signal provided by a bandgap reference circuit can be used as the third voltage signal V3.

[0099] The comparison output unit 220 is connected to the charge and discharge unit 210, and the output signal OUT is obtained by comparing the capacitor voltage signal Vcap and the reference voltage signal Vref, so as to realize the quantization of the clock current signal Iclk based on the duty cycle of the output signal OUT. In one example, the comparison output unit 220 includes a comparator CMP1, an inverter INV and a D flip-flop DFF, wherein the first input terminal (e.g., the negative input terminal) of the comparator CMP1 is connected to the reference voltage signal Vref, the second input terminal (e.g., the positive input terminal) of the comparator CMP1 is connected to the output terminal of the charge and discharge unit 210, the output terminal of the comparator CMP1 is connected to the input terminal of the inverter INV, the output terminal of the inverter INV is connected to the data terminal of the D flip-flop DFF, the clock terminal of the D flip-flop DFF is connected to the clock signal clk, and the output terminal of the D flip-flop DFF serves as the output terminal of the comparison output unit 220. It should be noted that the clock signal clk connected to the clock terminal of the D flip-flop DFF is the clock signal to be detected and does not need to be provided additionally.

[0100] In the signal quantization module 200 described in the above embodiment, the third voltage signal V3 of the voltage control providing part 215 satisfies Formula 8: Thus, the current flowing through the branch where the second resistor R2 is located satisfies Formula 9: Among them, V3' is the value of the node voltage of the first end of the second resistor R2, V3 is the value of the third voltage signal, IR2 is the value of the current flowing through the branch where the second resistor is located, and R2 is the value of the second resistor; in addition, the eighteenth MOS tube M18, the nineteenth MOS tube M19, the twentieth MOS tube M20 and the twenty-first MOS tube M21 constitute a common source and common gate current mirror, and the width-to-length ratio of the eighteenth MOS tube M18 is consistent with the width-to-length ratio of the nineteenth MOS tube M19, that is, the current mirror ratio of the common source and common gate current mirror is 1:1, therefore, the current flowing through the branch where the nineteenth MOS tube M19 is located is equal to the current flowing through the branch where the second resistor is located.

[0101] The seventh MOS transistor M7 and the eighth MOS transistor M8 in the first current part 211 and the eighteenth MOS transistor M18 and the twentieth MOS transistor M20 in the control voltage providing part 215 form a cascode current mirror. The width-to-length ratio of the seventh MOS transistor M7 and the width-to-length ratio of the eighteenth MOS transistor M18 satisfy M:1, that is, the current mirror ratio of the cascode current mirror is M:1. In this way, the first current signal I1 satisfies Formula 10: The ninth MOS tube M9, the tenth MOS tube M10, the eleventh MOS tube M11 and the twelfth MOS tube M12 in the clock current part 212 form a cascode current mirror, and the width-to-length ratio of the eleventh MOS tube M11 is consistent with the width-to-length ratio of the twelfth MOS tube M12, that is, the current mirror ratio of the cascode current mirror is 1:1, so that the transmission of the clock current signal Iclk can be achieved. The thirteenth MOS tube M13 and the fourteenth MOS tube M14 in the third current part 213 and the twenty-second MOS tube M22 and the twenty-third MOS tube M23 in the control voltage providing part 215 form a cascode current mirror, and the width-to-length ratio of the fourteenth MOS tube M14 and the width-to-length ratio of the twenty-third MOS tube M23 satisfy N:1, that is, the current mirror ratio of the cascode current mirror is N:1, so that the third current signal I3 satisfies Formula 11: The first current signal I1 is greater than the sum of the clock current signal Iclk and the third current signal I3 , that is, I1>Iclk+I3 , therefore, M>N.

[0102] The fifteenth MOS transistor M15 and the seventeenth MOS transistor M17 in the charge and discharge control part 214 are respectively controlled by the output signal and its inverted signal; within the first time T1, the output signal OUT is at a high level, the inverted signal OUTb of the output signal is at a low level, the fifteenth MOS transistor M15 is turned off and the seventeenth MOS transistor M17 is turned on, the third capacitor C3 is charged based on the first current signal I1, and the third capacitor C3 is discharged based on the second current signal (that is, the sum of the clock current signal Iclk and the third current signal I3). Since the charging current is greater than the discharging current, the capacitor voltage signal Vcap rises, that is, the voltage at the positive input terminal of the comparator CMP1 rises. When Vc When ap>Vref, the output of the comparator CMP1 flips to a high level, and the output of the D flip-flop DFF flips to a low level; within the second time T2, the output signal OUT is a low level, the inverted signal OUTb of the output signal is a high level, the fifteenth MOS tube M15 is turned on and the seventeenth MOS tube M17 is turned off, and the third capacitor C3 is discharged based on the second current signal (i.e., the sum of the clock current signal Iclk and the third current signal I3), and the capacitor voltage signal Vcap drops, that is, the voltage at the positive input end of the comparator CMP1 drops, and when Vcap<Vref, the output of the comparator CMP1 flips to a low level, and the output of the D flip-flop DFF flips to a high level. When the charge and discharge are balanced, there is Formula 12: Combining Formula 5, Formula 10 and Formula 11, we get Formula 13: When the first voltage signal V1 and the third voltage signal V3 are reference voltage signals, Formula 13 is simplified to Formula 14: Finally, the clock frequency fclk of the clock signal is converted into the duty cycle Duty of the output signal. The value of the clock frequency fclk can be calculated by combining known parameters. The entire detection process does not require an additional crystal oscillator to provide the main frequency. It can be seen from the above formula that the duty cycle Duty of the output signal is directly proportional to the clock frequency fclk of the clock signal.

[0103] For the case where the analog electrical signal includes a clock voltage signal:

[0104] In one embodiment, if Figure 8 As shown, the signal quantization module 200 includes an input conversion unit 230 in addition to the various units described above.

[0105] The input conversion unit 230 is connected between the frequency conversion module 100 and the charge-discharge unit 210, and is used to convert the clock voltage signal Vclk into a clock current signal Iclk. Figure 8 As shown, the input conversion unit 230 includes an amplifier part 231 and a voltage-current conversion part 232 , and further includes a Miller compensation part 233 .

[0106] The amplifier part 231 is connected to the frequency conversion module 100 and is used to amplify the clock voltage signal Vclk to obtain a fourth voltage signal V4. Figure 8 As shown, the amplifier part 231 includes a two-stage operational amplifier AMP3 connected to a unit gain negative feedback. For example, the negative input terminal of the two-stage operational amplifier AMP3 is connected to the clock voltage signal Vclk, and the positive input terminal of the two-stage operational amplifier AMP3 is connected to its output terminal and connected to the first end of the third resistor R3 in the voltage-to-current conversion part 232.

[0107] The voltage-current conversion part 232 is connected to the amplifier part 231 and is used to convert the fourth voltage signal V4 into a clock current signal Iclk. Specifically, the voltage-current conversion part 232 includes a twenty-fourth MOS transistor M24, a twenty-fifth MOS transistor M25, a twenty-sixth MOS transistor M26, a twenty-seventh MOS transistor M27 and a third resistor R3, wherein the control end of the twenty-fourth MOS transistor M24 is connected to the control end of the twenty-fifth MOS transistor M25 and is connected to the fourth voltage signal V4, the first end of the twenty-fourth MOS transistor M24 is connected to the second end of the twenty-sixth MOS transistor M26, the second end of the twenty-fourth MOS transistor M24 is connected to the power supply voltage signal AVDD, the first end of the twenty-fifth MOS transistor M25 is connected to the second end of the twenty-seventh MOS transistor M27, the second end of the twenty-fifth MOS transistor M25 is connected to the power supply voltage signal AVDD, the control end of the twenty-sixth MOS transistor M26 is connected to the control end of the twenty-seventh MOS transistor M27 and is connected to the first bias signal Vb1, the first end of the twenty-sixth MOS transistor M26 is connected to the first end of the third resistor R3, the first end of the twenty-seventh MOS transistor M27 serves as the output end of the input conversion unit 230, the first end of the third resistor R3 is connected to the output end of the amplifier part 231, and the second end of the third resistor R3 is connected to the reference ground.

[0108] Miller compensation part 233 is connected between amplifier part 231 and voltage-current conversion part 232, and is used to compensate for the frequency characteristics of amplifier part 231; at this time, the positive input end of the two-stage operational amplifier AMP3 in amplifier part 231 is no longer directly connected to its output end, but is connected to its output end via Miller compensation part 233, and the first end of the third resistor in voltage-current conversion part 232 is no longer directly connected to the output end of amplifier part 231, but is connected to the output end of amplifier part 231 via Miller compensation part 233. In one example, Miller compensation part 233 includes Miller capacitor (not shown in the figure), of course, in other examples, Miller compensation part 233 also includes compensation resistor (not shown in the figure), at this time, Miller capacitor and compensation resistor are connected in series between amplifier part 231 and voltage-current conversion part 232.

[0109] In the above implementation, the fourth voltage signal of the amplifier part 231 satisfies Formula 15: Wherein, V4 is the value of the fourth voltage signal; in the voltage-current conversion part 232, the twenty-fourth MOS tube M24, the twenty-fifth MOS tube M25, the twenty-sixth MOS tube M26 and the twenty-seventh MOS tube M27 constitute a common source and common gate current mirror, and the width-to-length ratio of the twenty-fourth MOS tube M24 is consistent with the width-to-length ratio of the twenty-fifth MOS tube M25, that is, the current mirror ratio of the common source and common gate current mirror is 1:1, therefore, the current flowing through the branch where the third resistor R3 is located is equal to the current flowing through the branch where the twenty-fifth MOS tube M25 is located, satisfying Formula 16: IR3 is the current flowing through the branch where the third resistor is located; then the clock current signal Iclk is quantized using the method described above. For the case of Vclk=V1·R1·fclk·(C1+C2), when the values ​​of the first resistor R1 and the third resistor R3 are designed to be equal and the first voltage signal V1 and the third voltage signal V3 are reference voltage signals, Formula 14 can be obtained. In the case where the values ​​of the first resistor R1, the second resistor R2 and the third resistor R3 are designed to be equal and the first voltage signal V1 and the third voltage signal V3 are reference voltage signals, Formula 17 is obtained: Finally, the clock frequency fclk of the clock signal clk is converted into the duty cycle Duty of the output signal. The value of the clock frequency fclk can be calculated by combining the known parameters. The entire detection process does not require an additional crystal oscillator to provide the main frequency. It can be seen from Formula 14 that the duty cycle Duty of the output signal is directly proportional to the clock frequency fclk of the clock signal. It can be seen from Formula 17 that the duty cycle Duty of the output signal is inversely proportional to the clock frequency fclk of the clock signal.

[0110] In another embodiment, the signal quantization module 200 is implemented using a flash analog-to-digital converter (Flash ADC), a successive approximation analog-to-digital converter (SAR ADC) or a pipelined analog-to-digital converter (pipelined ADC). The above analog-to-digital converters do not require an additional crystal oscillator to provide the main frequency. Of course, other analog-to-digital conversion structures that do not use an additional crystal oscillator are also applicable to this embodiment. Fig. 9 An n-bit flash memory analog-to-digital converter is shown, including a resistor string 240, a comparator array 250 and a decoder 260; the resistor string 240 includes 2n fourth resistors R4, which are connected in series between a reference voltage signal Vref and a reference ground, and divide the reference voltage signal Vref to obtain 2n-1 divided voltage signals; the comparator array 250 includes 2n-1 comparators CMP2, whose positive input terminals are correspondingly connected to the 2n-1 divided voltage signals, whose negative input terminals are all connected to the clock voltage signal Vclk, and whose output terminals are connected to the decoder 260; the decoder 260 converts the thermometer codes output by the 2n-1 comparators CMP2 into binary codes to realize the quantization of the clock voltage signal Vclk; wherein n is a natural number greater than 1.

[0111] In practical applications, the first MOS tube M1, the second MOS tube M2, the ninth MOS tube M9, the tenth MOS tube M10, the eleventh MOS tube M11, the twelfth MOS tube M12, the thirteenth MOS tube M13, the fourteenth MOS tube M14, the sixteenth MOS tube M16, the twenty-second MOS tube M22 and the twenty-third MOS tube M23 mentioned above are NMOS tubes, and the third MOS tube M3, the fourth MOS tube M4, the fifth MOS tube M5, the sixth MOS tube M6, the seventh MOS tube M7, the eighth MOS tube M8, the fifteenth MOS tube M15, the seventeenth MOS tube M17, the eighteenth MOS tube M18, the nineteenth MOS tube M19, the twentieth MOS tube M20, the twenty-first MOS tube M21, the twenty-fourth MOS tube M24, the twenty-fifth MOS tube M25, the twenty-sixth MOS tube M26 and the twenty-seventh MOS tube M27 are PMOS tubes; wherein the control end is the gate, the first end is the drain, and the second end is the source.

[0112] Correspondingly, this embodiment further provides a frequency detection method, comprising the following steps; wherein the frequency detection method is implemented using the frequency detection circuit 10 described above.

[0113] The clock frequency fclk of the clock signal is converted into an analog electrical signal. In one embodiment, the clock frequency fclk of the clock signal is converted into a clock current signal as an analog electrical signal output; in another embodiment, the clock frequency fclk of the clock signal is converted into a clock voltage signal as an analog electrical signal output; the relevant content is detailed above and will not be repeated here.

[0114] Without using an additional clock signal, the analog electrical signal is quantized into a digital signal for clock frequency detection. In one embodiment, the clock current signal is quantized into a digital signal; in another embodiment, the clock voltage signal is quantized into a digital signal; the relevant contents are described above and will not be repeated here.

[0115] The utility model also provides an image sensor, comprising a quantization circuit as described in any one of the above solutions. The quantization circuit can be arranged in a peripheral circuit area of ​​the image sensor. Furthermore, the image sensor can be applied to electronic devices, for example, the electronic devices can be security monitoring, vehicle-mounted electronics, mobile phone cameras, machine vision and other devices.

[0116] In summary, the frequency detection circuit and image sensor of the utility model convert the clock frequency of the clock signal into a current signal or voltage signal in the analog domain and then quantize it, without the need for an additional crystal oscillator to provide the main frequency, saving chip area, facilitating circuit integration, and reducing design costs. Therefore, the utility model effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0117] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the technology may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed in the present invention shall still be covered by the claims of the present invention.

Claims

1. A frequency detection circuit, characterized in that: The frequency detection circuit comprises: A frequency conversion module receives a clock signal and converts the clock frequency of the clock signal into an analog electrical signal for clock frequency detection; wherein the frequency conversion module includes a resistance acquisition unit, which receives the clock signal and converts the clock frequency of the clock signal into a clock resistance signal to obtain the analog electrical signal.

2. The frequency detection circuit according to claim 1, characterized in that: The resistance acquisition unit includes a first transmission gate, a second transmission gate, a first MOS transistor, a second MOS transistor, a first capacitor and a second capacitor. The input end of the first transmission gate is connected to the input end of the second transmission gate and serves as an access end of the resistance acquisition unit. The output end of the first transmission gate is connected to the first end of the first MOS transistor and is connected to a reference ground via the first capacitor. The first control end of the first transmission gate is connected to the control end of the second MOS transistor and receives the clock signal. The second control end of the first transmission gate receives an inverted signal of the clock signal. The output end of the second transmission gate is connected to the first end of the second MOS transistor and is connected to the reference ground via the second capacitor. The first control end of the second transmission gate receives the inverted signal of the clock signal. The second control end of the second transmission gate is connected to the control end of the first MOS transistor and receives the clock signal. The second ends of the first MOS transistor and the second MOS transistor are connected to the reference ground.

3. The frequency detection circuit according to claim 1, characterized in that: The frequency conversion module comprises: A voltage amplifying unit, connected to the access end of the resistance acquiring unit, receives a first voltage signal, and amplifies the first voltage signal to obtain a second voltage signal; a current generating unit connected to the voltage amplifying unit, generating a clock current signal based on the second voltage signal and the clock resistance signal and outputting the clock current signal as the analog electrical signal; Alternatively, the frequency conversion module further includes: a Miller compensation unit connected between the resistance acquisition unit and the voltage amplification unit.

4. The frequency detection circuit according to claim 3, characterized in that: The voltage amplification unit includes a first operational amplifier, a third MOS tube and a fourth MOS tube, wherein the first input end of the first operational amplifier is connected to the first voltage signal, the second input end of the first operational amplifier is connected to the access end of the resistance acquisition unit, the output end of the first operational amplifier is connected to the control end of the third MOS tube and connected to the access end of the resistance acquisition unit, the first end of the third MOS tube is connected to the second end of the fourth MOS tube, the second end of the third MOS tube is connected to the power supply voltage signal, the control end of the fourth MOS tube is connected to the first bias signal, and the first end of the fourth MOS tube is connected to the access end of the resistance acquisition unit; wherein, when the frequency conversion module further includes a Miller compensation unit, the output end of the first operational amplifier is connected to the access end of the resistance acquisition unit via the Miller compensation unit; The current generating unit includes a fifth MOS tube and a sixth MOS tube, the control end of the fifth MOS tube is connected to the output end of the first operational amplifier, the first end of the fifth MOS tube is connected to the second end of the sixth MOS tube, the second end of the fifth MOS tube is connected to the power supply voltage signal, the control end of the sixth MOS tube is connected to the first bias signal, and the first end of the sixth MOS tube serves as the output end of the current generating unit.

5. The frequency detection circuit according to claim 3, characterized in that: The frequency conversion module also includes: The voltage generating unit is connected to the current generating unit and is used to convert the clock current signal into a clock voltage signal and replace the clock current signal as the analog electrical signal output.

6. The frequency detection circuit according to claim 5, characterized in that: The voltage generating unit is implemented by using a first resistor.

7. The frequency detection circuit according to claim 6, characterized in that: The first resistor and the resistor acquisition unit are exchanged in position, wherein the current generation unit generates a fixed current signal based on the second voltage signal and the first resistance signal, and generates the clock voltage signal through the resistor acquisition unit.

8. The frequency detection circuit according to any one of claims 1 to 7, characterized in that: The frequency detection circuit also includes: The signal quantization module is connected to the frequency conversion module and quantizes the analog electrical signal into a digital signal without using an additional clock signal.

9. The frequency detection circuit according to claim 8, characterized in that: When the analog electrical signal includes a clock current signal, the signal quantization module includes: a charge-discharge unit connected to the frequency conversion module, performing a charge operation based on a difference between a first current signal and a second current signal within a first time and performing a discharge operation based on the second current signal within a second time to obtain a capacitor voltage signal, wherein the second current signal is the sum of the clock current signal and a third current signal; a comparison output unit connected to the charge-discharge unit, obtaining an output signal by comparing the capacitor voltage signal with a reference voltage signal, so as to quantize the clock current signal based on the duty cycle of the output signal; And / or, the comparison output unit includes a comparator, an inverter and a D flip-flop, the first input end of the comparator is connected to a reference voltage signal, the second input end of the comparator is connected to the output end of the charge and discharge unit, the output end of the comparator is connected to the input end of the inverter, the output end of the inverter is connected to the data end of the D flip-flop, the clock end of the D flip-flop is connected to the clock signal, and the output end of the D flip-flop serves as the output end of the comparison output unit.

10. The frequency detection circuit according to claim 9, characterized in that: The charging and discharging unit comprises: A first current part, used to generate the first current signal to perform a charging operation; A clock current part, connected to the frequency conversion module, for transmitting the clock current signal for discharging operation; A third current part, used for generating the third current signal to perform a discharge operation; The charge and discharge control part is respectively connected to the first current part, the clock current part and the third current part, and is used to simultaneously start the charging operation and the discharging operation within a first time under the control of the output signal, and to close the charging operation and continue the discharging operation within a second time.

11. The frequency detection circuit according to claim 10, characterized in that: The first current part includes a seventh MOS tube and an eighth MOS tube, the control end of the seventh MOS tube is connected to the first control voltage signal, the first end of the seventh MOS tube is connected to the second end of the eighth MOS tube, the second end of the seventh MOS tube is connected to the power supply voltage signal, the control end of the eighth MOS tube is connected to the first bias signal, and the first end of the eighth MOS tube serves as the current supply end of the first current part; And / or, the clock current part includes a ninth MOS tube, a tenth MOS tube, an eleventh MOS tube and a twelfth MOS tube, the control end of the ninth MOS tube is connected to the control end of the tenth MOS tube and connected to the second bias signal, the first end of the ninth MOS tube is connected to the output end of the frequency conversion module, the second end of the ninth MOS tube is connected to the first end of the eleventh MOS tube, the first end of the tenth MOS tube serves as the current supply end of the clock current part, the second end of the tenth MOS tube is connected to the first end of the twelfth MOS tube, the control end of the eleventh MOS tube is connected to the control end of the twelfth MOS tube and connected to the first end of the ninth MOS tube, and the second ends of the eleventh MOS tube and the twelfth MOS tube are connected to the reference ground; And / or, the third current part includes a thirteenth MOS tube and a fourteenth MOS tube, the control end of the thirteenth MOS tube is connected to the second bias signal, the first end of the thirteenth MOS tube serves as the current supply end of the third current part, the second end of the thirteenth MOS tube is connected to the first end of the fourteenth MOS tube, the control end of the fourteenth MOS tube is connected to the second control voltage signal, and the second end of the fourteenth MOS tube is connected to the reference ground; And / or, the charge and discharge control part includes a fifteenth MOS tube, a sixteenth MOS tube, a seventeenth MOS tube and a third capacitor, the control end of the fifteenth MOS tube is connected to the output signal, the first end of the fifteenth MOS tube is connected to the first end of the sixteenth MOS tube, the second end of the fifteenth MOS tube is connected to the second end of the seventeenth MOS tube and connected to the current supply end of the first current part, the control end of the sixteenth MOS tube is connected to its first end, the second end of the sixteenth MOS tube is connected to the reference ground, the control end of the seventeenth MOS tube is connected to the inverted signal of the output signal, the first end of the seventeenth MOS tube is connected to the first end of the third capacitor and connected to the clock current part and the current supply end of the third current part, the first end of the third capacitor serves as the output end of the charge and discharge unit, and the second end of the third capacitor is connected to the reference ground.

12. The frequency detection circuit according to claim 10, characterized in that: The charge and discharge unit further includes a voltage control providing part for providing a first voltage control signal to the first current part and a second voltage control signal to the third current part.

13. The frequency detection circuit according to claim 12, characterized in that: The voltage control providing part includes a second operational amplifier, an eighteenth MOS tube, a nineteenth MOS tube, a twentieth MOS tube, a twenty-first MOS tube, a twenty-second MOS tube, a twenty-third MOS tube and a second resistor. The first input end of the second operational amplifier is connected to a third voltage signal, the second input end of the second operational amplifier is connected to a first end of the second resistor, the output end of the second operational amplifier is connected to the control end of the eighteenth MOS tube and the nineteenth MOS tube, the output end of the second operational amplifier is also connected to the first end of the second resistor and serves as the first output end of the voltage control providing part, the first end of the eighteenth MOS tube is connected to the second end of the twentieth MOS tube, the second end of the eighteenth MOS tube is connected to a power supply voltage signal, the first end of the nineteenth MOS tube is connected to the twenty-first MOS tube the second end of the nineteenth MOS tube is connected to the power supply voltage signal, the control end of the twentieth MOS tube is connected to the control end of the twenty-first MOS tube and is connected to the first bias signal, the first end of the twentieth MOS tube is connected to the first end of the second resistor, the first end of the twenty-first MOS tube is connected to the first end of the twenty-second MOS tube and the control end of the twenty-third MOS tube and serves as the second output end of the control voltage providing part, the control end of the twenty-second MOS tube is connected to the second bias signal, the second end of the twenty-second MOS tube is connected to the first end of the twenty-third MOS tube, and the second ends of the twenty-third MOS tube and the second resistor are connected to the reference ground; or, the control voltage providing part further includes a Miller capacitor connected between the output end of the second operational amplifier and the first end of the second resistor.

14. The frequency detection circuit according to claim 9, characterized in that: When a clock voltage signal is used to replace a clock current signal as the analog electrical signal, the signal quantization module further includes: an input conversion unit connected between the frequency conversion module and the charge and discharge unit, and used to convert the clock voltage signal into the clock current signal.

15. The frequency detection circuit according to claim 14, characterized in that: The input conversion unit comprises: an amplifier part, connected to the frequency conversion module, and configured to amplify the clock voltage signal to obtain a fourth voltage signal; a voltage-current conversion part, connected to the amplifier part, for converting the fourth voltage signal into the clock current signal; Alternatively, the input conversion unit further includes a Miller compensation part connected between the amplifier part and the voltage-current conversion part.

16. The frequency detection circuit according to claim 15, characterized in that: The amplifier part includes a two-stage operational amplifier connected in a unit gain negative feedback; and / or, the voltage-current conversion part includes a twenty-fourth MOS transistor, a twenty-fifth MOS transistor, a twenty-sixth MOS transistor, a twenty-seventh MOS transistor and a third resistor, the control end of the twenty-fourth MOS transistor is connected to the control end of the twenty-fifth MOS transistor and connected to the fourth voltage signal, the first end of the twenty-fourth MOS transistor is connected to the second end of the twenty-sixth MOS transistor, the second end of the twenty-fourth MOS transistor is connected to the power supply voltage signal, the first end of the twenty-fifth MOS transistor is connected to the second end of the twenty-seventh MOS transistor, the second end of the twenty-fifth MOS transistor is connected to the power supply voltage signal, the control end of the twenty-sixth MOS transistor is connected to the control end of the twenty-seventh MOS transistor and connected to the first bias signal, the first end of the twenty-sixth MOS transistor is connected to the first end of the third resistor, the first end of the twenty-seventh MOS transistor serves as the output end of the input conversion unit, the first end of the third resistor is connected to the output end of the amplifier part, and the second end of the third resistor is connected to the reference ground; wherein, when the input conversion unit includes a Miller compensation part, the first end of the third resistor is connected to the output end of the amplifier part via the Miller compensation part.

17. The frequency detection circuit according to claim 8, characterized in that: The signal quantization module is implemented by a flash memory analog-to-digital converter, a successive approximation analog-to-digital converter or a pipeline analog-to-digital converter.

18. An image sensor, characterized in that: The method comprises the frequency detection circuit as claimed in any one of claims 1 to 17.

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