Cross coupling charge pump circuit

Abstract

The utility model discloses a cross coupling charge pump circuit, which comprises MOS (Metal Oxide Semiconductor) tubes M1-8, capacitors C1-4 and a capacitor CL, the source electrode of the MOS tube M1 and the source electrode of the MOS tube M2 are connected to a power supply VDD; the other end of the capacitor C2 is connected to a clock signal CKA3; the other end of the capacitor C1 is connected to a clock signal CKB3; the other end of the capacitor C3 is connected to a clock signal CKB2; the grid electrode of the MOS tube M4 is connected to a clock signal CKB1; the other end of the capacitor C4 is connected to a clock signal CKA2; the grid electrode of the MOS tube M6 is connected to a clock signal CKA1; the clock signal CKA1-3 and the clock signal CKB1-3 are non-overlapping clock signals; electric leakage can be avoided by using the non-overlapping clock, and the efficiency is higher than that of a traditional cross-coupled charge pump using an overlapping clock; frequent electric leakage output to the inside is avoided, so that output ripples are smaller; and electric leakage on the capacitor is avoided, so that charges accumulated on the capacitor are closer to an ideal value, and an output voltage value is closer to the ideal value.

Description

Technical Field

[0001] The utility model relates to the field of semiconductor integrated circuits, and particularly relates to a cross-coupled charge pump circuit. Background Art

[0002] With the rapid development of integrated circuits, the requirements for integration and low power consumption are getting higher and higher. Therefore, the power supply voltage becomes lower and lower. However, too low a power supply voltage may cause the circuit performance to decline and make the design more difficult. Therefore, a circuit that can provide a voltage higher than the power supply voltage is needed to solve the above problems. The charge pump is one of the circuits that can complete this function and is thus widely used.

[0003] The earliest used was the Dickson charge pump, which charges the capacitor through a diode under the control of a clock and transfers it level by level to finally realize the voltage boost. However, in this structure, due to the large voltage drop of the diode during voltage boost, the final output voltage is much lower than the ideal value. The more stages there are, the greater the deviation of the output voltage. After that, with the continuous emergence of many charge pump structures, the functions and performances of charge pumps have become better and better. Now, a widely used charge pump structure is the cross-coupled charge pump. This charge pump optimizes the problems of diode voltage drop loss or MOS transistor threshold loss existing in the previous charge pumps. During the transmission process, the MOS transistors can all conduct, alleviating the threshold loss problem. At the same time, this charge pump can complete the transmission work in each half cycle within a period, improving the utilization rate compared with the previous charge pumps.

[0004] When in application, there is a need for a two-fold voltage boost. Usually, the traditional cross-coupled circuit is cascaded to achieve this. Referring to Figure 1 , in Figure 1 In the shown charge pump circuit, V DD is the input voltage, V 1 is the output voltage of the first-stage charge pump, and V OUT is the total output voltage of the two-stage charge pump; this circuit first raises the voltage at the V 1 point by 1 V DD , and then raises it by another 1 V 1 on the basis of the V DD voltage. Finally, V OUT is raised by two V DD voltages to achieve a two-fold voltage boost; although this circuit realizes a two-fold voltage boost, since the clock CLK A and CLK B are overlapping clocks, there is a situation where the MOS transistors conduct simultaneously, resulting in leakage. Eventually, the efficiency will be reduced; at the same time, it will also cause the output voltage ripple to be large and deviate greatly from the ideal value. In addition, in order to meet the load requirements, the coupling capacitors C1 and C2 will also use large-capacitance capacitors, which will increase the area cost.

[0005] Therefore, there is an urgent need for a cross-coupled charge pump circuit to solve the above problems. Summary of the Invention

[0006] The present invention aims to solve at least one of the technical problems existing in the prior art. For this purpose, the present invention provides a cross-coupled charge pump circuit.

[0007] An embodiment of the present invention solves the technical problem by adopting the following technical solution: A cross-coupled charge pump circuit includes MOS transistors M1-8, capacitors C1-4, and capacitor CL;

[0008] The source of MOS transistor M1 and the source of MOS transistor M2 are connected to power supply V DD ;

[0009] The gate of MOS transistor M1 is respectively connected to one end of capacitor C2, the drain of MOS transistor M2, the source of MOS transistor M5, and the source of MOS transistor M6. The other end of capacitor C2 is connected to clock signal CKA3; The gate of MOS transistor M2 is respectively connected to one end of capacitor C1, the drain of MOS transistor M1, the source of MOS transistor M3, and the source of MOS transistor M4. The other end of capacitor C1 is connected to clock signal CKB3;

[0010] The gate of MOS transistor M3 is respectively connected to one end of capacitor C3, the drain of MOS transistor M4, the drain of MOS transistor M7, and the gate of MOS transistor M8. The other end of capacitor C3 is connected to clock signal CKB2; The gate of MOS transistor M4 is connected to the drain of MOS transistor M3 and clock signal CKB1;

[0011] The gate of MOS transistor M5 is respectively connected to one end of capacitor C4, the drain of MOS transistor M6, the gate of MOS transistor M7, and the drain of MOS transistor M8. The other end of capacitor C4 is connected to clock signal CKA2; The gate of MOS transistor M6 is connected to the drain of MOS transistor M5 and clock signal CKA1;

[0012] The sources of MOS transistors M7 and M8 are grounded through capacitor CL and output voltage V OUT , and clock signals CKA1, CKA2, CKA3, CKB1, CKB2, and CKB3 are non-overlapping clock signals.

[0013] As one of the preferred embodiments of the present invention, a cross-coupled charge pump circuit further includes a capacitor C5 with one end respectively connected to the drain of MOS transistor M3 and the gate of MOS transistor M4 and the other end connected to clock signal CKB1.

[0014] As one of the preferred embodiments of the present utility model, the capacitance value of capacitor C5 is smaller than that of capacitors C1, C2, C3, and C4.

[0015] As one of the preferred embodiments of the present utility model, a cross-coupled charge pump circuit further includes a capacitor C6 with one end connected to the drain of MOS transistor M5 and the gate of MOS transistor M6 respectively, and the other end connected to the clock signal CKA1.

[0016] As one of the preferred embodiments of the present utility model, the capacitance value of capacitor C6 is smaller than that of capacitors C1, C2, C3, and C4.

[0017] As one of the preferred embodiments of the present utility model, MOS transistors M1-6 are set as NMOS transistors, and MOS transistors M7 and M8 are set as PMOS transistors.

[0018] As one of the preferred embodiments of the present utility model, the capacitance values of capacitors C1 and C2 are smaller than those of capacitors C3 and C4.

[0019] Advantages of the present utility model:

[0020] 1. Using non-overlapping clocks can avoid leakage, and the efficiency will be higher than that of traditional cross-coupled charge pumps using overlapping clocks;

[0021] 2. There will be no frequent leakage from the output to the inside, making the output ripple smaller;

[0022] 3. Since leakage on the capacitor is avoided, the charge accumulated on the capacitor is closer to the ideal value, making the output voltage value closer to the ideal value. Description of the drawings

[0023] The above and / or additional aspects and advantages of the present utility model will become apparent and be easily understood from the description of the embodiments in conjunction with the following drawings, where:

[0024] Figure 1 is the circuit schematic diagram of the existing charge pump circuit;

[0025] Figure 2 is the circuit schematic diagram of the cross-coupled charge pump circuit provided by the present utility model;

[0026] Figure 3 is the timing diagram of the non-overlapping clock. Detailed implementation manners

[0027] This section will describe in detail the specific embodiments of the present utility model. The preferred embodiments of the present utility model are shown in the accompanying drawings. The function of the accompanying drawings is to supplement the description in the text part of the specification, enabling people to intuitively and vividly understand each technical feature and the overall technical solution of the present utility model. However, it should not be construed as a limitation on the protection scope of the present utility model.

[0028] In the description of the present utility model, the meaning of "a plurality of" is more than two. Understandings such as "greater than", "less than", and "exceeding" do not include the present number, and understandings such as "above", "below", and "within" include the present number. If there is a description of "first" and "second", it is only for the purpose of distinguishing technical features and cannot be construed as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features or implicitly indicating the sequence relationship of the indicated technical features.

[0029] In the description of the present utility model, it should be understood that for the orientation description, such as the orientation or position relationship indicated by "upper", "lower", "front", "rear", "left", "right", etc., is based on the orientation or position relationship shown in the accompanying drawings. It is only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the indicated device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be construed as a limitation on the present utility model.

[0030] In the present utility model, unless otherwise clearly defined, terms such as "set", "installed", and "connected" should be understood in a broad sense. For example, it can be directly connected, or indirectly connected through an intermediate medium; it can be fixedly connected, or detachably connected, and can also be integrally formed; it can be mechanically connected; it can be the communication inside two elements or the interaction relationship between two elements. Those skilled in the art can reasonably determine the specific meanings of the above terms in the present utility model in combination with the specific content of the technical solution.

[0031] Refer to Figures 2 to 3 , a cross-coupled charge pump circuit, including MOS transistors M1-8, capacitors C1-4, and capacitor CL;

[0032] The source electrodes of MOS transistor M1 and MOS transistor M2 are connected to power supply V DD ;

[0033] The gate electrode of MOS transistor M1 is respectively connected to one end of capacitor C2, the drain electrode of MOS transistor M2, the source electrode of MOS transistor M5, and the source electrode of MOS transistor M6. The other end of capacitor C2 is connected to clock signal CKA3; the gate electrode of MOS transistor M2 is respectively connected to one end of capacitor C1, the drain electrode of MOS transistor M1, the source electrode of MOS transistor M3, and the source electrode of MOS transistor M4. The other end of capacitor C1 is connected to clock signal CKB3;

[0034] The gate of MOS transistor M3 is connected to one end of capacitor C3, the drain of MOS transistor M4, the drain of MOS transistor M7, and the gate of MOS transistor M8 respectively. The other end of capacitor C3 is connected to clock signal CKB2. The gate of MOS transistor M4 is connected to the drain of MOS transistor M3 and clock signal CKB1.

[0035] The gate of MOS transistor M5 is connected to one end of capacitor C4, the drain of MOS transistor M6, the gate of MOS transistor M7, and the drain of MOS transistor M8 respectively. The other end of capacitor C4 is connected to clock signal CKA2. The gate of MOS transistor M6 is connected to the drain of MOS transistor M5 and clock signal CKA1.

[0036] The sources of MOS transistor M7 and MOS transistor M8 are grounded through capacitor CL and output voltage V OUT , and clock signals CKA1, CKA2, CKA3, CKB1, CKB2, and CKB3 are non-overlapping clock signals.

[0037] The working principle of the present invention is as follows:

[0038] ① Refer to Figures 2-3 , in the first half cycle, CKA3 = 1, CKB3 = 0. Since the voltage across capacitor C2 was charged to V in the previous stage DD , the voltage at point V2 is raised to 2V DD , MOS transistor M1 conducts, and V DD charges capacitor C1 through MOS transistor M1, and finally V1 is charged to V DD . At this time, CKA1 = 1, CKA2 = 0, and the voltage across capacitor C6 was charged to V in the previous stage DD , so the voltage at point V6 is raised to 3V DD . The voltage at point V4 drops from 3V DD to 2V DD because CKA2 drops to 0. At this moment, MOS transistor M6 conducts, and capacitor C4 is charged by the voltage at point V2 through MOS transistor M6 so that the voltage at point V4 remains at 2V DD . Also, because CKB1 = 0, CKB2 = 1, and the voltage across capacitor C3 was charged to 2V in the previous stage DD , the voltage at point V3 is raised to 3V DD , MOS transistor M3 conducts, and the voltage across capacitor C5 is charged to V DD , that is, the voltage at point V5 is V DD . Also, because the voltage at point V4 is 2V at this time DD , MOS transistor M7 conducts while MOS transistor M8 turns off, and the voltage at point V3 provides 3V for output voltage V OUT through MOS transistor M7. DDThe voltage also powers the load capacitor CL. At this point, the charge pump circuit has completed the work of the first half cycle.

[0039] ②In the second half of the cycle, CKA3=0, CKB3=1, which is opposite to the first half of the cycle. At this time, the voltage at point V1 is raised to 2V DD , MOS tube M2 is turned on, and the voltage across capacitor C2 is charged to V DD , that is, the voltage at point V2 is V DD , at this time CKB1 = 1, CKB2 = 0, so the voltage at point V5 is raised to 3V DD , the voltage across capacitor C3 drops to 2V because CKB2 drops to 0 DD At this moment, MOS tube M4 is turned on, and capacitor C3 is charged by the voltage at point V1 through MOS tube M4, so that the voltage at point V3 remains at 2V DD ; and because CKA1=0, CKA2=1, the voltage at point V4 is raised to 3V DD , MOS tube M5 is turned on, and the voltage across capacitor C6 is charged to V DD , that is, the voltage at point V6 is V DD , and because the voltage at point V3 is 2V DD , so MOS tube M8 is turned on and MOS tube M7 is turned off, and the voltage at point V4 passes through MOS tube M8 to become the output voltage V OUT Provide 3V DD The voltage also powers the load capacitor CL. At this point, the charge pump circuit has completed the second half of the cycle.

[0040] Each cycle of the charge pump circuit is divided into a front and a rear half cycle to respectively turn on the MOS tube M7 and the MOS tube M8 to complete the output voltage V OUT is charged, so that the output voltage V OUT =3V DD , thereby achieving an output voltage V OUT Complete double boost (at input voltage V DD Raised 2V DD voltage) function.

[0041] ③ Reference Figure 3 , before T1:

[0042] (1) CKB1 is 0 first, and CKB3 is 0 later. If CKB3 is 0 first, the voltage at point V1 is VDD. At this time, CKB1 is 1, so the voltage at point V5 is 2V DD , then MOS tube M4 is turned on, at this time CKB2=0, so the voltage at point V3 is 2V DD , eventually current will flow out of capacitor C3; and if CKB1 is 0 first, then the voltage at point V5 will drop to V DD , the voltage at point V1 is 2V​​​DD , MOS transistor M4 will not conduct. Then CKB3 drops to 0, and the voltage at point V1 drops to V DD , MOS transistor M4 still will not conduct, avoiding leakage.

[0043] (2) CKB2 is 1 first, and CKA2 is 0 later. If CKA2 is 0 first, the voltage at point V4 drops to 2V DD , at this time the voltage at point V3 is still 2V DD , and because the V OUT voltage is 3V DD , so both MOS transistor M7 and MOS transistor M8 conduct, and there will be leakage from the output to nodes V3 and V4; therefore, CKB2 should be 1 first, then the voltage at point V3 is raised to 3V DD , and at this time the voltage at point V4 is also 3V DD , then both MOS transistor M7 and MOS transistor M8 will not conduct, so there will be no leakage.

[0044] (3) CKA3 is 1 first, and CKA1 is 1 later. If CKA1 is 1 first, the voltage at point V6 is raised to 2V DD , and the voltage at point V2 is still V DD , so MOS transistor M6 conducts. At this time, CKA2 = 0, and the voltage at point V4 is 2V DD , and there will be current flowing out from capacitor C4; while if CKA3 is 1 first, then the voltage at point V2 is 2V DD , the voltage at point V6 is V DD , MOS transistor M6 will not conduct, avoiding leakage.

[0045] ④ Refer to Figure 3 , after time T2, the specific situation is similar to that before time T1, which will not be elaborated here. The conclusion is directly given as follows:

[0046] (1) CKA1 is 0 first, and CKA3 is 0 later, avoiding the conduction and leakage of MOS transistor M6.

[0047] (2) CKA2 is 1 first, and CKB2 is 0 later, avoiding the conduction and leakage of MOS transistor M7 and MOS transistor M8.

[0048] (3) CKB3 is 1 first, and CKB1 is 1 later, avoiding the conduction and leakage of MOS transistor M4.

[0049] ⑤ The advantages of the present utility model are as follows:

[0050] (1) Using non-overlapping clocks can avoid leakage, and the efficiency will be higher than that of the traditional cross-coupled charge pump using overlapping clocks;

[0051] (2) There will be no frequent leakage from the output to the inside, making the output ripple smaller;

[0052] (3) Since the leakage of the capacitor is avoided, the charge accumulated on the capacitor is closer to the ideal value, and the output voltage value is also closer to the ideal value.

[0053] Preferably, the MOS transistors M1-6 are set as NMOS transistors, and the MOS transistors M7 and M8 are set as PMOS transistors.

[0054] In an embodiment provided by the present invention, the capacitors mainly providing the load capacity are C3 and C4, and the capacitors C1 and C2 are secondary power supply capacitors. Therefore, only the capacitance values of C3 and C4 need to be large (the same as those in the traditional structure), and the capacitance values of C1 and C2 are smaller than those of C3 and C4.

[0055] In another embodiment, a cross-coupled charge pump circuit further includes a capacitor C5 with one end connected to the drain of the MOS transistor M3 and the gate of the MOS transistor M4 respectively and the other end connected to the clock signal CKB1, and further includes a capacitor C6 with one end connected to the drain of the MOS transistor M5 and the gate of the MOS transistor M6 respectively and the other end connected to the clock signal CKA1; and the capacitance values of C5 and C6 are smaller than those of C1, C2, C3 and C4; C5 and C6 are capacitors for boosting the gate voltage of the MOS transistors, only used to assist the conduction of the MOS transistors M4 and M6. Therefore, their capacitance values are much smaller than those of C1, C2, C3 and C4, so that the total capacitance value will be smaller than that in the traditional structure, and the area can be saved; and, since there are two capacitors C5 and C6 to assist the conduction of the MOS transistors M4 and M6, the capacitors C3 and C4 can be charged more quickly at the beginning stage when C3 and C4 are charged, and at the same time, the MOS transistors M4 and M6 can be fully conducted, reducing the conduction impedance, making the voltages at both ends of C3 and C4 closer to the ideal value. At the same time, because there is no leakage problem, at the same clock frequency and load capacitance, more energy is provided for the output voltage V OUT Therefore, the load capacity of the charge pump designed by the present invention is stronger than that of the traditional architecture.

[0056] Of course, the present invention is not limited to the above embodiments. Those skilled in the art can make equivalent deformations or substitutions without departing from the spirit of the present invention, and these equivalent deformations and substitutions are all included in the scope defined by the claims of this application.

Claims

1. A cross-coupled charge pump circuit, characterized in that: Including MOS tubes M1-8, capacitors C1-4 and capacitor CL; The source of MOS tube M1 and the source of MOS tube M2 are connected to the power supply V DD ; The gate of the MOS transistor M1 is respectively connected to one end of the capacitor C2, the drain of the MOS transistor M2, the source of the MOS transistor M5 and the source of the MOS transistor M6, and the other end of the capacitor C2 is connected to the clock signal CKA3; the gate of the MOS transistor M2 is respectively connected to one end of the capacitor C1, the drain of the MOS transistor M1, the source of the MOS transistor M3 and the source of the MOS transistor M4, and the other end of the capacitor C1 is connected to the clock signal CKB3; The gate of the MOS transistor M3 is respectively connected to one end of the capacitor C3, the drain of the MOS transistor M4, the drain of the MOS transistor M7 and the gate of the MOS transistor M8, and the other end of the capacitor C3 is connected to the clock signal CKB2; the gate of the MOS transistor M4 is connected to the drain of the MOS transistor M3 and the clock signal CKB1; The gate of the MOS tube M5 is respectively connected to one end of the capacitor C4, the drain of the MOS tube M6, the gate of the MOS tube M7 and the drain of the MOS tube M8, and the other end of the capacitor C4 is connected to the clock signal CKA2; the gate of the MOS tube M6 is connected to the drain of the MOS tube M5 and the clock signal CKA1; The source of the MOS tube M7 and the source of the MOS tube M8 are grounded through the capacitor CL and the output voltage V OUT , the clock signals CKA1, CKA2, CKA3, CKB1, CKB2 and CKB3 are non-overlapping clock signals.

2. A cross-coupled charge pump circuit according to claim 1, characterized in that: It also includes a capacitor C5 whose one end is connected to the drain of the MOS transistor M3 and the gate of the MOS transistor M4 respectively, and the other end is connected to the clock signal CKB1.

3. A cross-coupled charge pump circuit according to claim 2, characterized in that: The capacitance of the capacitor C5 is smaller than the capacitances of the capacitors C1 , C2 , C3 and C4 .

4. The cross-coupled charge pump circuit according to claim 1, characterized in that: It also includes a capacitor C6 whose one end is connected to the drain of the MOS transistor M5 and the gate of the MOS transistor M6 respectively, and the other end is connected to the clock signal CKA1.

5. A cross-coupled charge pump circuit according to claim 4, characterized in that: The capacitance of the capacitor C6 is smaller than the capacitances of the capacitors C1 , C2 , C3 and C4 .

6. The cross-coupled charge pump circuit according to claim 1, characterized in that: The MOS tubes M1-6 are configured as NMOS tubes, and the MOS tubes M7 and M8 are configured as PMOS tubes.

7. The cross-coupled charge pump circuit according to claim 1, characterized in that: The capacitance of the capacitor C1 and the capacitor C2 is smaller than the capacitance of the capacitor C3 and the capacitor C4.

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