Debugging system

Abstract

The embodiment of the utility model discloses a debugging system. The debugging system comprises an upper computer and debugging equipment, the debugging device comprises a control mainboard and an interface mainboard. The upper computer is electrically connected with the control mainboard; the interface main board comprises a joint test working group interface circuit and a combined interface circuit; the joint test working group interface circuit and the combined interface circuit are used for connecting to-be-tested chips with different test interfaces; the upper computer sends a preset debugging signal to the connected to-be-tested chip through the control mainboard and the interface mainboard, debugging of the to-be-tested chip is achieved, and the preset debugging signal is determined by an instruction set architecture of the to-be-tested chip. According to the method and the device, the preset debugging signal is set in the upper computer, and the debugging of different to-be-tested chips is realized by utilizing various different interfaces integrated on the interface mainboard, so that the technical problems that the universality of debugging equipment in the prior art is poor, and the chips with specific instruction architecture sets and different interfaces cannot be directly debugged are solved.

Description

Technical Field

[0001] The embodiment of the utility model relates to the technical field of chip debugging, and in particular to a debugging system. Background Art

[0002] As the market demand for artificial intelligence computing power (including training and reasoning) increases, artificial intelligence chips for various scenarios are emerging in the market. Since AI (Artificial Intelligence) chips are different from any general x86, ARM (Advanced RISC Machine) or MIPS (Million Instructions Per Second, the average execution speed of single-word fixed-point instructions) architecture, almost all AI chips have their own instruction set architecture (ISA), and in-circuit debugging (ICD) of the chip is an indispensable requirement. Therefore, there is a problem that there is no general debugger on the market that can support the online debugging of self-developed AI chips. Secondary development based on general debugging equipment and tools is not only inefficient, but also has poor versatility, is difficult to maintain, and has high hardware purchase and development and maintenance costs. Utility Model Content

[0003] The embodiment of the utility model provides a debugging system, which solves the technical problem that the debugging equipment in the prior art has poor versatility and cannot directly debug chips with a specific instruction architecture set and different interfaces.

[0004] The utility model embodiment provides a debugging system, the debugging system comprises a host computer and a debugging device; the debugging device comprises a control mainboard and an interface mainboard;

[0005] The host computer is electrically connected to the control mainboard;

[0006] The interface mainboard includes a joint test working group interface circuit and a combination interface circuit, wherein the joint test working group interface circuit includes a joint test working group interface, and the combination interface circuit includes two asynchronous receiver and transmitter interfaces, five integrated circuit bus interfaces, and one serial peripheral interface; the interface mainboard is used to connect chips to be tested with different test interfaces;

[0007] The host computer uses the interface mainboard to send a preset debugging signal to the connected chip under test through the control mainboard to debug the chip under test, wherein the preset debugging signal is determined by the instruction set architecture of the chip under test.

[0008] Furthermore, the interface mainboard also includes a first universal serial bus interface;

[0009] The host computer and the control main board are connected to each other through the first universal serial bus interface, or the host computer and the control main board are connected to each other through Ethernet.

[0010] Furthermore, the interface mainboard further comprises a signal conversion circuit; the signal conversion circuit comprises a second universal serial bus interface, a signal conversion chip and a level conversion chip;

[0011] The control mainboard is connected to the signal conversion chip via the second universal serial bus interface;

[0012] The signal conversion chip is used to convert the preset debugging signal transmitted from the control mainboard into a signal transmittable by the joint test working group interface or the asynchronous receiver-transmitter interface;

[0013] The level conversion chip is used to amplify the preset debugging signal transmittable by the joint test working group interface.

[0014] Furthermore, the interface mainboard also includes a universal input and output interface, and the universal input and output interface is provided with a preset number of pins;

[0015] The universal input and output interface is used to realize the transmission of the preset debugging signal between the control main board and the interface main board.

[0016] Furthermore, the debugging device also includes a switching switch; the switching switch is used to switch the communication connection mode between the host computer and the control main board, wherein the communication connection mode includes realizing communication connection through the first universal serial bus interface, and realizing communication connection through Ethernet.

[0017] Furthermore, the interface mainboard also includes a serial peripheral interface signal amplification circuit;

[0018] The serial peripheral interface signal amplifying circuit is arranged between the universal input and output interface and the combined interface circuit.

[0019] Furthermore, the interface mainboard also includes an asynchronous receiver / transmitter interface signal amplification circuit;

[0020] The asynchronous receiver-transmitter interface signal amplifying circuit is arranged between the signal conversion circuit and the combined interface circuit.

[0021] Furthermore, the interface mainboard also includes an integrated circuit bus interface expansion circuit;

[0022] The integrated circuit bus interface expansion circuit is arranged between the universal input and output interface and the combination interface circuit.

[0023] Furthermore, the interface mainboard also includes a dip switch;

[0024] The dip switch is used to switch the signal transmission channel between the control main board and the interface main board, wherein the signal transmission channel includes the transmission of the preset debugging signal through the signal conversion circuit, and the transmission of the preset debugging signal through the universal input and output interface.

[0025] Furthermore, the control main board is a Raspberry Pi board, and the chip to be tested is a chip used to process computing tasks in artificial intelligence applications.

[0026] The utility model embodiment discloses a debugging system, including a host computer and a debugging device; the debugging device includes a control mainboard and an interface mainboard; the host computer is electrically connected to the control mainboard; the interface mainboard includes a joint test working group interface circuit and a combination interface circuit; the joint test working group interface circuit and the combination interface circuit are used to connect a chip to be tested with different test interfaces; the host computer uses the interface mainboard to send a preset debugging signal to the connected chip to be tested through the control mainboard to debug the chip to be tested, wherein the preset debugging signal is determined by the instruction set architecture of the chip to be tested. The present application solves the technical problem that the debugging device in the prior art has poor versatility and cannot directly debug chips with a specific instruction architecture set and different interfaces by setting a preset debugging signal in the host computer and using a variety of different interfaces integrated on the interface mainboard, thereby achieving the technical effect of improving the versatility of the debugging system, shortening the development and maintenance cycle, and significantly improving the chip debugging efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a structural diagram of a debugging system provided by an embodiment of the utility model;

[0028] Figure 2 It is a schematic diagram of a joint test working group interface circuit provided by an embodiment of the utility model;

[0029] Figure 3 It is a schematic diagram of a combined interface circuit provided by an embodiment of the utility model;

[0030] Figure 4 is a schematic diagram of a signal conversion circuit provided by an embodiment of the utility model;

[0031] Figure 5 It is a schematic diagram of a universal input and output interface provided by an embodiment of the utility model;

[0032] Figure 6 It is a schematic diagram of a serial peripheral interface signal amplifying circuit provided by an embodiment of the utility model;

[0033] Figure 7 It is a schematic diagram of an asynchronous receiver / transmitter interface signal amplifying circuit provided by an embodiment of the utility model;

[0034] Figure 8 It is a schematic diagram of an integrated circuit bus interface expansion circuit provided by an embodiment of the utility model. DETAILED DESCRIPTION

[0035] The present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only the parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0036] It should be noted that the terms "first", "second", etc. in the specification, claims and drawings of the utility model are used to distinguish different objects, rather than to limit a specific order. The following embodiments of the utility model can be implemented separately, and the embodiments can also be implemented in combination with each other, and the embodiments of the utility model do not make specific limitations on this.

[0037] Figure 1 It is a structural diagram of a debugging system provided by an embodiment of the utility model.

[0038] like Figure 1 As shown, the debugging system includes a host computer 10 and a debugging device 20 ; the debugging device 20 includes a control mainboard 21 and an interface mainboard 22 ; the host computer 10 is electrically connected to the control mainboard 21 .

[0039] The interface mainboard 21 includes a joint test working group interface circuit and a combination interface circuit. Figure 2 is a schematic diagram of a joint test working group interface circuit provided by an embodiment of the utility model, Figure 3 is a schematic diagram of a combined interface circuit provided by an embodiment of the utility model, such as Figure 2 As shown, the joint test working group interface circuit includes a joint test working group (Joint Test Action Group, JTAG) interface, such as Figure 3As shown, the combined interface circuit includes two asynchronous receiver and transmitter (Universal Asynchronous Receiver Transmitter, UART) interfaces, five integrated circuit bus (Inter Integrated Circuit, I2C) interfaces and one serial peripheral interface (Serial Peripheral Interface, SPI) interface; the interface mainboard 22 is used to connect the chip 30 to be tested with different test interfaces;

[0040] The host computer 10 controls the main board 21 and uses the interface main board 22 to send a preset debugging signal to the connected chip under test 30 to debug the chip under test 30 , wherein the preset debugging signal is determined by the instruction set architecture of the chip under test 30 .

[0041] For example, see Figure 2 The joint test working group interface circuit includes a 2×7Pin joint test working group interface, wherein pin 1 of the joint test working group interface is a TDI pin, pins 2, 4, and 6 are all GND pins, connected to ground GND0, pin 3 is a TDO pin, pin 5 is a TCK pin, pins 7, 12, and 13 are empty, all are NC pins, pin 8 is empty as a KEY pin, pin 9 is an NSRST pin, pin 10 is a TMS pin, pin 11 is a VCC pin, connected to the power supply VCC_JTAGREF, and pin 14 is an NTRST pin; pin 11 is also connected to ground GND through two parallel capacitors C1 and C2.

[0042] For example, see Figure 3 The combination interface circuit includes a 2×15Pin combination interface, which integrates 2 asynchronous receiver-transmitter interfaces, 5 integrated circuit bus interfaces and 1 serial peripheral interface.

[0043] Among them, see Figure 3 , pins 1, 2, 4, 5, 7, 8, 10, 11, 13, and 14 of the combination interface are all pins for transmitting integrated circuit bus signals. Specifically, pin 1 is the I2C0_SCL pin, pin 2 is the I2C0_SDA pin, pin 4 is the I2C1_SCL pin, pin 5 is the I2C1_SDA pin, pin 7 is the I2C2_SCL pin, pin 8 is the I2C2_SDA pin, pin 10 is the I2C3_SCL pin, pin 11 is the I2C3_SDA pin, pin 13 is the I2C4_SCL pin, and pin 14 is the I2C4_SDA pin.

[0044] See also Figure 3Pins 18, 19, 29, and 30 of the combined interface are all pins for transmitting asynchronous receiver and transmitter signals. Specifically, pin 18 is the UART1_TXD pin, and pin 18 is also connected to the power supply VCC_UARTREF through the first resistor R1; pin 19 is the UART1_RXD pin, and pin 19 is also connected to the power supply VCC_UARTREF through the second resistor R2; pin 29 is the UART2_TXD pin, and pin 29 is also connected to the power supply VCC_UARTREF through the third resistor R3; pin 30 is the UART2_RXD pin, and pin 30 is also connected to the power supply VCC_UARTREF through the fourth resistor R4.

[0045] See also Figure 3 Pins 21, 23, 24, 25, and 26 of the combination interface are all pins for transmitting serial peripheral interface signals. Specifically, pin 21 is connected to the control end of the serial peripheral interface and receives the SPI_REF signal, pin 23 is the SPI_CE pin, pin 24 is the SPI_SCLK pin, pin 25 is the SPI_MISO pin, and pin 26 is the SPI_MOSI pin.

[0046] See also Figure 3 , pins 3, 6, 9, 12, 15, 17, 22, and 28 of the combination interface are all GND pins, grounded GND0, pin 16 is connected to the power supply VCC_UARTREF, pin 20 is left empty, and pin 27 is connected to the power supply VCC_UARTREF.

[0047] Specifically, the debugging device 20 can be designed as a hardware debug (computer troubleshooting) box (EnFlameDebug Box, EFDB), and the host computer 10 is a debug tool (Enflame Debug Manager, EFDM) supporting the debugging device 20. EFDB is connected to the corresponding interface on the board where the chip under test 30 is located through a serial port such as JTAG, SPI, I2C or UART, thereby realizing the connection with the chip under test 30. After the connection is completed, the chip under test 30 is controlled and debugged through the above-mentioned interface, so as to achieve the purpose of debugging the chip under test 30 through a variety of different protocols or means (i.e., protocols corresponding to different interfaces, etc.) through one debugging device 20.

[0048] It should be noted that since different chips under test 30, especially a certain series of self-developed chips under test 30, have their own unique instruction set architecture, the host computer 10 is pre-set with corresponding preset debugging signals according to the instruction set architecture of the chip under test 30. The display device and human-computer interaction device of the host computer 10 can conveniently and intuitively select and send preset debugging signals to realize online debugging of the self-developed chip under test 30.

[0049] This application sets a preset debugging signal in the host computer and uses a variety of different interfaces integrated on the interface mainboard to debug different chips under test. It solves the technical problem that the debugging equipment in the prior art has poor versatility and chips with specific instruction architecture sets and different interfaces cannot be directly debugged. It achieves the technical effect of improving the versatility of the debugging system, shortening the development and maintenance cycle, and significantly improving the chip debugging efficiency.

[0050] Optionally, the interface mainboard 22 also includes a first universal serial bus (USB) interface; the host computer 10 and the control mainboard 21 are communicated through the first universal serial bus interface, or the host computer 10 and the control mainboard 21 are communicated through Ethernet.

[0051] Optionally, the debugging device 20 also includes a switch (Switch); the switch is used to switch the communication connection mode between the host computer 10 and the control mainboard 21, wherein the communication connection mode includes realizing communication connection through a first universal serial bus interface, and realizing communication connection through Ethernet.

[0052] Specifically, when using it, the user only needs to enter the IP address of the debugging device 20 in the host computer 10, and all debugging work on the chip under test 30 can be realized remotely through Ethernet; or through the USB Switch on the debugging device 20, switch to the USB direct connection mode, that is, switch to the first universal serial bus interface connection mode, so that the chip under test 30 can be debugged directly without connecting to the Internet.

[0053] Figure 4 It is a schematic diagram of a signal conversion circuit provided by an embodiment of the utility model.

[0054] Alternatively, if Figure 4 As shown, the interface mainboard 22 also includes a signal conversion circuit; the signal conversion circuit includes a second Universal Serial Bus (USB) interface, a signal conversion chip U1 and a level conversion chip U2; the control mainboard 21 is connected to the signal conversion chip U1 through the second Universal Serial Bus interface; the signal conversion chip U1 is used to convert the preset debugging signal transmitted from the control mainboard 21 into a signal that can be transmitted by the Joint Test Group (JTAG) interface or the asynchronous receiver-transmitter (UART) interface; the level conversion chip U2 is used to amplify the preset debugging signal that can be transmitted by the Joint Test Group interface.

[0055] Specifically, the signal conversion chip U1 can use the FT2232D chip, which is used to convert the preset debugging signal transmitted by the control mainboard 21 through the second universal serial bus interface into a signal that can be transmitted by the Joint Test Group (JTAG) interface or the asynchronous receiver-transmitter (UART) interface. The level conversion chip U2 can use the SN74ALVC164245 chip, which is used to amplify the preset debugging signal converted by the signal conversion chip U1.

[0056] like Figure 4 As shown, pin 7 and pin 8 in the signal conversion chip U1 are respectively used to connect the positive USB D+ and negative USB D- ends of the second universal serial bus interface, and pins 17, 22, 13, 11, 15, 12, 21, 23, and 24 in the signal conversion chip U1 are used to output the converted preset debugging signal that can be transmitted by the Joint Test Group (JTAG) interface to the level conversion chip U2, wherein pin 17 of the signal conversion chip U1 is the SRST N IN pin, pin 22 is the TDO IN pin, pin 13 is the SRSTN OUT pin, pin 11 is the SRST N OEN pin, pin 15 is the TRST N OUT pin, pin 12 is the TRST N OEN pin, pin 21 is the TMS OUT pin, pin 23 is the TDIOUT pin, and pin 24 is the TCK OUT pin.

[0057] See also Figure 4 , pins 17, 22, 13, 11, 15, 12, 21, 23, and 24 in the signal conversion chip U1 are respectively connected to pins 14, 13, 11, 9, 8, 6, 5, 3, and 2 in the level conversion chip U2; the signal conversion chip U1 outputs the converted preset debugging signal that can be transmitted by the joint test working group interface to the level conversion chip U2, and the level conversion chip U2 amplifies the preset debugging signal and outputs it through pins 47, 46, 44, 43, 41, 40, 38, 36, and 35 Figure 2 The joint test working group interface circuit is shown.

[0058] Specifically, pin 47 of the level conversion chip U2 outputs the TCK signal to Figure 2 Pin 5 of the joint test working group interface; Pin 46 of the level conversion chip U2 outputs the TDI signal to Figure 2 Pin 1 of the joint test working group interface; Pin 44 of the level conversion chip U2 outputs the TMS signal to Figure 2 Pin 10 of the joint test working group interface; Pins 43 and 41 of the level conversion chip U2 output the NTRST signal to a line driver chip U3. Figure 2Pin 14 of the joint test working group interface, wherein the line driver chip U3 can use chip 74AHCT1G125, pin 43 of U2 is connected to the CE# pin of U3, pin 41 of U2 is connected to the A pin of U3, the ground pin GND of U3 is grounded to GND0, the power pin VCC of U3 is connected to the power supply VCC1, and the Y pin of U3 outputs the NTRST signal; pins 40, 38, and 35 of the level conversion chip U2 output the NSRST signal to a line driver chip U4. Figure 2 Pin 9 of the joint test working group interface, wherein the line driver chip U4 can use chip 74AHCT1G125, pin 40 of U2 is connected to the CE# pin of U4, pin 38 of U2 is connected to the A pin of U4, the ground pin GND of U4 is connected to the ground GND0, the power pin VCC of U4 is connected to the power supply VCC1, pin 35 of U2 is connected to the Y pin of U4, and the Y pin of U4 outputs the NSRST signal; pin 36 of the level conversion chip U2 outputs the TDO signal to Figure 2 Pin 3 of the JTWG interface.

[0059] like Figure 4 As shown, pins 39 and 40 in the signal conversion chip U1 are used to output the converted preset debugging signal that can be transmitted by the asynchronous receiver-transmitter (UART) interface to the following Figure 7 The asynchronous receiver / transmitter interface signal amplifying circuit shown in the figure amplifies the signal, wherein pin 39 is the USB RXD pin and pin 40 is the USB TXD pin.

[0060] It should be noted that Figure 4 The signal conversion circuit shown in FIG. 1 also includes conventional peripheral circuits that enable the signal conversion chip U1 and the level conversion chip U2 to achieve their respective functions. Figure 4 It is not reflected in the text and will not be described here.

[0061] Figure 5 It is a schematic diagram of a universal input and output interface provided by an embodiment of the utility model.

[0062] Alternatively, if Figure 5 As shown, the interface mainboard also includes a general-purpose input / output (GPIO) interface, which is provided with a preset number of pins; the general-purpose input / output interface is used to realize the transmission of preset debugging signals between the control mainboard 21 and the interface mainboard 22.

[0063] Specifically, the universal input and output interface is used to realize the transmission of preset debugging signals of the integrated circuit bus interface, the serial peripheral interface and one of the asynchronous receiver and transmitter interfaces between the control main board 21 and the interface main board 22 .

[0064] For example, Figure 5 As shown, the universal input and output interface is a 2×20Pin interface, wherein pins 3, 5, and 7 are channels for transmitting integrated circuit bus interface signals, pin 3 is the I2C SDA pin, pin 5 is the I2C SCL pin, and pin 7 is the LCD RESET pin; pins 19, 21, 23, and 24 are channels for transmitting serial peripheral interface signals, pin 19 is the SPI0 MOSI pin, pin 21 is the SPI0 MISO pin, pin 23 is the SPI0 SCLK pin, and pin 24 is the SPI0 CE pin; pins 8 and 10 are channels for transmitting one of the asynchronous receiver and transmitter interface signals, pin 8 is the UARTA TX pin, and pin 10 is the UARTA RX pin.

[0065] It should be noted that the general input and output interface also reserves multiple pins as GPIO spare pins ( Figure 5 It can be used as an expansion function that requires a GPIO interface during chip debugging.

[0066] It should be noted that Figure 5 The universal input and output interface shown in FIG. 1 also includes conventional peripheral circuits that enable the interface to realize its own functions. The conventional peripheral circuits are Figure 5 It is not reflected in the text and will not be described here.

[0067] Figure 6 It is a schematic diagram of a serial peripheral interface signal amplifying circuit provided by an embodiment of the utility model.

[0068] Alternatively, if Figure 6 As shown, the interface mainboard 22 also includes a serial peripheral interface signal amplifying circuit; the serial peripheral interface signal amplifying circuit is arranged between the universal input and output interface and the combination interface circuit.

[0069] Specifically, the serial peripheral interface signal amplification circuit is arranged between the general input and output interface and the combination interface circuit, see Figure 3 , 5 , 6, in Figure 5 In the universal input and output interface circuit, the 2×20Pin interface pins 19, 21, 23, and 24 are respectively connected to Figure 6 The pins 4, 5, 3, and 2 of the serial peripheral interface signal amplifier chip U5 are connected. Figure 6 The pins 7, 8, 9, and 10 of the serial peripheral interface signal amplifier chip U5 shown in FIG. Figure 3Pins 25, 26, 24, and 23 of the combined interface circuit shown are connected, pin 1 of U5 is connected to the power supply VCC_3V3, pins 2, 3, 4, and 5 of U5 are connected to the power supply VCC_3V3 through resistors R5, R6, R7, and R8 respectively, pin 11 of U5 is connected to the SPI control signal input terminal SPI_REF, pins 7, 8, 9, and 10 of U5 are connected to the SPI control signal input terminal SPI_REF through resistors R12, R11, R10, and R9 respectively, and pin 6 of U5 is grounded GND0.

[0070] The serial peripheral interface signal amplifying circuit is used to amplify the preset debugging signal suitable for the serial peripheral interface transmitted through the universal input and output interface circuit, and then transmit the amplified preset debugging signal to the chip under test 30 through the serial peripheral interface in the combination interface circuit to debug the chip under test 30.

[0071] Figure 7 It is a schematic diagram of an asynchronous receiver / transmitter interface signal amplifying circuit provided by an embodiment of the utility model.

[0072] Alternatively, if Figure 7 As shown, the interface main board 22 also includes an asynchronous receiver / transmitter interface signal amplifying circuit; the asynchronous receiver / transmitter interface signal amplifying circuit is arranged between the signal conversion circuit and the combined interface circuit.

[0073] Specifically, the asynchronous receiver-transmitter interface signal amplifying circuit is arranged between the signal conversion circuit and the combined interface circuit, see Figure 3 , 4 , 7, in Figure 4 In the signal conversion circuit, the pins 39 and 40 of the signal conversion chip U1 are respectively connected to Figure 7 The pins 3 and 2 of the asynchronous receiver / transmitter interface signal amplifier chip U6 are connected. Figure 7 The pins 9 and 10 of the asynchronous receiver / transmitter interface signal amplifier chip U6 shown in FIG. Figure 3 Pins 30 and 29 of the combined interface circuit shown are connected, pins 1 and 12 of the asynchronous transceiver interface signal amplifier chip U6 are connected to the power supply VCC_5V, and pin 6 of the asynchronous transceiver interface signal amplifier chip U6 is grounded GND0.

[0074] The asynchronous receiver-transmitter interface signal amplifying circuit is used to amplify a preset debugging signal suitable for the asynchronous receiver-transmitter interface transmitted through the second universal serial bus interface, and then transmit the amplified preset debugging signal to the chip under test 30 through the asynchronous receiver-transmitter interface in the combined interface circuit to debug the chip under test 30.

[0075] It should be noted that Figure 7The asynchronous receiver-transmitter interface signal amplifying circuit shown in FIG. 1 also includes a conventional peripheral circuit that enables the asynchronous receiver-transmitter interface signal amplifying chip U6 to realize its own functions. The conventional peripheral circuit is Figure 7 It is not reflected in the text and will not be described here.

[0076] Figure 8 It is a schematic diagram of an integrated circuit bus interface expansion circuit provided by an embodiment of the utility model.

[0077] Alternatively, if Figure 8 As shown, the interface mainboard 22 also includes an integrated circuit bus interface expansion circuit; the integrated circuit bus interface expansion circuit is arranged between the universal input and output interface and the combination interface circuit.

[0078] Specifically, the integrated circuit bus interface expansion circuit is arranged between the universal input and output interface and the combination interface circuit, and the multi-channel expansion of the integrated circuit bus interface is realized through the integrated circuit bus interface expansion chip U7. For example, see Figure 8 The integrated circuit bus interface expansion chip U7 can use the TCA9548A chip to achieve 5-way expansion of the integrated circuit bus interface.

[0079] See also Figure 3 , 5 , 8, in Figure 5 In the universal input and output interface of the 2×20Pin, the interface pins 3, 5, and 7 are respectively Figure 8 Pins 20, 19, and 24 of the integrated circuit bus interface expansion chip U7 are connected, and then the first integrated circuit bus interface is expanded through pins 1 and 2 of the integrated circuit bus interface expansion chip U7, the second integrated circuit bus interface is expanded through pins 3 and 4, the second integrated circuit bus interface is expanded through pins 3 and 4, the third integrated circuit bus interface is expanded through pins 5 and 6, the fourth integrated circuit bus interface is expanded through pins 7 and 8, and the fifth integrated circuit bus interface is expanded through pins 10 and 11.

[0080] Among them, pin 1 of the integrated circuit bus interface expansion chip U7 is the I2C0 SDA pin, pin 2 is the I2C0 SCL pin, pin 3 is the I2C1 SDA pin, pin 4 is the I2C1 SCL pin, pin 5 is the I2C2 SDA pin, pin 6 is the I2C2SCL pin, pin 7 is the I2C3 SDA pin, pin 8 is the I2C3 SCL pin, pin 10 is the I2C4 SDA pin, and pin 11 is the I2C4 SCL pin.

[0081] See also Figure 8, the pins 1, 2, 3, 4, 5, 6, 7, 8, 10, 11 of the integrated circuit bus interface expansion chip U7 are also connected to the power supply VCC_3V3 through resistors R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, respectively, and the pins 19, 20, 24 are connected to the power supply VCC_3V3 through resistors R28, R27, R26, respectively. Figure 5 In the universal input and output interface, the interface pins 5, 3, and 7 of the 2×20Pin are connected, and the pins 19, 20, and 24 are also connected to the power supply VCC_3V3 through resistors R15, R14, and R13 respectively, and the pins 19, 20, and 24 are also connected to the ground GND0 through capacitors C5, C4, and C3 respectively.

[0082] See also Figure 8 Pins 18, 22, and 21 of the integrated circuit bus interface expansion chip U7 are all connected to the power supply VCC_3V3, and pins 9, 23, 25, 26, 27, 28, and 29 are all grounded GND0.

[0083] It should be noted that Figure 8 The integrated circuit bus interface expansion circuit shown in FIG. 1 also includes a conventional peripheral circuit that enables the integrated circuit bus interface expansion chip U7 to realize its own functions. The conventional peripheral circuit is Figure 8 It is not reflected in the text and will not be described here.

[0084] Optionally, the interface main board 22 also includes a dip switch; the dip switch is used to switch the signal transmission channel between the control main board 21 and the interface main board 22, wherein the signal transmission channel includes the transmission of a preset debugging signal through a signal conversion circuit, and the transmission of a preset debugging signal through a universal input and output interface.

[0085] Optionally, the control main board 21 is a Raspberry Pi board, and the chip to be tested 30 is a chip for processing computing tasks in artificial intelligence (AI) applications.

[0086] In the embodiment of the utility model, a hardware solution of Raspberry Pi plus a self-developed interface mainboard is used, and preset debugging signals matching the instruction set architecture of the chip to be tested are set in the host computer, which greatly reduces the equipment procurement cost of chip R&D users, improves the versatility of the debugging system, shortens the development and maintenance cycle, and significantly improves the debugging efficiency.

[0087] In the description of the embodiments of the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0088] Finally, it should be noted that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention is described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A debugging system, characterized in that: The debugging system includes a host computer and a debugging device; the debugging device includes a control mainboard and an interface mainboard; The host computer is electrically connected to the control mainboard; The interface mainboard includes a joint test working group interface circuit and a combination interface circuit, wherein the joint test working group interface circuit includes a joint test working group interface, and the combination interface circuit includes two asynchronous receiver and transmitter interfaces, five integrated circuit bus interfaces, and one serial peripheral interface; the interface mainboard is used to connect chips to be tested with different test interfaces; The host computer uses the interface mainboard to send a preset debugging signal to the connected chip under test through the control mainboard to debug the chip under test, wherein the preset debugging signal is determined by the instruction set architecture of the chip under test.

2. The debugging system according to claim 1, characterized in that: The interface mainboard also includes a first universal serial bus interface; The host computer and the control main board are connected to each other through the first universal serial bus interface, or the host computer and the control main board are connected to each other through Ethernet.

3. The debugging system according to claim 2, characterized in that: The interface mainboard also includes a signal conversion circuit; the signal conversion circuit includes a second universal serial bus interface, a signal conversion chip and a level conversion chip; The control mainboard is connected to the signal conversion chip via the second universal serial bus interface; The signal conversion chip is used to convert the preset debugging signal transmitted from the control mainboard into a signal transmittable by the joint test working group interface or the asynchronous receiver-transmitter interface; The level conversion chip is used to amplify the preset debugging signal transmittable by the joint test working group interface.

4. The debugging system according to claim 3, characterized in that: The interface mainboard also includes a universal input and output interface, and the universal input and output interface is provided with a preset number of pins; The universal input and output interface is used to realize the transmission of the preset debugging signal between the control main board and the interface main board.

5. The debugging system according to claim 2, characterized in that: The debugging device also includes a switching switch; the switching switch is used to switch the communication connection mode between the host computer and the control mainboard, wherein the communication connection mode includes realizing communication connection through the first universal serial bus interface and realizing communication connection through Ethernet.

6. The debugging system according to claim 4, characterized in that: The interface mainboard also includes a serial peripheral interface signal amplification circuit; The serial peripheral interface signal amplifying circuit is arranged between the universal input and output interface and the combined interface circuit.

7. The debugging system according to claim 4, characterized in that: The interface mainboard also includes an asynchronous receiver / transmitter interface signal amplification circuit; The asynchronous receiver-transmitter interface signal amplifying circuit is arranged between the signal conversion circuit and the combined interface circuit.

8. The debugging system according to claim 4, characterized in that: The interface mainboard also includes an integrated circuit bus interface expansion circuit; The integrated circuit bus interface expansion circuit is arranged between the universal input and output interface and the combination interface circuit.

9. The debugging system according to claim 4, characterized in that: The interface mainboard also includes a DIP switch; The dip switch is used to switch the signal transmission channel between the control main board and the interface main board, wherein the signal transmission channel includes the transmission of the preset debugging signal through the signal conversion circuit, and the transmission of the preset debugging signal through the universal input and output interface.

10. The debugging system according to claim 1, characterized in that: The control main board is a Raspberry Pi board, and the chip to be tested is a chip used to process computing tasks in artificial intelligence applications.

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