Semiconductor structure

Abstract

A semiconductor structure includes an integrated circuit chip having a device region and a peripheral region. The first integrated circuit chip includes a substrate; a device layer on the substrate; an interconnect structure on the device layer; a nitride layer on the first portion of the interconnect structure in the peripheral region; and an oxide layer on the second portion of the interconnect structure in the device region. An upper surface of the oxide layer is substantially coplanar with an upper surface of the nitride layer. The semiconductor structure also includes a second integrated circuit chip on the oxide layer.

Description

Technical Field

[0001] The embodiments of the utility model relate to a semiconductor structure, and more particularly to a bonded integrated circuit chip. Background Art

[0002] As semiconductor technology advances, the demand for higher storage capacity, faster processing systems, higher performance, and lower costs increases. To meet these demands, the semiconductor industry continues to reduce the size of semiconductor devices such as metal oxide semiconductor field effect transistors, fin field effect transistors, and all-around gate field effect transistors in integrated circuit chips. In order to further reduce the two-dimensional footprint of semiconductor devices, integrated circuit chips are stacked together to form a three-dimensional integrated circuit. The reduction in size also increases the complexity of the manufacturing method of the three-dimensional integrated circuit. Utility Model Content

[0003] The purpose of the present invention is to provide a semiconductor structure to solve at least one of the above problems.

[0004] In some embodiments, a semiconductor structure includes an integrated circuit chip having a device region and a peripheral region. The first integrated circuit chip includes a substrate; a device layer located on the substrate; an interconnect structure located on the device layer; a nitride layer located on a first portion of the interconnect structure in the peripheral region; and an oxide layer located on a second portion of the interconnect structure in the device region. An upper surface of the oxide layer is substantially coplanar with an upper surface of the nitride layer. The semiconductor structure also includes a second integrated circuit chip located on the oxide layer.

[0005] According to one embodiment of the present invention, a first portion of the nitride layer is located on an upper surface of the interconnect structure, and a second portion of the nitride layer is located on sidewalls of the interconnect structure, the device layer, and the substrate.

[0006] According to one embodiment of the present invention, the nitride layer extends from the edge of the substrate toward the center of the substrate by a distance of 5 mm to 10 mm.

[0007] According to one embodiment of the present invention, another nitride layer is further included, which is directly located on a portion of the substrate in the peripheral region and on a sidewall of the substrate.

[0008] According to one embodiment of the present invention, an upper surface of the further nitride layer is substantially coplanar with an upper surface of a portion of the substrate in the device region.

[0009] According to one embodiment of the present invention, another nitride layer is further included, which is directly located on a portion of the device layer in the peripheral region and on a sidewall of the device layer.

[0010] According to one embodiment of the present invention, an upper surface of the other nitride layer is substantially coplanar with an upper surface of a portion of the device layer in the device region.

[0011] According to one embodiment of the present invention, another nitride layer is further included, which is directly located on a portion of the interconnect structure in the peripheral region and on a sidewall of the interconnect structure.

[0012] According to one embodiment of the present invention, an upper surface of the further nitride layer is substantially coplanar with an upper surface of a portion of the interconnect structure in the device region.

[0013] According to one embodiment of the present invention, the surface height variation from the center to the edge of the oxide layer is 1 nm to 30 nm. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1A is an isometric view of a three-dimensional integrated circuit in some embodiments.

[0015] Figures 1B to 1E Different cross-sectional views of a three-dimensional integrated circuit with a grinding stop layer in some embodiments.

[0016] Figure 2 The present invention is a flow chart of a method for manufacturing a three-dimensional integrated circuit with a grinding stop layer in some embodiments.

[0017] Figures 3 to 7 sectional views of a three-dimensional integrated circuit with a polishing stop layer at various stages of the fabrication process in some embodiments.

[0018] Figure 8 The present invention is a flow chart of a method for manufacturing another three-dimensional integrated circuit with a grinding stop layer in some embodiments.

[0019] Figures 9 to 16 FIG. 4 is a cross-sectional view of another three-dimensional integrated circuit with a polishing stop layer at various stages of the fabrication process in some embodiments.

[0020] The reference numerals are as follows:

[0021] AA: Section Line

[0022] D1: Distance

[0023] M1, M2, M3: internal connection layer

[0024] T1, T2: thickness

[0025] 100: Three-dimensional integrated circuit

[0026] 101A: First integrated circuit chip

[0027] 101B: Second integrated circuit chip

[0028] 102A: Installation area

[0029] 102Ae,112e:Edge

[0030] 102B: Peripheral area

[0031] 104:Substrate

[0032] 104s: Sidewall

[0033] 104t,112a,114At,114Bt,114Ct,128t,132t: Upper surface

[0034] 106: Device layer

[0035] 106A, 106B: Field Effect Transistor

[0036] 108:Through hole layer

[0037] 110:Internal connection structure

[0038] 110td,110tp: Upper surface

[0039] 112: Bonding layer

[0040] 112p: Edge

[0041] 114A, 114B, 114C, 114D, 114E: Grinding stop layer

[0042] 116: Fin structure

[0043] 118: Source / drain region

[0044] 120: Gate structure

[0045] 120A: Interface layer

[0046] 120B: High dielectric constant gate dielectric layer

[0047] 120C: work function metal layer

[0048] 120D: Gate metal filling layer

[0049] 122: Gate spacer

[0050] 124,134A,134B,140: Etch stop layer

[0051] 126A, 126B, 136, 142: Interlayer dielectric layer

[0052] 128: Contact structure

[0053] 128A: Silicide layer

[0054] 128B:Contact plug

[0055] 130: Shallow Trench Isolation Area

[0056] 132: Isolation Structure

[0057] 138:Through hole

[0058] 144: Conductive circuit

[0059] 146: Conductive via

[0060] 200,800:Method

[0061] 205,210,215,220,805,810,815,820,825,830: Steps 512,1032,1328: Layers

[0062] 932: Groove

[0063] 1228: Contact opening DETAILED DESCRIPTION

[0064] The following content is described in detail with the accompanying drawings to facilitate understanding of the embodiments of the present utility model. The following content is described with the accompanying drawings to illustrate exemplary embodiments. In the accompanying drawings, similar reference numerals generally represent identical, functionally similar and / or structurally similar units.

[0065] The following content provides different embodiments or examples that can implement different structures of the utility model. The following specific components and arrangement embodiments are used to simplify the content of the utility model and are not intended to limit the utility model. For example, the description of forming a first component on a second component includes an embodiment in which the two are in direct contact, or an embodiment in which the two are separated by other additional components but not in direct contact. In addition, multiple examples of the utility model may repeatedly use the same number for simplicity, but the elements with the same number in multiple embodiments and / or settings do not necessarily have the same corresponding relationship.

[0066] Spatially relative terms such as "below," "beneath," "below," "above," "upper," or similar terms may be used to simplify the description of the relative relationship of one element to another element in a diagram. Spatially relative terms may be extended to elements used in other orientations, not limited to the orientation shown. Elements may also be rotated 90 degrees or other angles, so directional terms are only used to describe the orientation shown in the diagram.

[0067] It is worth noting that the embodiments described in the following contents as "an embodiment", "an exemplary embodiment", "exemplary", or similar terms may include specific features, structures, or characteristics, but each embodiment may not necessarily include specific features, structures, or characteristics. In addition, these terms do not necessarily refer to the same embodiment. In addition, when specific features, structures, or characteristics are described in conjunction with an embodiment, whether or not explicitly stated, a person skilled in the art can implement these features, structures, or characteristics in conjunction with other embodiments.

[0068] It should be understood that the purpose of the words or terms herein is for explanation rather than limitation, and thus those skilled in the art may interpret the words or terms of the following description based on the description herein.

[0069] In some embodiments, the terms "approximately" and "substantially" refer to a given value that varies within 5% (e.g., a value of ±1%, ±2%, ±3%, ±4%, or ±5%). These values ​​are used for example only and are not intended to limit the embodiments of the present invention. The terms "approximately" and "substantially" may refer to a percentage of a value as interpreted by a person skilled in the art based on the context of the present invention.

[0070] The fin structures described herein may be patterned by any suitable method. For example, the fin structures may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Generally, double patterning or multiple patterning processes combine photolithography with self-alignment processes to produce patterns with a pitch that is less than the pitch of patterns obtained using a single direct photolithography process. For example, one embodiment forms a sacrificial layer on a substrate and patterns the sacrificial layer using a photolithography process. A self-alignment process is used to form spacers along the sides of the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fin structures.

[0071] An integrated circuit chip may include a collection of layers of different functions, such as interconnects, power distribution networks, logic chips, memory chips, radio frequency chips, and the like. A three-dimensional integrated circuit is a non-monolithic vertical structure developed based on an integrated circuit chip, and may include two to eight two-dimensional integrated circuit chips stacked on each other and bonded to each other via a bonding layer. The bonding reliability of a three-dimensional integrated circuit may depend on the surface profile of the bonding layer and / or the substantially flat surface area size of the bonding layer. As the size of the integrated circuit chip decreases, the challenge of forming a substantially flat bonding layer in the reduced surface area of ​​the bonding layer increases.

[0072] In order to solve the above problems, the embodiments of the present invention provide a grinding stop layer in an integrated circuit chip, and form the grinding stop layer to form a bonding layer, which has a substantially flat surface profile from the center to the edge of the bonding layer and / or minimized surface height variation (e.g., about 1 nm to about 30 nm). The grinding stop layer can avoid or minimize the edge roll-off of the bonding layer near the edge and / or the edge of the device region in the integrated circuit chip, eliminate or minimize the surface height variation from the center to the edge of the bonding layer, and increase the substantially flat surface area size of the bonding layer. Increasing the substantially flat surface area size can increase the bonding area of ​​the integrated circuit chip and improve the bonding interface between the stacked integrated circuit chips in the three-dimensional integrated circuit, thereby improving the bonding reliability of the three-dimensional integrated circuit.

[0073] In some embodiments, the bonding layer formed by the grinding stop layer has a surface height variation of about 1 nm to about 30 nm from the center to the edge of the bonding layer. In some embodiments, before forming the bonding layer in the device area of ​​the integrated circuit chip, a grinding stop layer can be formed in the peripheral area of ​​the integrated circuit chip. The material included in the grinding stop layer has a higher grinding resistance than the material of the bonding layer. The grinding stop layer with high grinding resistance can avoid or minimize the collapse of the bonding layer at the edge and / or near the edge of the device area during a grinding process such as a chemical mechanical grinding process. The edge collapse of the bonding layer may come from the higher concentration of grinding stress at the edge and / or near the edge of the device area (compared with the center of the device area). The edge collapse of the bonding layer may also come from the uneven surface of the lower layer formed in the peripheral area of ​​the bonding layer. The uneven surface of the lower layer may come from the lower layer being formed on the oblique surface in the peripheral area of ​​the substrate of the integrated circuit chip.

[0074] Figure 1A FIG. 1 is an isometric view of a three-dimensional integrated circuit 100 in some embodiments. Figures 1B to 1E In some embodiments, the three-dimensional integrated circuit 100 is arranged along Figure 1A Different cross-sectional views of section line AA. Figures 1B to 1E A cross-sectional view of a three-dimensional integrated circuit 100 is shown having additional structures not shown in FIG. Figure 1A To simplify Figure 1A The contents of elements with the same reference numerals are interchangeable with each other unless otherwise specified.

[0075] like Figures 1A to 1E In some embodiments shown, the 3D integrated circuit 100 may include a first integrated circuit chip 101A, and a second integrated circuit chip 101B stacked on top of the first integrated circuit chip 101A. Although the 3D integrated circuit 100 shown in the drawings has two integrated circuit chips, the 3D integrated circuit 100 may have any number of integrated circuit chips.

[0076] like Figure 1A and Figure 1B In some embodiments shown, the first integrated circuit chip 101A may include (i) a device region 102A (also referred to as a functional region) and (ii) a peripheral region 102B adjacent to and surrounding the device region 102A. Figure 1B The peripheral region 102B on one side of the device region 102A is shown, and the peripheral region 102B surrounding the device region 102A is not shown to simplify the drawing. As described in detail below, the device region 102A of some embodiments may include electrically active devices and structures, and the peripheral region 102B may include electrically inactive layers. In some embodiments, the peripheral region 102B does not include electrically active devices and structures. In some embodiments, the distance D1 extending from the edge of the substrate 104 of the first integrated circuit chip 101A toward the center of the substrate 104 may be about 5 nm to about 10 nm.

[0077] In some embodiments, the first integrated circuit chip 101A may include (i) a substrate 104; (ii) a device layer 106 located on the substrate 104; (iii) a via layer 108 located on the device layer 106; (iv) an interconnect structure 110 located on the via layer 108; (v) a bonding layer 112 (also considered as a passivation layer) located on the interconnect structure 110; and (vi) a grinding stop layer 114A located on the interconnect structure 110. The first integrated circuit chip 101A may include other elements located between the interconnect structure 110 and the bonding layer 112, such as a conductive pad located on the interconnect structure 110, a polymer layer located on the conductive pad, a conductive via located on the conductive pad, and a stress buffer layer located on the polymer layer, which are not shown in the figure to simplify the drawings. In some embodiments, the structure in the device layer 106 may be considered as a front-end process structure in the following content. In some embodiments, the structure in the via layer 108 may be considered as a mid-stage process structure in the following content. In some embodiments, the structures in the interconnect structure 110 may be considered as back-end-of-line structures in the following description.

[0078] In some embodiments, the substrate 104 may be a semiconductor material such as silicon, germanium, silicon germanium, a silicon-on-insulator structure, or a combination thereof. In addition, the substrate 104 may be doped with p-type dopants (such as boron, indium, aluminum, or gallium) or n-type dopants (such as phosphorus or arsenic).

[0079] like Figure 1A and Figure 1BIn some embodiments shown, the bonding layer 112 may include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, or metal oxide. The bonding layer 112 may be located on a portion of the interconnect structure 110 in the device region 102A, and may be configured to mechanically bond the first integrated circuit chip 101A to the second integrated circuit chip 101B. The bonding reliability between the first integrated circuit chip 101A and the second integrated circuit chip 101B may depend on the surface profile and / or substantially flat surface area size of the upper surface of the bonding layer 112. The greater the surface flatness of the upper surface 112a and / or the larger the substantially flat surface area size of the upper surface 112a, the higher the bonding reliability between the first integrated circuit chip 101A and the second integrated circuit chip 101B.

[0080] By using the grinding stop layer 114A, the bonding layer 112 having a substantially flat upper surface 112a can be formed, and the edge 102Ae of the device region 102A and / or the edge portion 112p of the bonding layer 112 near the edge 102Ae have no edge collapse or have negligible edge collapse, such as Figure 1B As shown. The upper surface 112a may be substantially coplanar with the upper surface 114At of the grinding stop layer 114A, and the thickness T1 of the bonding layer 112 may be substantially equal to the thickness T2 of the grinding stop layer 114A. The grinding stop layer 114A may eliminate or minimize the difference in grinding rate between the edge portion 112p of the bonding layer 112 and other portions (such as the central portion) (caused by the grinding stress with a higher concentration at the edge 102Ae and / or near the edge 102Ae), such as with Figures 2 to 6 The following content is described. The surface height variation (also considered as morphology variation) between the edge 112e and the center (not shown) of the bonding layer 112 can be less than about 30nm (e.g., about 1nm to about 30nm). Within this range of surface height variation, all of the surface area or about 100% of the surface area of ​​the upper surface 112a can be effectively used to bond the first integrated circuit chip 101A and the second integrated circuit chip 101B. Therefore, by using the grinding stop layer 114A, a larger surface area of ​​the bonding layer 112 can be effectively used to bond the integrated circuit chips (compared to the bonding layer formed without the grinding stop layer 114A).

[0081] In some embodiments, the grinding stop layer 114A may include an oxide layer (such as silicon oxide), a nitride layer (such as silicon nitride), a carbide layer (such as silicon carbide or silicon carbonitride), a metal layer (such as tantalum), a metal oxide layer (such as tungsten oxide), a metal nitride layer (such as tantalum nitride or titanium nitride), or a polysilicon layer. In some embodiments, the material included in the grinding stop layer 114A may be different from the material of the bonding layer 112. The grinding resistance of the material of the grinding stop layer 114A to the grinding chemical is higher than the grinding resistance of the material of the bonding layer 112 to the grinding chemical. The material of the grinding stop layer 114A has a higher grinding resistance, and a lower grinding rate can be achieved during a grinding process such as chemical mechanical polishing (compared with the material of the bonding layer 112), such as with Figures 2 to 6 As described below. In some embodiments, if the bonding layer 112 comprises silicon oxide or metal oxide, the grinding stop layer 114A may comprise silicon nitride (or vice versa) to achieve a high grinding selectivity between the bonding layer 112 and the grinding stop layer 114A. In some embodiments, if the bonding layer 112 comprises silicon oxide, the grinding stop layer 114A may comprise polysilicon to achieve a high grinding selectivity between the bonding layer 112 and the grinding stop layer 114A.

[0082] In some embodiments, the grinding stop layer 114A may include a horizontal portion and a vertical portion. The horizontal portion of the grinding stop layer 114A is located on all upper surfaces of the portion of the interconnect structure 110 in the peripheral region 102B. The vertical portion of the grinding stop layer 114A may be directly located on the outer sidewall of the first integrated circuit chip 101A (which may include the outer sidewall of the portion of the interconnect structure 110, the via layer 108, the device layer 106, and the substrate 104 in the peripheral region 102B). In some embodiments, the horizontal portion of the grinding stop layer 114A may extend to the edge 102Ae of the device region 102A, and the distance D1 from the edge of the substrate 104 toward the center of the substrate 104 is about 5 nm to about 10 nm, so as to achieve the surface profile of the bonding layer 112 as described above.

[0083] like Figure 1A and Figure 1B In some embodiments shown, device layer 106 may include fin field effect transistors 106A and 106B (also referred to as field effect transistors). The content of field effect transistor 106A may be used for field effect transistor 106B unless otherwise stated. Although device layer 106 in the figure has two field effect transistors, device layer 106 may have any number of field effect transistors. Device layer 106 may include other active and / or passive devices, which are not shown to simplify the figure. In some embodiments, in addition to (or in place of field effect transistors 106A and 106B), device layer 106 may include fully wrapped gate field effect transistors and / or metal oxide semiconductor field effect transistors, but are not shown to simplify the figure.

[0084] In some embodiments, the field effect transistor 106A may include (i) a fin structure 116 on the substrate 104; (ii) a source / drain region 118 on the fin structure 116; (iii) a gate structure 120 on the fin structure 116; (iv) a gate spacer 122 on the sidewalls of the gate structure 120; (v) an etch stop layer 124 on the source / drain region 118; (vi) interlayer dielectric layers 126A and 126B on the etch stop layer 124; (vii) a contact structure 128 on the source / drain region 118; (viii) a shallow trench isolation region 130 on the substrate 104; and (ix) an isolation structure 132 in the fin structure 116. The source / drain region 118 may be considered as a source or a drain, either alone or together, depending on the context.

[0085] In some embodiments, the fin structure 116 may include a material similar to the substrate 104 and may extend along the X-axis. The fin structure 116 may have an elongated side extending along the X-axis. In some embodiments, the gate spacer 122, the etch stop layer 124, the interlayer dielectric layers 126A and 126B, the shallow trench isolation region 130, and the isolation structure 132 may include an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride, silicon carbon oxynitride, or silicon germanium oxide.

[0086] For an n-type field effect transistor 106A, the source / drain regions 118 may each include an epitaxially grown semiconductor material (e.g., silicon) and an n-type dopant (e.g., phosphorus or other suitable n-type dopant). For a p-type field effect transistor 106A, the source / drain regions 118 may each include an epitaxially grown semiconductor material (e.g., silicon or silicon germanium) and a p-type dopant (e.g., boron or other suitable p-type dopant).

[0087] In some embodiments, the gate structures 120 may each include (i) an oxide interface layer 120A; (ii) a high-k gate dielectric layer 120B located on the interface layer 120A; (iii) a work function metal layer 120C located on the high-k gate dielectric layer 120B; and (iv) a gate metal filling layer 120D located on the work function metal layer 120C. In some embodiments, the interface layer 120A may include silicon oxide, silicon germanium oxide, or germanium oxide. In some embodiments, the high-k gate dielectric layer 120B may include a high-k dielectric material such as hafnium oxide, titanium oxide, hafnium zirconium oxide, tantalum oxide, hafnium silicate, zirconium oxide, or zirconium silicate. In some embodiments, the work function metal layer 120C may include titanium aluminum, titanium aluminum carbide, tantalum aluminum, tantalum aluminum carbide, aluminum-doped titanium, aluminum-doped titanium nitride, aluminum-doped tantalum, aluminum-doped tantalum nitride, or other suitable aluminum-based materials for the n-type field effect transistor 106A. In some embodiments, the work function metal layer 120C may include a titanium-based nitride or alloy substantially free of aluminum (e.g., free of aluminum), such as titanium nitride, titanium silicon nitride, titanium-gold alloy, titanium-copper alloy, tantalum nitride, tantalum silicon nitride, tantalum-gold alloy, or tantalum-copper alloy for use in a p-type field effect transistor 106A. In some embodiments, the gate metal filling layer 120D may include a suitable conductive material, such as tungsten, titanium, silver, ruthenium, molybdenum, copper, cobalt, aluminum, iridium, nickel, a metal alloy, or a combination thereof.

[0088] In some embodiments, the contact structures 128 may each include (i) a silicide layer 128A on the source / drain regions 118; and (ii) a contact plug 128B on the silicide layer 128A. In some embodiments, the silicide layer 128A may each include titanium silicide, tantalum silicide, molybdenum silicide, zirconium silicide, hafnium silicide, scandium silicide, yttrium silicide, terbium silicide, lutetium silicide, erbium silicide, ytterbium silicide, europium silicide, thorium silicide, other suitable metal silicide materials, or combinations thereof for the n-type field effect transistor 106A. In some embodiments, the silicide layers 128A may each include nickel silicide, cobalt silicide, manganese silicide, tungsten silicide, iron silicide, rhodium silicide, palladium silicide, ruthenium silicide, platinum silicide, iridium silicide, osmium silicide, other suitable metal silicide materials, or combinations thereof for the p-type field effect transistor 106A. In some embodiments, the contact plugs 128B may each include a low-resistance (e.g., resistance less than or equal to about 50 μΩ-cm) conductive material, such as cobalt, tungsten, ruthenium, aluminum, molybdenum, iridium, nickel, osmium, rhodium, other suitable low-resistance conductive materials, or combinations thereof.

[0089] The isolation structure 132 is an electrically inactive structure that is not electrically coupled to any power source and is electrically isolated from other structures of the field effect transistor 106A. In some embodiments, the upper surface of the isolation structure 132 may be substantially coplanar with the upper surface of the fin structure 116. In some embodiments, the isolation structure 132 may have a tapered structure, with the width of the upper surface being greater than the width of the lower surface.

[0090] In some embodiments, the via layer 108 may include (i) etch stop layers 134A and 134B; (ii) an interlayer dielectric layer 136 located between the etch stop layers 134A and 134B; and (iii) a via 138 located in a portion of the interlayer dielectric layer 136 and the etch stop layers 134A and 134B in the device region 102A. The via layer 108 does not have a via located in the peripheral region 102B. In some embodiments, the via layer 108 may electrically connect the field effect transistor 106A to the interconnect structure 110 via the via 138. In some embodiments, the via 138 may include a conductive material such as ruthenium, cobalt, nickel, aluminum, molybdenum, tungsten, iridium, osmium, copper, or palladium. The interlayer dielectric layer 136 and the etch stop layers 134A and 134B may include an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride, or silicon germanium oxide.

[0091] In some embodiments, the interconnect structure 110 may be located on the via layer 108. In some embodiments, the interconnect structure 110 may include interconnect layers M1 to M3. Figure 1B Three interconnect layers M1 to M3 are shown, and the interconnect structure 110 may have any number of interconnect layers. The interconnect layers M1 to M3 may each include an etch stop layer 140 and an interlayer dielectric layer 142. The etch stop layer 140 may include a dielectric material such as aluminum oxide, silicon carbonitride, or silicon oxycarbide, and the dielectric constant thereof may be about 4 to about 10.

[0092] In some embodiments, the interlayer dielectric layer 142 may include a dielectric material with a low dielectric constant or an extremely low dielectric constant, whose dielectric constant is lower than the dielectric constant of silicon oxide (e.g., between about 2 and about 3.7). The dielectric material with a low dielectric constant or an extremely low dielectric constant may reduce the parasitic capacitance between the interconnect layers M1 to M3. In some embodiments, the dielectric material with a low dielectric constant or an extremely low dielectric constant may include silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride, or silicon oxycarbide. In some embodiments, the interlayer dielectric layer 142 may include one or more layers of insulating carbon material (having a low dielectric constant such as less than about 2, such as about 1 to about 1.9). In some embodiments, the one or more insulating carbon materials may include one or more fluorinated graphene layers (whose dielectric constant may be about 1 to about 1.5), or may include one or more graphene oxide layers.

[0093] In some embodiments, the interconnect structure 110 in the device area 102A may include electrically active (i) conductive lines 144 located in the interconnects M1 and M3, and (ii) conductive vias 146 located in the interconnect layer M2. The conductive lines 144 and the conductive vias 146 may be electrically connected to a power source and / or an active device. The layout of the conductive lines 144 and the conductive vias 146 is only for illustration and not for limitation of the embodiments of the present invention, and other layout variations of the conductive lines 144 and the conductive vias 146 also fall within the scope of the embodiments of the present invention. The wiring between the field effect transistor 106A in the device area 102A and a portion of the interconnect structure 110 (which may also be considered an electrical connection) is only for illustration and not for limitation of the embodiments of the present invention. The wiring between the field effect transistor 106A and the interconnect layers M1 to M3 may not be shown. Figure 1B in the cross-sectional view.

[0094] The conductive lines 144 may be respectively located in the interlayer dielectric layer 142, the conductive vias 146 may be respectively located in the interlayer dielectric layer 142, and the paired etch stop layers 140 may be located on the upper and lower surfaces of the corresponding interlayer dielectric layer 142. The conductive vias 146 provide electrical connection between the conductive lines 144 of adjacent interconnect layers. In some embodiments, the conductive lines 144 may include conductive materials such as copper, ruthenium, cobalt, molybdenum, carbon nanotubes, graphene layers, or any other suitable conductive materials. In some embodiments, the conductive vias 146 may include conductive materials such as copper, ruthenium, cobalt, molybdenum, copper alloys (such as copper ruthenium, copper aluminum, or copper manganese), carbon nanotubes, graphene layers, or any other suitable conductive materials. In some embodiments, the conductive lines 144 and the conductive vias 146 may include metal pads (not shown) and the conductive materials may be located thereon. The metal liner may include metal (such as tantalum, cobalt, or other suitable metals) or metal nitride (such as titanium nitride, tantalum nitride, or other suitable metal nitrides). The conductive lines 144 and conductive vias 146 of one or more interconnect layers M1 to M3 may be single damascene structures or dual damascene structures.

[0095] Figure 1C For three-dimensional integrated circuits along Figure 1A Different cross-sectional views of section line AA. Figure 1A , Figure 1B and Figure 1C The contents of the components with the same reference numerals in the figure can be mutually connected unless otherwise specified. In some embodiments, the substrate 104 may have an inclined edge, so the upper surface 104t of the substrate 104 in the peripheral area 102B may have a non-planar (such as an arc-shaped) surface profile, which is different from Figure 1BDue to the uneven surface profile of the upper surface 104t in the peripheral region 102B, the device layer 106, the via layer 108 and / or the portion of the interconnect structure 110 formed on the upper surface 104t may continue the uneven topography of the upper surface 104t and have an uneven upper surface profile. The bonding layer 112 formed by the grinding stop layer 114A can prevent the bonding layer 112 from having an uneven upper surface profile similar to the underlying layer. The edge portion 112p of the bonding layer 112 has no edge collapse or has negligible edge collapse, and the bonding layer 112 has a substantially flat upper surface 112a, such as with Figure 1B Explain the above content.

[0096] Figure 1D Display of 3D integrated circuit devices along Figure 1A Different cross-sectional views of section line AA. Figures 1A to 1D The contents of the components with the same reference numerals in the drawings are interchangeable unless otherwise specified. In some embodiments, the first integrated circuit chip 101A may further include a grinding stop layer 114B located on the upper surface 104t and the sidewall 104s of the substrate 104. The grinding stop layer 114B can prevent the substrate 104 below from being ground during the grinding process performed to form the isolation structure 132, such as with Figures 8 to 11 As described in detail below. Without the polishing stop layer 114B, the upper surface 104t may be exposed to the polishing process and may remove a portion of the substrate 104 in the peripheral region 102B. Damage to the substrate 104 may negatively affect the surface profile of the upper layers. In some embodiments, the polishing stop layer 114B and the upper surface of the isolation structure 132 may be substantially coplanar with each other.

[0097] In some embodiments, the grinding stop layer 114B may include an oxide layer such as silicon oxide, a nitride layer such as silicon nitride, a carbide layer such as silicon carbide or silicon carbonitride, or a polysilicon layer. In some embodiments, the material of the grinding stop layer 114B may be different from the material of the isolation structure 132. The grinding resistance of the material of the grinding stop layer 114B to the grinding chemical is higher than the grinding resistance of the material of the isolation structure 132 to the grinding chemical. The material of the grinding stop layer 114B has a higher grinding resistance, and a lower grinding rate (compared with the material of the isolation structure 132) can be achieved during a grinding process such as chemical mechanical polishing, such as with Figures 8 to 11As described below. In some embodiments, if the isolation structure 132 comprises silicon oxide, the grinding stop layer 114B may comprise silicon nitride (or vice versa) to achieve a high grinding selectivity between the isolation structure 132 and the grinding stop layer 114B. In some embodiments, if the isolation structure 132 comprises silicon oxide, the grinding stop layer 114B may comprise polysilicon to achieve a high grinding selectivity between the isolation structure 132 and the grinding stop layer 114B. In some embodiments, the materials of the grinding stop layers 114A and 114B may be similar or different from each other.

[0098] and Figure 1B The grinding stop layer 114A is different. Figure 1D The grinding stop layer 114A in FIG. 1 is not directly located on the outer side wall of the substrate 104, but directly located on the outer side wall of the grinding stop layer 114B. Figure 1B and Figure 1C The etching stop layer 124 is different. Figure 1D The etch stop layer 124 in FIG. 1 is not directly located on the portion of the substrate 104 in the peripheral region 102B, but is directly located on the upper surface of the grinding stop layer 114B.

[0099] Figure 1E For three-dimensional integrated circuits along Figure 1A Different cross-sectional views of section line AA. Figures 1A to 1E Components with the same reference numerals in the figure may be interchangeable unless otherwise specified. In some embodiments, the first integrated circuit chip 101A may further include grinding stop layers 114C, 114D, and 114E. The grinding stop layer 114C may be directly located on the upper surface portion of the interlayer dielectric layer 126B in the peripheral area 102B, and on the outer sidewalls of the interlayer dielectric layers 126A and 126B, the etch stop layer 124, and the grinding stop layer 114B. The grinding stop layer 114D may be directly located on the upper surface portion of the interlayer dielectric layer 142 of the interconnect layer M1 in the peripheral area 102B, and on the outer sidewalls of the interlayer dielectric layers 142 and 136 and the grinding stop layer 114C. The grinding stop layer 114E may be directly located on the upper surface portion of the interlayer dielectric layer 142 of the interconnect layer M3 in the peripheral region 102B, and on the outer sidewalls of the interlayer dielectric layer 142 of the interconnect layers M2 and M3 and the grinding stop layer 114D. Similar to the grinding stop layer 114B, the grinding stop layers 114C, 114D, and 114E may avoid grinding the underlying layers. The grinding stop layer 114C may avoid grinding the underlying interlayer dielectric layer 126B when forming the contact plug 128B, such as with Figure 8 and Figure 12 to Figure 14 Similarly, the grinding stop layers 114D and 114E can prevent the grinding of the underlying interlayer dielectric layer 142 when forming the conductive line 144. Figure 8 and Figures 12 to 15 Details are given below.

[0100] In some embodiments, the grinding stop layer 114C may include an oxide layer such as silicon oxide, a metal oxide layer such as tungsten oxide, or a metal nitride layer such as tantalum nitride. In some embodiments, the material of the grinding stop layer 114C may be different from the material of the contact plug 128B. The grinding resistance of the material of the grinding stop layer 114C to grinding chemicals is higher than the grinding resistance of the material of the contact plug 128B to grinding chemicals. The higher grinding resistance of the material of the grinding stop layer 114C can achieve a lower grinding rate (compared to the material of the contact plug 128B) during a grinding process such as chemical mechanical polishing, such as with Figure 8 and Figures 12 to 14 As described below. In some embodiments, if the contact plug 128B includes tungsten, the polishing stop layer 114C may include silicon oxide or tungsten nitride to achieve a high polishing selectivity between the contact plug 128B and the polishing stop layer 114C. In some embodiments, if the contact plug 128B includes cobalt, the polishing stop layer 114C may include silicon oxide or tantalum nitride to achieve a high polishing selectivity between the contact plug 128B and the polishing stop layer 114C.

[0101] In some embodiments, the grinding stop layers 114D and 114E may include an oxide layer (e.g., silicon oxide), a metal layer (e.g., tantalum), or a metal nitride layer (e.g., tantalum nitride). In some embodiments, the material of the grinding stop layers 114D and 114E is different from the material of the conductive circuit 144. The grinding resistance of the material of the grinding stop layers 114D and 114E to grinding chemicals may be higher than the grinding resistance of the material of the conductive circuit 144 to grinding chemicals. The higher grinding resistance of the material of the grinding stop layers 114D and 114E may achieve a lower grinding rate (compared to the material of the conductive circuit) during a grinding process such as chemical mechanical polishing, such as with Figure 8 and Figures 12 to 15 As described below. In some embodiments, if the conductive line 144 includes copper, the polishing stop layers 114D and 114E may include silicon oxide, tantalum, or tantalum nitride to achieve high polishing selectivity between the conductive line 144 and the polishing stop layers 114D and 114E. In some embodiments, the materials of the polishing stop layers 114D and 114E may be similar to each other and different from the materials of the polishing stop layers 114A, 114B, and / or 114C.

[0102] and Figure 1B The grinding stop layer 114A is different. Figure 1E The grinding stop layer 114A in FIG. 1 is not directly located on the outer side wall of the substrate 104, but is directly located on the outer side wall of the grinding stop layer 114E. Figures 1B to 1D The etching stop layer 134A is different. Figure 1EThe etching stop layer 134A in the peripheral region 102B is not directly located on the portion of the interlayer dielectric layer 126B in the peripheral region 102B, but is directly located on the upper surface of the grinding stop layer 114C; (ii) Figures 1B to 1D The etching stop layer 140 of the interconnect layer M1 is different. Figure 1E The etch stop layer 140 is not directly located on the portion of the interlayer dielectric layer 142 in the peripheral region 102B, but is directly located on the upper surface of the grinding stop layer 114D; and (iii) Figures 1B to 1D The etching stop layer 140 of the interconnect layer M3 is different. Figure 1E The etch stop layer 140 is not directly located on the portion of the interlayer dielectric layer 142 in the peripheral region 102B, but is directly located on the upper surface of the grinding stop layer 114E.

[0103] Figure 2 For some embodiments, the production Figure 1B 1 is a flow chart of a method 200 of a cross-sectional view of a three-dimensional integrated circuit 100. For illustration purposes, Figure 2 The steps shown will be paired with Figures 3 to 7 A process for fabricating a three-dimensional integrated circuit 100 is shown. Figures 3 to 7 In some embodiments, the three-dimensional integrated circuit 100 is fabricated at various stages along the Figure 1A 2. The steps may be performed in different orders, or some steps may not be performed, depending on the specific application. It is worth noting that method 200 does not produce a complete three-dimensional integrated circuit 100. In summary, it should be understood that additional processes may be provided before, during, and after method 200, and some other processes are only briefly described here. Figures 3 to 7 Zhongyu Figure 1A and Figure 1B The components with the same reference numerals have been described above.

[0104] like Figure 2 In step 205, a device layer is formed on a substrate of an integrated circuit chip. Figure 3 For example, a device layer 106 is formed on a substrate 104 of a first integrated circuit chip 101A. The method for forming the device layer 106 may include sequentially performing the following steps: (i) forming a fin structure 116 on the substrate 104; (ii) forming a source / drain region 118 on the fin structure 116; (iii) forming a gate structure 120 on the fin structure 116; (iv) depositing an etch stop layer 124 on the source / drain region 118; (v) depositing an interlayer dielectric layer 126A on the etch stop layer 124; (vi) depositing an interlayer dielectric layer 126B on the interlayer dielectric layer 126A; and (vii) forming a contact structure 128 on the source / drain region 118 and in the interlayer dielectric layers 126A and 126B.

[0105] like Figure 2 In step 210, a through hole is formed on the device layer. Figure 3 For example, a via layer 108 is formed on the device layer 106. The method of forming the device layer 106 may include sequentially performing the following steps: (i) depositing an etch stop layer 134A on the device layer 106; (ii) depositing an interlayer dielectric layer 136 on the etch stop layer 134A; and (iii) forming a via 138 on the contact structure 128 and in the etch stop layer 134A and the interlayer dielectric layer 136.

[0106] like Figure 2 As shown in step 215, an internal connection structure is formed on the through hole layer. Figure 3 For example, the interconnect structure 110 is formed on the via layer 108. The method of forming the interconnect structure 110 may include forming the conductive line 144 and the conductive via 146 in a single damascene process or a dual damascene process.

[0107] like Figure 2 As shown in step 220, a bonding layer is formed on the interconnect structure. Figures 4 to 7 For example, a bonding layer 112 is formed on a portion of the interconnect structure 110 in the device region 102A. The method for forming the bonding layer 112 may include sequentially performing the following steps: (i) masking (not shown) an upper surface portion 110td of the interconnect structure 110 in the device region 102A; (ii) depositing a grinding stop layer 114A on an upper surface portion 110tp of the interconnect structure in the peripheral region 102B, and on the outer sidewalls of the interconnect structure 110, the via layer 108, the device layer 106, and the substrate 104, as shown in FIG. Figure 4 (iii) depositing a layer 512 of the material of the bonding layer 112 on a portion of the interconnect structure 110 in the device region 102A and on an upper surface 114At of the grinding stop layer 114A, such as Figure 5 (iv) performing a chemical mechanical polishing process on the layer 512 to form a bonding layer 112, the upper surface 112a of which is substantially coplanar with the upper surface 114At of the grinding stop layer 114A, such as Figure 6 and (v) performing a bonding process on the bonding layer 112 to bond the second integrated circuit chip 101B to the first integrated circuit chip 101A to form Figure 1B In some embodiments, before bonding the second integrated circuit chip 101B to the first integrated circuit chip 101A, the grinding stop layer 114A may be removed to form a Figure 7 structure.

[0108] In some embodiments, the method of masking the upper surface portion 110td may be to pattern a mask layer (such as a photoresist layer, not shown) directly on the upper surface portion 110td, or to place a metal plate (not shown) on the upper surface portion 110td. Figure 3 The metal plate is disposed on and spaced a distance from the structure so as to cover the upper surface portion 110td when the grinding stop layer 114A is deposited. In some embodiments, the metal plate can be part of a deposition chamber used to deposit the grinding stop layer 114A.

[0109] In some embodiments, the grinding stop layer 114A may have a thickness T2 of about 100 nm to about 5 microns, and the deposition method thereof may be a plasma-enhanced chemical vapor deposition process, wherein the deposition temperature using the precursor and the reactive gas may be about 100° C. to about 400° C., and the RF power may be about 10 MHz to about 15 MHz. In some embodiments, the grinding stop layer 114A has a larger thickness (e.g., about 100 nm to about 20 microns), and the deposition method thereof may be a physical vapor deposition process (e.g., sputtering, electron beam evaporation, plasma-enhanced ion plating, or the like), wherein the deposition temperature using the precursor and the reactive gas may be about room temperature to about 400° C. The deposition temperature is maintained at less than or equal to 400° C. to avoid thermal damage to the layers and / or structures in the interconnect structure 110, the via layer 108, and / or the device layer 106. In some embodiments, the reactive gas used in the plasma-enhanced chemical vapor deposition process may be silane, disilane, methane, ethylene, ammonia, or a mixture of nitrogen and hydrogen. In some embodiments, the reaction gases used in the physical vapor deposition process may be argon, nitrogen, and hydrogen.

[0110] In some embodiments, the polishing chemistry used in the chemical mechanical polishing process has a higher polishing selectivity for the material of the layer 512 than for the material of the polishing stop layer 114A, so that the polishing rate on the layer 512 is higher than the polishing rate on the upper surface 114At of the polishing stop layer 114A. Due to the lower polishing rate on the polishing stop layer 114A, when the portion of the layer 512 on the polishing stop layer 114A is removed to expose the upper surface 114At to the polishing process, the amount of the polishing stop layer 114A removed can be negligible, and no edge collapse area is formed on the polishing stop layer 114A. In this way, when the portion of the layer 512 in the device area 102A is polished to a thickness T1 (substantially equal to the thickness T2), the polishing stop layer 114A can prevent the edge portion 112p from being over-polished to less than the thickness T1 and avoid causing a collapse in the edge portion 112p.

[0111] Figure 8 For some embodiments, the production Figure 1E A flow chart of a method 800 used in a cross-sectional view of a three-dimensional integrated circuit 100. For illustration purposes, Figure 8 The steps shown will be paired with Figures 9 to 16 A process for fabricating a three-dimensional integrated circuit 100 is shown. Figures 9 to 16 In some embodiments, the three-dimensional integrated circuit 100 is fabricated at various stages along the Figure 1A 800. The steps may be performed in a different order, or some steps may not be performed, depending on the specific application. It is worth noting that method 800 does not produce a complete three-dimensional integrated circuit 100. In summary, it should be understood that additional processes may be provided before, during, and after method 800, and some other processes are only briefly described here. Figures 9 to 16 Zhongyu Figures 1A to 1E The components with the same reference numerals have been described above.

[0112] like Figure 8 In step 805, a first grinding stop layer is deposited on the substrate of the integrated circuit chip. Fig. 9 For example, a grinding stop layer 114B is deposited on a portion of the substrate 104 in the peripheral region 102B. The deposition process used for the grinding stop layer 114B can be similar to that described above for the grinding stop layer 114A, except that the deposition temperature used can be greater than the deposition temperature used for the grinding stop layer 114A. In some embodiments, the deposition temperature used for the grinding stop layer 114B can be about 100° C. to about 600° C. The manner in which the portion of the substrate 104 in the device region 102A is masked before depositing the grinding stop layer 114B can be similar to that described above for the grinding stop layer 114A. Figure 2 The contents described in step 220 are similar.

[0113] like Figure 8 In step 810, a fin structure is formed on a substrate, and an isolation structure is formed in the fin structure. Figures 9 to 11 For example, a fin structure 116 is formed on a portion of the substrate 104 in the device region 102A, and an isolation structure 132 is formed in the fin structure 116. The method of forming the isolation structure 132 may include sequentially performing the following steps: (i) forming a trench 932 in the fin structure 116, such as Fig. 9 (ii) depositing a layer 1032 of the material of the isolation structure 132 in the trench 932 and on the fin structure 116 and the grinding stop layer 114B, such as Fig.10 and (iii) performing a chemical mechanical polishing process on the layer 1032 to form an isolation structure 132, the upper surface 132t of which is substantially coplanar with the upper surface 114Bt of the polishing stop layer 114B, such as Fig.11 shown.

[0114] In some embodiments, the polishing selectivity of the polishing chemical used in the chemical mechanical polishing process to the material of the layer 1032 is greater than the polishing selectivity to the material of the polishing stop layer 114B, so that the polishing rate on the layer 1032 is higher than the polishing rate on the upper surface 114Bt of the polishing stop layer 114B. Since the polishing rate on the polishing stop layer 114B is lower, when removing the portion of the layer 1032 on the polishing stop layer 114B to expose the upper surface 114Bt to the polishing process, the removal amount of the polishing stop layer 114B can be ignored. In this way, the polishing stop layer 114B can avoid polishing the upper surface 104t of the portion of the substrate 104 in the peripheral area 102B during the chemical mechanical polishing process.

[0115] like Figure 8 In step 815, source / drain regions and gate structures are formed on the fin structure. Fig.12 For example, source / drain regions 118 and gate structure 120 may be formed on fin structure 116. After forming the source / drain regions, etch stop layer 124 and interlayer dielectric layers 126A and 126B may be formed.

[0116] like Figure 8 In step 820, a contact structure is formed on the source / drain region. Figures 12 to 14 For example, a contact structure 128 is formed on the source / drain region 118 to pass through the etch stop layer 124 and the interlayer dielectric layers 126A and 126B. The method of forming the contact structure 128 may include sequentially performing the following steps: (i) depositing a grinding stop layer 114C on a portion of the interlayer dielectric layer 126B in the peripheral region 102B, and on the outer sidewalls of the interlayer dielectric layers 126A and 126B, the etch stop layer 124, and the grinding stop layer 114B, such as Fig.12 (ii) forming a contact opening 1228 in the interlayer dielectric layer 126A and 126B and the etch stop layer 124, such as Fig.12 (iii) forming a silicide layer 128A on the source / drain region 118 in the contact opening 1228, such as Fig.13 (iv) depositing a layer 1328 of a material of the contact plug 128B in the contact opening 1228 and on the interlayer dielectric layer 126B and the grinding stop layer 114C, such as Fig.13 and (v) performing a chemical mechanical polishing process on the layer 1328 to form a contact plug 128B, whose upper surface 128t is substantially coplanar with the upper surface 114Ct of the polishing stop layer 114C, such as Fig.14 shown.

[0117] The deposition process used for grinding stop layer 114C may be similar to that described above for grinding stop layer 114A, except that the deposition temperature used may be higher than that used for grinding stop layer 114A. In some embodiments, the deposition temperature used for grinding stop layer 114C may be about 100° C. to about 550° C. Prior to depositing grinding stop layer 114C, portions of interlayer dielectric layer 126B in device region 102A may be masked, and the masking method may be the same as for grinding stop layer 114A. Figure 2 The method described in step 220 of is similar. In some embodiments, the polishing chemical used in the chemical mechanical polishing process has a higher polishing selectivity for the material of the layer 1328 than for the material of the polishing stop layer 114C, so that the polishing rate on the layer 1328 is higher than the polishing rate on the upper surface 114Ct of the polishing stop layer 114C. Since the polishing rate of the polishing stop layer 114C is lower, the removal amount of the polishing stop layer 114C can be ignored when removing the portion of the layer 1328 on the polishing stop layer 114C and exposing the upper surface 114Ct to the polishing process. In this way, the polishing stop layer 114C can avoid polishing a portion of the upper surface and the underlying layer of the interlayer dielectric layer 126B in the peripheral area 102B during the chemical mechanical polishing process.

[0118] like Figure 8 In step 825, an internal connection structure is formed on the contact structure. Fig.15 For example, the interconnect structure 110 having the grinding stop layers 114D and 114E is formed on the contact structure 128. In some embodiments, the formation method of the conductive lines 144 in the interconnect layers M1 and M3 and the grinding stop layers 114D and 114E can be combined with Figure 8 The formation of the contact structure 128 is similar to the formation of step 820 described in the previous embodiment. Before forming the interconnect structure 110 , the via layer 108 may be formed on the contact structure 128 .

[0119] like Figure 8 In step 830, a bonding layer and a second polishing stop layer are formed on the interconnect structure. Fig.16 For example, the bonding layer 112 and the grinding stop layer 114A are formed on the interconnect structure 110. The method of forming the bonding layer 112 and the grinding stop layer 114A can be combined with Figure 2 The method described in step 220 is similar.

[0120] In some embodiments, Figure 1CThe method for forming the structure may adopt method 800 with additional steps such as (i) removing the grinding stop layer 114B after forming the isolation structure 132 in step 810 and before forming the source / drain region 118 in step 815; (ii) removing the grinding stop layer 114C after forming the contact structure 128 in step 820 and before forming the through-hole layer 108 in step 825; and (iii) removing the grinding stop layer 114D after forming the conductive line 144 in step 825 and before forming the grinding stop layer 114A in step 830.

[0121] In some embodiments, Figure 1D The method for forming the structure may adopt method 800 with additional steps such as (i) removing the grinding stop layer 114C after forming the contact structure 128 in step 820 and before forming the through-hole layer 108 in step 825; and (ii) removing the grinding stop layers 114D and 114E after forming the conductive line 144 in step 825 and before forming the grinding stop layer 114A in step 830.

[0122] The present invention provides a grinding stop layer (such as grinding stop layer 114A) in an integrated circuit chip (such as the first integrated circuit chip 101A), and a method for forming the grinding stop layer to form a bonding layer (such as bonding layer 112), which has a substantially flat surface profile and / or minimized surface height variation (such as about 1 nm to about 30 nm) from the center to the edge of the bonding layer. The grinding stop layer can avoid or minimize the edge collapse of the bonding layer at the edge and / or near the edge of the device region in the integrated circuit chip, so as to eliminate or minimize the surface height variation from the center to the edge of the bonding layer, and increase the substantially flat surface area size of the bonding layer. Increasing the substantially flat surface area size can increase the bonding area of ​​the integrated circuit chip, and improve the bonding interface between the stacked integrated circuit chips (such as the first integrated circuit chip 101A and the second integrated circuit chip 101B) in the three-dimensional integrated circuit (such as the three-dimensional integrated circuit 100), thereby improving the bonding reliability of the three-dimensional integrated circuit.

[0123] In some embodiments, the bonding layer formed by the grinding stop layer has a surface height variation from the center to the edge of the bonding layer of about 1 nm to about 30 nm. In some embodiments, before forming the bonding layer in the device area (such as the device area 102A) of the integrated circuit chip, a grinding stop layer may be formed in the peripheral area (such as the peripheral area 102B) of the integrated circuit chip. The material contained in the grinding stop layer may have higher grinding resistance than the material of the bonding layer. The grinding stop layer with high grinding resistance can avoid or minimize the collapse of the bonding layer at the edge and / or near the edge of the device area during a grinding process such as a chemical mechanical grinding process. The edge collapse of the bonding layer may come from the grinding stress concentration at the edge and / or near the edge of the device area, which is higher than the grinding stress concentration at the center of the device area. The edge collapse of the bonding layer may also come from the bonding layer being formed on the uneven surface of the lower layer in the peripheral area. The uneven surface of the lower layer may come from the lower layer being formed on the oblique surface in the peripheral area of ​​the substrate of the integrated circuit chip.

[0124] In some embodiments, a method for forming a semiconductor structure includes forming a first integrated circuit chip, which includes a device region and a peripheral region. The steps of forming the first integrated circuit chip include forming a device layer on a substrate; forming an interconnect structure on the device layer; depositing a first dielectric layer on a first portion of the interconnect structure in the peripheral region; depositing a second dielectric layer on the first dielectric layer and a second portion of the interconnect structure in the device region; and performing a grinding process on the second dielectric layer so that the upper surface of the second dielectric layer is substantially coplanar with the upper surface of the first dielectric layer. The method also includes performing a bonding process on the second dielectric layer to bond the second integrated circuit chip to the first integrated circuit chip.

[0125] In some embodiments, the method further includes masking a second portion of the interconnect structure before depositing the first dielectric layer.

[0126] In some embodiments, depositing the first dielectric layer includes depositing a nitride layer.

[0127] In some embodiments, depositing the second dielectric layer includes depositing an oxide layer.

[0128] In some embodiments, the step of performing the polishing process includes performing chemical mechanical polishing with a polishing chemical, and the polishing selectivity of the chemical polishing agent to the second dielectric layer is greater than the polishing selectivity to the first dielectric layer.

[0129] In some embodiments, the method further includes removing the first dielectric layer before performing the bonding process.

[0130] In some embodiments, the step of depositing the first dielectric layer includes depositing a first portion of the first dielectric layer on an upper surface of the interconnect structure; and depositing a second portion of the first dielectric layer on a sidewall of the interconnect structure.

[0131] In some embodiments, the step of depositing the first dielectric layer includes depositing a portion of the first dielectric layer on the interconnect structure, the device layer, and the sidewalls of the substrate.

[0132] In some embodiments, depositing a first dielectric layer includes depositing a nitride layer at a deposition temperature less than about 400°C.

[0133] In some embodiments, the method further includes depositing a third dielectric layer on a portion of the substrate in the peripheral region before forming the device layer on the substrate.

[0134] In some embodiments, a method for forming a semiconductor structure includes depositing a first dielectric layer on a first portion of a substrate in a peripheral area of ​​an integrated circuit chip; forming a fin structure on a second portion of the substrate in a device area of ​​the integrated circuit chip; forming a groove in the fin structure; depositing a second dielectric layer in the groove and on the upper surface of the fin structure and the first dielectric layer; performing a grinding process on the second dielectric layer so that the upper surface of the second dielectric layer and the first dielectric layer are substantially coplanar; forming a source / drain region on the fin structure; and depositing an interlayer dielectric layer on the source / drain region and the first dielectric layer.

[0135] In some embodiments, the step of depositing the first dielectric layer includes depositing a first portion of the first dielectric layer on the upper surface of the substrate; and depositing a second portion of the first dielectric layer on the sidewall of the substrate.

[0136] In some embodiments, depositing the first dielectric layer includes depositing a nitride layer.

[0137] In some embodiments, depositing the second dielectric layer includes depositing an oxide layer.

[0138] In some embodiments, the method further includes depositing a third dielectric layer on a portion of the interlayer dielectric layer in the peripheral region.

[0139] In some embodiments, the method further includes forming a contact structure on the source / drain region, and an upper surface of the contact structure is substantially coplanar with an upper surface of the third dielectric layer.

[0140] In some embodiments, a semiconductor structure includes an integrated circuit chip having a device region and a peripheral region. The first integrated circuit chip includes a substrate; a device layer located on the substrate; an interconnect structure located on the device layer; a nitride layer located on a first portion of the interconnect structure in the peripheral region; and an oxide layer located on a second portion of the interconnect structure in the device region. An upper surface of the oxide layer is substantially coplanar with an upper surface of the nitride layer. The semiconductor structure also includes a second integrated circuit chip located on the oxide layer.

[0141] In some embodiments, a first portion of the nitride layer is located on an upper surface of the interconnect structure, and a second portion of the nitride layer is located on sidewalls of the interconnect structure, the device layer, and the substrate.

[0142] In some embodiments, the nitride layer extends a distance from the edge of the substrate toward the center of the substrate of about 5 mm to about 10 mm.

[0143] In some embodiments, the semiconductor structure further includes another nitride layer directly over the portion of the substrate in the peripheral region and over the sidewalls of the substrate.

[0144] In some embodiments, an upper surface of the further nitride layer is substantially coplanar with an upper surface of a portion of the substrate in the device region.

[0145] In some embodiments, the semiconductor structure further includes another nitride layer directly over a portion of the device layer in the peripheral region and over a sidewall of the device layer.

[0146] In some embodiments, an upper surface of the further nitride layer is substantially coplanar with an upper surface of a portion of the device layer in the device region.

[0147] In some embodiments, the semiconductor structure further includes another nitride layer directly over a portion of the interconnect structure in the peripheral region and over a sidewall of the interconnect structure.

[0148] In some embodiments, an upper surface of the further nitride layer is substantially coplanar with an upper surface of a portion of the interconnect structure in the device region.

[0149] In some embodiments, the surface height variation from the center to the edge of the oxide layer is about 1 nm to about 30 nm.

[0150] The features of the above embodiments are helpful for those skilled in the art to understand the present invention. Those skilled in the art should understand that the present invention can be used as a basis to design and change other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the spirit and scope of the present invention, and can be changed, replaced, or modified without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor structure, characterized in that: include: A first integrated circuit chip includes a device region and a peripheral region, wherein the first integrated circuit chip includes: a substrate; a device layer located on the substrate; an internal connection structure located on the device layer; a nitride layer located on the first portion of the interconnect structure in the peripheral region; and an oxide layer located on the second portion of the interconnect structure in the device region, wherein an upper surface of the oxide layer is coplanar with an upper surface of the nitride layer; and A second integrated circuit chip is located on the oxide layer.

2. The semiconductor structure according to claim 1, wherein: A first portion of the nitride layer is located on an upper surface of the interconnect structure, and The second portion of the nitride layer is located on the inner connection structure, the device layer, and the side wall of the substrate.

3. The semiconductor structure according to claim 1, wherein: The nitride layer extends from the edge of the substrate toward the center of the substrate by a distance of 5 mm to 10 mm.

4. The semiconductor structure according to claim 1, wherein: Also included is another nitride layer directly over a portion of the substrate in the peripheral region and over a sidewall of the substrate.

5. The semiconductor structure according to claim 4, characterized in that An upper surface of the further nitride layer is coplanar with an upper surface of a portion of the substrate in the device region.

6. The semiconductor structure according to claim 1, wherein: Also included is another nitride layer directly over a portion of the device layer in the peripheral region and over a sidewall of the device layer.

7. The semiconductor structure according to claim 6, wherein: An upper surface of the further nitride layer is coplanar with an upper surface of a portion of the device layer in the device region.

8. The semiconductor structure according to claim 1, wherein: Also included is another nitride layer directly over a portion of the interconnect structure in the peripheral region and over a sidewall of the interconnect structure.

9. The semiconductor structure according to claim 8, characterized in that The upper surface of the further nitride layer is coplanar with an upper surface of a portion of the interconnect structure in the device region.

10. The semiconductor structure according to claim 1, wherein: The surface height of the oxide layer varies from 1 nm to 30 nm from the center to the edge.

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