GPMC bus-to-Ethernet realization circuit

Abstract

The utility model discloses a GPMC bus-to-Ethernet realization circuit, which comprises a CPU, the CPU is connected with an FPGA through a GPMC bus interface, the FPGA is connected with a PHY chip through an I / O interface, and the PHY chip is connected with external equipment through an Ethernet connector. According to the utility model, a plurality of network ports can be expanded by using the GPMC bus, and information interaction with a plurality of external devices can be carried out by using the FPGA.

Description

Technical Field

[0001] The utility model belongs to the technical field of communication, and more specifically, relates to a GPMC (General Purpose Memory Controller) bus to Ethernet implementation circuit. Background Art

[0002] Usually, the CPU has only one or two network interfaces, resulting in a one-to-one connection between devices. In some usage scenarios, this will greatly limit the working efficiency of the device. The GPMC bus can simultaneously realize a set of buses to switch to multiple Ethernet interfaces, act on multiple devices at the same time, and complete the joint collaboration, control, conversion, etc. of multiple devices, thereby greatly improving work efficiency. Utility Model Content

[0003] The purpose of the utility model is to overcome the deficiencies in the prior art and to provide a GPMC bus to Ethernet implementation circuit, which can expand multiple network ports using the GPMC bus and can simultaneously connect to multiple external devices and exchange information using FPGA.

[0004] The purpose of the utility model is achieved through the following technical solutions.

[0005] The utility model discloses a GPMC bus to Ethernet realization circuit, comprising a CPU, wherein the CPU is connected to an FPGA via a GPMC bus interface, the FPGA is connected to a PHY chip via an I / O interface, and the PHY chip is connected to an external device via an Ethernet connector.

[0006] Furthermore, the FPGA is connected to at least one PHY chip, and each of the PHY chips is connected to an external device via an Ethernet connector.

[0007] Furthermore, the GPMC bus interface of the CPU includes 8 chip select enable signal line interfaces, 1 clock signal line interface, 26 address line interfaces, and 10 control line interfaces, the 26 address line interfaces include a high 10-bit address line interface and a low 16-bit address line interface, the low 16-bit address line interface is multiplexed with the data line interface, the 10 control line interfaces include 4 wait signal reception start interfaces, 1 address valid control enable interface, 1 output enable interface, 1 read-write total control enable interface, 1 low eight-bit read-write enable interface, 1 high eight-bit read-write enable interface, and 1 write protection enable interface, each interface of the GPMC bus interface is respectively connected to the I / O port of the FPGA, and the FPGA allocates an independent I / O port to each interface of the GPMC bus interface.

[0008] Furthermore, the FPGA is respectively connected to the MAC of each PHY chip, and the 15 address line interfaces, 16 data line interfaces, 4 nByte enable interfaces and address enable interface, reset interface, interrupt control interface, data channel selection interface, address channel selection interface, in-place output interface, high write and low read interface, asynchronous working status indication interface, readback control interface, and clock signal interface of each PHY chip MAC are respectively connected to the I / O ports of the FPGA, and the FPGA allocates an I / O port to each of the above interfaces, and the address line interfaces and data line interfaces of all PHY chips reuse the same I / O port of the FPGA.

[0009] The Ethernet connector adopts an RJ45 socket, and each RJ45 socket is connected between a PHY chip and an external device.

[0010] Furthermore, the differential data line port portion of each of the RJ45 sockets is connected to its corresponding external device, wherein the differential signal positive sending port, the differential signal negative sending port, the differential signal positive receiving port, and the differential signal negative receiving port are respectively connected to the positive output port, negative output port, positive input port, and negative input port of the corresponding PHY chip, and the green light negative pole and yellow light negative pole of each of the RJ45 sockets are respectively connected to the green light control port and yellow light control port of its corresponding PHY chip.

[0011] Compared with the prior art, the beneficial effects brought about by the technical solution of the utility model are:

[0012] The utility model connects the GPMC bus port part of the CPU to the FPGA, connects the MAC of the corresponding PHY chip through the FPGA, improves the adaptability of the GPMC, and can greatly increase the number of peripherals of the GPMC bus interface by introducing the FPGA, connects the differential data line from the PHY chip to the RJ45 socket or other connectors, and realizes the use of GPMC for communication within the system and Ethernet for communication with the outside of the system. When the control line in the GPMC bus passes through the FPGA, the FPGA transforms the state of the control line, so that the GPMC can reuse the same set of addresses and data to connect multiple PHY chips at the same time. The utility model can realize the networking and interaction of multiple devices at the same time, and has high versatility. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a principle block diagram of the utility model GPMC bus to Ethernet realization circuit.

[0014] Figure 2 The utility model is a schematic diagram of the pin connection of the GPMC bus part of the CPU.

[0015] Figure 3It is a schematic diagram of the pin wiring of the I / O part of the FPGA in the utility model.

[0016] Figure 4 It is a schematic diagram of the pin connection of the MAC part of the PHY chip in the utility model.

[0017] Figure 5 The utility model is a schematic diagram of the connection of the pins of the connection part between the PHY chip and the Ethernet connector.

[0018] Figure 6 It is a schematic diagram of RJ45 pin wiring in the utility model. DETAILED DESCRIPTION

[0019] The utility model is further described below in conjunction with the accompanying drawings.

[0020] like Figure 1 As shown, the utility model GPMC bus to Ethernet implementation circuit mainly includes a CPU, FPGA, PHY chip, Ethernet connector, external devices, etc. connected in sequence. The CPU is connected to the FPGA through the GPMC bus interface, the FPGA is connected to the PHY chip through the I / O interface, and the PHY chip is connected to the external device through the Ethernet connector. Among them, at least one PHY chip can be set, and each PHY chip can be connected to an external device through an Ethernet connector. The CPU can use AM3517, and the external device refers to various devices with reserved network interfaces such as computers, switches, and servers.

[0021] In the above circuit, if Figure 2As shown, the GPMC bus interface of the CPU includes 8 chip select enable signal line interfaces (GPMC_NCS0~GPMC_NCS7), 1 clock signal line interface (GPMC_CLK), 26 address line interfaces, and 10 control line interfaces. The 26 address line interfaces include high 10-bit address line interfaces (GPMC_A1~GPMC_A10) and low 16-bit address line interfaces (GPMC_D0~GPMC_D15). The low 16-bit address line interface is multiplexed with the data line interface. The control line interface includes 4 wait signal reception start interfaces (GPMC_WAIT0~GPMC_WAIT3), 1 address valid control enable interface (GPMC_NADV_ALE), 1 output enable interface (GPMC_NOE), 1 read-write general control enable interface (GPMC_NWE), 1 low eight-bit read-write enable interface (GPMC_NBE0_CLE), 1 high eight-bit read-write enable interface (GPMC_NBE1), and 1 write protection enable interface (GPMC_NWP). Each interface of the above GPMC bus interface is connected to some I / O ports of FPGA respectively, and FPGA allocates an independent I / O port to each interface of GPMC bus interface, see Figure 3 In addition, except for the four wait signal receiving start interfaces GPMC_WAIT0 to GPMC_WAIT3, the remaining interfaces of the GPMC bus interface of the CPU can be connected to the allocated I / O ports in the FPGA via a resistor (such as R1 to R41).

[0022] In the above circuit, the FPGA is connected to the MAC of each PHY chip respectively, such as Figure 4 As shown, each PHY chip MAC has 15 address line interfaces (A1~A15), 16 data line interfaces (D0~D15), 4 nByte enable interfaces (NBE0~NBE3, low enable), 1 address enable interface (AEN, low enable), 1 reset interface (RESET, low level reset), 1 interrupt control interface (INTR0, high interrupt), 1 data channel selection interface (NDATACS, low effective), 1 address channel selection interface (NADS, low effective), 1 The in-position output interface (NLDEV), the high write low read interface (W / NR), the asynchronous working status indication interface (ARDY), the readback control interface (NRDYRTN), and the clock signal interface (LCLK) are connected to some I / O ports of the FPGA. The FPGA allocates an I / O port to each of the above interfaces, and the address line interface (A1~A15) and data line interface (D0~D15) of all PHY chips reuse the same I / O port of the FPGA, while the other interfaces are not reused. In addition, the interrupt control interface INTR0 can also be grounded to GND through a resistor R54.

[0023] In the above circuit, the Ethernet connector can be an RJ45 socket or other connectors, each RJ45 socket is connected between a PHY chip and an external device, and the RJ45 socket can be HR911130A, etc. Figure 5 and Figure 6 As shown, the differential data line port part (MDI0_P, MDI0_M, MDI1_P, MDI1_M, MDI2_P, MDI2_M, MDI3_P, MDI3_M) of each RJ45 socket is connected to its corresponding external device, wherein the differential signal positive sending port MDI0_P, the differential signal negative sending port MDI0_M, the differential signal positive receiving port MDI1_P, and the differential signal negative receiving port MDI1_M are respectively connected to the positive output port TPO+, the negative output port TPO-, the positive input port TPI+, and the negative input port TPI- of the corresponding PHY chip, and the differential signal positive sending port MDI0_P, the differential signal negative sending port MDI0_M, the differential signal positive receiving port MDI1_P, and the differential signal negative receiving port MDI1_M are respectively connected to the 3.3V power supply via resistors R45, R46, R47, and R48. The transformer tap interface of each RJ45 socket is connected to a 3.3V power supply and a capacitor C1 to ground GND via an inductor FB2, and the shell ground port SHIELD of each RJ45 socket is connected to ground GND via an inductor FB1 and a resistor R50. The positive pole of the green light Green of each RJ45 socket is connected to a 3.3V power supply via a resistor R49, and the negative pole of the green light Green is connected to the green light control port NLEDA of its corresponding PHY chip via a resistor R51. The positive pole of the yellow light Yellow of each RJ45 socket is connected to a 3.3V power supply via a resistor R52, and the negative pole of the yellow light Yellow is connected to the yellow light control port NLEDB of its corresponding PHY chip via a resistor R53. In addition, the green light control port NLEDA and the yellow light control port NLEDB of each PHY chip can be connected to ground GND via resistors R43 and R44, respectively, and the fixed pull-down port RBIAS of each PHY chip is connected to ground GND via a resistor R42.

[0024] The utility model connects the GPMC bus port part of the CPU to the FPGA, and connects the corresponding PHY chip through the FPGA to improve the adaptability of the GPMC. The FPGA performs corresponding protocol conversion on the data of the GPMC, configures the register of the PHY chip, and puts the PHY chip into a prefabricated working state. At the same time, the FPGA has a strong data processing capability, and can process multiple tasks or multiple data streams at the same time. The use of the FPGA can effectively improve the performance and energy efficiency ratio. The FPGA can also perform digital filtering, time domain processing, spectrum analysis and other processing, which has very effective protection for the signal. By introducing the FPGA, the number of peripherals of the GPMC bus interface can be greatly increased.

[0025] The utility model connects the GPMC bus interface of the CPU to the MAC of the PHY chip through the FPGA, and after the FPGA processes the data, the register of the PHY chip is configured accordingly, so that the PHY chip is in a corresponding rate working state. The differential data line is connected from the PHY chip to the RJ45 socket or other connectors.

[0026] The CPU sends a start transmission instruction through the GPMC bus interface. The FPGA transforms the data sent by the CPU through the GPMC bus interface, and then configures the MAC of the PHY chip. At the same time, it releases the reset control signal of the PHY chip, so that the PHY chip can read and write, and use the RJ45 socket or other connectors to exchange information with external devices. The system uses GPMC for internal communication and Ethernet for external communication.

[0027] Usually, the instructions issued by the CPU using the GPMC bus interface are mixed data and address multiplexed data streams, and data and addresses are transmitted within one clock. In the FPGA, the data and address instructions are separated and then connected to the corresponding PHY chip. The data is integrated and converted through the internal protocol of the PHY chip, and converted into data packets, which interact with external devices through the Ethernet connector. When the control line in the GPMC bus passes through the FPGA, the FPGA transforms the state of the control line, allowing the GPMC to reuse the same set of addresses and data to connect multiple PHY chips at the same time.

[0028] Although the functions and working processes of the utility model are described above in conjunction with the accompanying drawings, the utility model is not limited to the above-mentioned specific functions and working processes, and the above-mentioned specific implementation methods are merely illustrative rather than restrictive. Under the enlightenment of the utility model, ordinary technicians in this field can also make many forms without departing from the scope of protection of the purpose of the utility model and the claims, which are all within the protection of the utility model.

Claims

1. A GPMC bus to Ethernet implementation circuit, including a CPU, characterized in that: The CPU is connected to the FPGA via a GPMC bus interface, the FPGA is connected to the PHY chip via an I / O interface, and the PHY chip is connected to an external device via an Ethernet connector.

2. The GPMC bus to Ethernet implementation circuit according to claim 1, characterized in that: The FPGA is connected to at least one PHY chip, and each of the PHY chips is connected to an external device via an Ethernet connector.

3. The GPMC bus to Ethernet implementation circuit according to claim 1, characterized in that: The GPMC bus interface of the CPU includes 8 chip select enable signal line interfaces, 1 clock signal line interface, 26 address line interfaces, and 10 control line interfaces. The 26 address line interfaces include a high 10-bit address line interface and a low 16-bit address line interface, and the low 16-bit address line interface is multiplexed with the data line interface. The 10 control line interfaces include 4 wait signal reception start interfaces, 1 address valid control enable interface, 1 output enable interface, 1 read-write total control enable interface, 1 low eight-bit read-write enable interface, 1 high eight-bit read-write enable interface, and 1 write protection enable interface. Each interface of the GPMC bus interface is respectively connected to the I / O port of the FPGA, and the FPGA allocates an independent I / O port to each interface of the GPMC bus interface.

4. The GPMC bus to Ethernet implementation circuit according to claim 1, characterized in that: The FPGA is respectively connected to the MAC of each PHY chip, and the 15 address line interfaces, 16 data line interfaces, 4 nByte enable interfaces and address enable interface, reset interface, interrupt control interface, data channel selection interface, address channel selection interface, in-place output interface, high write and low read interface, asynchronous working status indication interface, readback control interface, and clock signal interface of each PHY chip MAC are respectively connected to the I / O ports of the FPGA, and the FPGA allocates an I / O port to each of the above interfaces, and the address line interfaces and data line interfaces of all PHY chips reuse the same I / O port of the FPGA.

5. The GPMC bus to Ethernet implementation circuit according to claim 1, characterized in that: The Ethernet connector adopts an RJ45 socket, and each RJ45 socket is connected between a PHY chip and an external device.

6. The GPMC bus to Ethernet implementation circuit according to claim 5, characterized in that: The differential data line port portion of each RJ45 socket is connected to its corresponding external device, wherein the differential signal positive sending port, the differential signal negative sending port, the differential signal positive receiving port, and the differential signal negative receiving port are respectively connected to the positive output port, negative output port, positive input port, and negative input port of the corresponding PHY chip, and the green light negative pole and yellow light negative pole of each RJ45 socket are respectively connected to the green light control port and yellow light control port of its corresponding PHY chip.

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