Semiconductor structure

Abstract

A semiconductor structure includes a first epitaxial source / drain feature on a first protruding portion of a substrate; a second epitaxial source / drain feature on the second protruding portion of the substrate; a third epitaxial source / drain feature on the third protruding portion of the substrate; a fourth epitaxial source / drain feature on a fourth protruding portion of the substrate; and an isolation structure on the substrate. The isolation structure has a base on the top surface of the substrate and sidewall portions on sidewalls of the first, second, third, and fourth protruding portions of the substrate. The first epitaxial source / drain feature and the second epitaxial source / drain feature are not merged. The third epitaxial source / drain feature and the fourth epitaxial source / drain feature merge by breaking through sidewall portions of the isolation structure.

Description

Technical Field

[0001] The embodiment of the utility model relates to a structure, and in particular to a semiconductor structure. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Advances in semiconductor manufacturing technology have produced several generations of ICs, each with smaller and more complex circuits than the previous generation. During IC evolution, functional density (that is, the number of interconnected IC devices per chip area) has generally increased while geometry (that is, the size and / or dimensions of IC components and / or the spacing between IC components) has decreased. In general, miniaturization has been limited by the ability to lithographically define IC components with ever-decreasing geometry dimensions.

[0003] As component sizes continue to decrease, the spacing between adjacent source / drain components becomes tighter, resulting in epitaxial merging between source / drain components in different active areas. In some cases, epitaxial merging is undesirable, such as when p-type epitaxial components of different transistor devices are shorted. Merging problems can have a negative impact on yield and wafer acceptance testing (WAT) performance. One of the reasons for epitaxial merging is due to over-etching when forming source / drain trenches, which may cause the isolation structure between active areas to break or become unstable. The source / drain component may grow horizontally through the broken portion of the isolation structure, thereby merging with the adjacent source / drain component.

[0004] Thus, while existing methods of forming source / drain features are generally adequate for their intended purposes, they are not satisfactory in all respects. Utility Model Content

[0005] The purpose of the present invention is to provide a semiconductor structure to solve at least one of the above problems.

[0006] Some embodiments of the present invention provide a semiconductor structure, including: a first epitaxial source / drain (S / D) component on a first protruding portion of a substrate; a second epitaxial source / drain component on a second protruding portion of the substrate; a third epitaxial source / drain component on a third protruding portion of the substrate; a fourth epitaxial source / drain component on a fourth protruding portion of the substrate; and an isolation structure on the substrate, the isolation structure having a base and a sidewall portion, the base being on the top surface of the substrate, and the sidewall portion being on the sidewalls of the first, second, third and fourth protruding portions of the substrate, wherein the first epitaxial source / drain component and the second epitaxial source / drain component are not merged, and wherein the third epitaxial source / drain component and the fourth epitaxial source / drain component are merged by breaking through the sidewall portion of the isolation structure.

[0007] According to one embodiment of the present invention, the third epitaxial source / drain component and the fourth epitaxial source / drain component are merged at the lower portion of the third epitaxial source / drain component and the fourth epitaxial source / drain component.

[0008] According to one embodiment of the present invention, the first epitaxial source / drain component and the second epitaxial source / drain component are p-type source / drain components, and the third epitaxial source / drain component and the fourth epitaxial source / drain component are n-type source / drain components.

[0009] According to one embodiment of the present invention, a plurality of sidewall portions of the isolation structure are vertically provided between an upper portion and a lower portion of the third epitaxial source / drain component.

[0010] According to one embodiment of the present invention, a plurality of sidewall portions of the isolation structure are vertically provided between an upper portion and a lower portion of the fourth epitaxial source / drain component.

[0011] According to one embodiment of the present invention, a bottom surface of the first epitaxial source / drain component is higher than a bottom surface of the third epitaxial source / drain component.

[0012] According to one embodiment of the present invention, a bottom surface of the first epitaxial source / drain component is higher than a bottom surface of the fourth epitaxial source / drain component.

[0013] According to one embodiment of the present invention, a bottom surface of the second epitaxial source / drain component is higher than a bottom surface of the third epitaxial source / drain component.

[0014] According to one embodiment of the present invention, a bottom surface of the second epitaxial source / drain component is higher than a bottom surface of the fourth epitaxial source / drain component.

[0015] According to one embodiment of the present invention, a redistribution structure is further included on the first epitaxial source / drain component. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The following will be detailed with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale and are only used for illustration. In fact, the size of the unit may be arbitrarily enlarged or reduced to clearly show the features of the present disclosure. It should also be noted that the attached drawings only illustrate typical embodiments of the present disclosure and should not be considered as limiting the scope thereof. The present disclosure may also be applicable to other embodiments.

[0017] According to one embodiment of the present disclosure, Figure 1AA flow chart illustrating a method of forming a semiconductor structure having non-epitaxially merged source / drain features.

[0018] According to one embodiment of the present disclosure, Figure 1B A flow chart illustrating a method of patterning a hard mask and a dummy gate layer in preparation for forming a semiconductor structure having non-epitaxially merged source / drain features.

[0019] According to one embodiment of the present disclosure, Figure 2-Figure 7 Show according to Figure 1A Method of forming a semiconductor structure at an intermediate stage of fabrication and in a cross-sectional view taken along the length of an active area.

[0020] According to one embodiment of the present disclosure, Figure 8-Figure 10 A semiconductor structure is shown at an intermediate stage of fabrication, taken along a cross-sectional view of multiple source / drain regions of an active region.

[0021] According to another embodiment of the present disclosure, Fig.11 A semiconductor structure is shown at an intermediate stage in fabrication, ready to form a semiconductor structure having merged source / drain features and unmerged source / drain features.

[0022] According to another embodiment of the present disclosure, Fig.12 A semiconductor structure with merged source / drain features and unmerged source / drain features is shown, taken along multiple source / drain features.

[0023] The reference numerals are as follows:

[0024] 100: Method

[0025] 102: Operation

[0026] 104: Operation

[0027] 106: Operation

[0028] 108: Operation

[0029] 110: Operation

[0030] 112: Operation

[0031] 114: Operation

[0032] 116: Operation

[0033] 118: Operation

[0034] 200:Semiconductor structure

[0035] 202:Substrate

[0036] 203: Isolation Structure

[0037] 204: Active area

[0038] 206:Extension components

[0039] 214: Gate layer

[0040] 216: Silicon nitride layer

[0041] 218: Silicon oxide layer

[0042] 220: Hard mask layer

[0043] 222: Photoresist

[0044] 224: Spacer

[0045] 233: Etching gas

[0046] 242: Groove

[0047] 400: Loop

[0048] 110-1: Steps / Process

[0049] 110-2: Steps / Process

[0050] 110-3: Steps / Process

[0051] 110-4: Steps / Process

[0052] 110-5: Steps / Process

[0053] 110-6: Steps / Process

[0054] 110-7: Steps / Process

[0055] 202a: protruding part

[0056] 204a: semiconductor layer

[0057] 204b: semiconductor layer

[0058] 206a:S / D parts

[0059] 206b:S / D parts

[0060] 214a: Gate structure

[0061] 214b: Gate structure

[0062] 216a: Silicon nitride layer

[0063] 218a: Silicon oxide layer

[0064] 220a: Hard mask structure

[0065] 220b: Hard mask structure

[0066] 242a: Groove

[0067] 242b: Groove

[0068] t1: time

[0069] t2: time

[0070] t3: time

[0071] t4: time

[0072] w1: width

[0073] w2: width

[0074] w3: width DETAILED DESCRIPTION

[0075] The following content provides many different embodiments or examples to implement different parts of the embodiments of the present disclosure. The following describes specific examples of components and configurations to simplify the embodiments of the present disclosure. Of course, these are merely examples and are not intended to limit the embodiments of the present disclosure. For example, in the following description, it is mentioned that a first component is formed above or on a second component, which may include an embodiment in which the first component and the second component are formed in direct contact, and may also include an embodiment in which an additional component is formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the embodiments of the present disclosure may repeat component symbols and / or letters in many examples. These repetitions are for the purpose of simplification and clarity, and do not themselves represent a specific relationship between the various embodiments and / or configurations discussed.

[0076] Spatially relative terms such as "under," "below," "lower," "above," "upper," and the like may be used herein to facilitate description of the relationship between one component or feature and another component or feature in the drawings. Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations depicted in the drawings. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatially relative adjectives used therein will also be interpreted based on the turned orientation.

[0077] Furthermore, when the terms "about", "approximately" and the like are used to describe a number or a range of numbers, the terms are intended to cover values ​​that include the described number within a reasonable range, such as within + / -10% of the described number, or other values ​​understood by a person skilled in the art. For example, the term "about 5 nanometers" covers a size range from 4.5 nanometers to 5.5 nanometers.

[0078] The present disclosure relates to a semiconductor structure having a source / drain component that does not merge with other source / drain components. One of the reasons for epitaxial merging is due to over-etching when forming the source / drain trench, which may cause the isolation structure between the active areas to break or become unstable. The source / drain component may grow horizontally through the broken portion of the isolation structure, thereby merging with the adjacent source / drain component. One of the reasons for the over-etching problem is that due to the small size of the dummy gate and the hard mask, excessive global etching gas etches the source / drain region and the isolation structure when forming the source / drain trench. The present disclosure considers expanding the hard mask profile to block the excessive global etching gas. Due to the gate hard mask profile design, the source / drain trench is formed shallower and does not cause damage to the isolation structure, thereby preventing undesirable source / drain epitaxial merging.

[0079] To illustrate various aspects of the present disclosure, methods of forming semiconductor devices are discussed below. Some embodiments shown in the present disclosure are implemented with gate-all-around (GAA) field effect transistors (FETs), however the present disclosure is not limited thereto. GAA FETs refer to transistors having a gate stack (gate electrode and gate dielectric layer) surrounding the transistor channel, such as vertically stacked all-around gate horizontal nanowire or nanosheet MOSFET devices. Those skilled in the art should understand that they can use the present disclosure as a basis for designing or modifying other structures to achieve the same purposes and / or achieve the same benefits as the embodiments introduced in the present disclosure.

[0080] Figure 1A A flow chart of a method 100 for forming a semiconductor structure 200 having source / drain features that are not epitaxially merged is shown. Figure 2-Figure 7 Describing method 100, Figure 2-Figure 7 The formation of a semiconductor structure 200 is depicted at an intermediate stage of fabrication and in a cross-sectional view taken along the length of an active region 204 on a substrate 202 (or as a portion of a substrate 202). Figure 8-Figure 10 Describing method 100, Figure 8-Figure 10 The formation of the semiconductor structure 200 is depicted at an intermediate stage of fabrication and in a cross-sectional view taken along the source / drain regions of the active region 204. Figure 1A , method 100 is further decomposed at operation 110 and Figure 1B Description, according to one embodiment of the present disclosure, Figure 1B A flow chart illustrating operations 110 of patterning a hard mask and a dummy gate layer using a multiple etch process.

[0081] Reference now Figure 2, the method 100 forms an active region 204 on a substrate 202 in operation 102. The substrate 202 may be a silicon (Si) substrate or a substrate having other semiconductor materials, such as germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), or diamond. The active region 204 may be a fin-type active region protruding on the substrate 202. For a GAA FET structure (as shown), the active region 204 includes a stack of staggered first semiconductor layers 204a and second semiconductor layers 204b. The first semiconductor layer 204a has a different material composition than the second semiconductor layer 204b. For example, each first semiconductor layer 204a is formed of silicon and each second semiconductor layer 204b is formed of silicon germanium. The first semiconductor layer 204a may have the same material composition as the substrate 202. For a FinFET (fin field effect transistor) structure (not shown), the active region 204 includes a single fin-type semiconductor layer 204a or 204b on the substrate 202.

[0082] The active region 204 extends longitudinally along the x-direction. In the y-direction, there may be adjacent active regions 204 formed similarly (see Figure 8 ), and also extends longitudinally along the x-direction. Figure 8 1 shows a view of the semiconductor structure 200 at operation 102, but it is a cross-sectional view taken along the y-direction across the plurality of active regions 204. Specifically, the cross-sectional view is taken along the source / drain regions of the plurality of active regions 204. Figure 8As shown, the active regions 204 are separated from each other in the y direction by the isolation structures 203 on the substrate 202. The substrate 202 may include a protruding portion 202a passing through the isolation structure 203, and the active region 204 may extend from the top surface of the protruding portion 202a. Each protruding portion 202a is between the isolation structures 203. Therefore, the isolation structure 203 intersects with the top surface of the substrate 202 and the side surface of the protruding portion 202a. The isolation structure 203, which may be a shallow trench isolation (STI) layer, provides isolation between adjacent active regions 204, and the active region 204 may include a semiconductor stack having a first semiconductor layer 204a and a second semiconductor layer 204b. In an exemplary process, the dielectric material for the isolation structure 203 is deposited on the workpiece using chemical vapor deposition (CVD), subatmospheric CVD (SACVD), flow CVD, physical vapor deposition (PVD), spin coating and / or other suitable processes. Thereafter, the deposited dielectric material is planarized and etched back until the active region 204 rises above the isolation structure 203. The dielectric material used for the isolation structure 203 may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k (dielectric constant) dielectrics, combinations thereof, and / or other suitable materials.

[0083] refer to Figure 2 In operation 104, the method 100 forms a dummy gate layer 214 on the active area 204. The dummy gate layer 214 may be formed by any suitable deposition process. The dummy gate layer 214 may include polycrystalline silicon, amorphous silicon, or microcrystalline silicon. Figure 2 , the method 100 forms a hard mask layer 220 on the dummy gate layer 214 in operation 106. The hard mask layer 220 may include a plurality of dielectric layers (also referred to as dielectric films). The hard mask layer 220 may be formed by thermal growth, atomic layer deposition (ALD), chemical vapor deposition (CVD), high density plasma CVD (HDP-CVD), or other suitable deposition processes. In the illustrated embodiment, the hard mask layer 220 includes a silicon oxide layer 218 formed on the silicon nitride layer 216. For example, the silicon nitride layer 216 is deposited on the dummy gate layer 214, and then the silicon oxide layer 218 is deposited on the silicon nitride layer 216. In another embodiment, the silicon nitride layer 216 may be formed on the silicon oxide layer 218. In other embodiments, additional silicon oxide and / or silicon nitride layers may be formed as part of the hard mask layer 220. In one embodiment, the dummy gate layer 214 has a greater thickness than the hard mask layer 220 , and the silicon oxide layer 218 has a greater thickness than the silicon nitride layer 216 .

[0084] Continue to refer Figure 2 , method 100 forms a patterned photoresist 222 on the hard mask layer 220 in operation 108. The patterned photoresist 222 can be formed by first depositing a photoresist layer on the hard mask layer 220, and then patterning (also referred to as photolithography patterning) the photoresist layer by an exposure and development process. For example, forming a patterned photoresist may include spin coating a photoresist layer, soft baking a photoresist layer, mask alignment, exposure, post-exposure baking, developing a photoresist layer, rinsing and drying (e.g., hard baking). Alternatively, the photolithography patterning process may be implemented, supplemented or replaced by other methods, such as maskless lithography, electron beam writing, and ion beam writing. In any case, a patterned photoresist 222 is formed and used as a mask to pattern the hard mask layer 220 and the dummy gate layer 214.

[0085] Reference now Figure 3, using the patterned photoresist 222 as a mask, the method 100 performs an etching process (also referred to as a patterning process) in operation 110 to pattern the hard mask layer 220 and the dummy gate layer 214. The etching process in operation 110 is designed to pattern the dummy gate layer 214 and the hard mask layer 220 to have an uneven sidewall profile having a protruding portion to control the subsequent source / drain etching process on the source / drain region through an etching load effect, thereby reducing the corresponding source / drain etching rate. The etching process may include wet etching, dry etching, or a combination thereof. The etching process forms a patterned hard mask layer and a patterned dummy gate layer, also referred to as a patterned stack having a patterned dummy gate structure 214a and a patterned hard mask structure 220a. The patterned hard mask structure 220a includes a patterned silicon nitride layer 216a and a patterned silicon oxide layer 218a. As shown, the patterned hard mask structure 220a is etched and patterned to have an uneven profile having a protruding portion. In one embodiment, the protruding portion is a patterned silicon nitride layer 216a. The protruding portion of each of the patterned hard mask structures 220a has a width w1 along the x-direction, and the width w1 is greater than the width w2 of the patterned dummy gate structure 214a. For example, the width w1 of each of the patterned silicon nitride layers 216a is greater than the width w2 of the patterned dummy gate structure 214a. In one embodiment, the ratio of w1 / w2 is greater than 1.1. Although not explicitly shown, the patterned silicon oxide layer 218a may also have a greater width than the patterned dummy gate structure 214a (i.e., the width w3 is greater than the width w2). As will be described in operation 114, having a wider hard mask structure profile (patterned silicon nitride layer 216a and / or silicon oxide layer 218a) is beneficial for controlling the formation of source / drain trenches. In one embodiment, the width w1 of the patterned silicon nitride layer 216a is greater than the width w3 of the patterned silicon oxide layer 218a, and the width w3 of the patterned silicon oxide layer 218a is greater than the width w2 of the patterned dummy gate structure 214a. Figure 3 As part of operation 110 , the patterned photoresist 222 is removed.

[0086] refer to Figure 1B The etching process of operation 110 is described in more detail. Figure 1B As shown, the etching process is a multi-step etching process, which includes one or more main plasma etching steps (e.g., steps 110-1 and 110-3), one or more plasma treatment steps (e.g., steps 110-2, 110-4, and 110-6), and one or more plasma trimming steps (e.g., steps 110-5 and 110-7). Each main plasma etching step includes applying a halogen-containing gas, such as Cl 2Br 2 , HBr, HCl or a combination thereof. Each plasma conditioning step also includes applying a halogen-containing gas, such as Cl 2 Br 2 , HBr, HCl or a combination thereof. However, as described below, the main plasma etching step and the plasma trimming step differ in the time point and duration of applying the bias voltage (bias voltage) and the halogen-containing gas. Each plasma treatment step may include: 2 Ashing, CO 2 ashing, nitrogen plasma treatment or a combination thereof.

[0087] Figure 1B The description begins with step 110-1. At step 110-1, operation 110 performs a first main plasma etch to initially pattern the hard mask layer 220 and the dummy gate layer 214. After step 110-1, a general stack of patterned structures may be formed by the initial pattern transfer, but the patterned photoresist 222 remains on the stack of patterned structures. In one embodiment, the first main plasma etch step 110-1 applies a bias voltage and a Cl 2 Then, at step 110-2, operation 110 performs a first plasma treatment to completely (or partially) remove the patterned photoresist 222. The first plasma treatment step 110-2 may include: 2 Ashing, CO 2 In one embodiment, the first plasma treatment step 110-2 includes: 2 Then, a second main plasma etching step 110-3 and a second plasma treatment step 110-4 may be performed. The second main plasma etching step 110-3 may be optional and may be similar to the first main plasma etching step, and the second plasma treatment step 110-4 may be optional and may be similar to the first plasma treatment step 110-2. In one embodiment, the second main plasma etching step 110-3 applies a bias voltage and Cl 2 or HBr gas for further patterning. The bias voltage applied in step 110-3 may be similar to or different from the bias voltage applied in step 110-1. In one embodiment, the second plasma treatment step 110-4 includes CO 2The process is then performed by ashing to remove residual chemicals from the previous step or further removing the remaining portion of the patterned photoresist 222. Then, at step 110-5, operation 110 performs a first plasma trimming step to trim the stack of patterned structures. This may also be referred to as a first soft-landing step. In one embodiment, the first plasma trimming step 110-5 trims the patterned structure to form a protruding portion of the patterned hard mask structure 220a (see FIG. 2 ). Figure 3 ). For example, the plasma trimming step 110-5 trims the silicon nitride layer 216 at a slower rate than the dummy gate layer 214 and / or the silicon oxide layer 218, thereby forming an uneven profile with a protruding portion. In one embodiment, the first plasma trimming step 110-5 applies a bias voltage and Cl 2 or HBr gas. Then, a third plasma treatment step 110-6 may be performed. The third plasma treatment step 110-6 may be optional and may be similar to or different from the first or second plasma treatment steps 110-2 and 110-4. In one embodiment, the third plasma treatment step 110-4 includes a nitrogen treatment to remove residual chemicals from the previous step, or to further remove or clean the remaining portions of the patterned photoresist 222. Then, a second plasma trimming step 110-7 may be performed. This may also be referred to as a second soft landing step. The second plasma trimming step 110-7 may be optional and may be similar to the first plasma trimming step 110-5. In the event that the second plasma trimming step 110-7 is performed, it is performed after the plasma treatment step (e.g., step 110-6). The second plasma trimming step may further trim and shape the stack of patterned structures to form a protruding portion of the patterned hard mask structure 220a (refer to Figure 3 ).

[0088] Reference now Figure 4, the plasma trimming steps 110-5 and 110-7 can each be a cyclic etching process. The cyclic etching process can include multiple etching cycles 400, which are repeated iteratively according to design considerations. As shown, each etching cycle 400 of the cyclic etching process includes multiple pulses of bias and multiple pulses of a gas source (i.e., a halogen-containing gas flow). Each etching cycle 400 has a first duration t1 and a second duration t2 after the first duration t1. The first duration t1 is active, and the second duration t2 is inactive. In other words, during the first duration, the cyclic etching process includes applying multiple pulses of bias and gas source, and during the second duration, the cyclic etching process does not apply any bias or gas source. Therefore, during the first duration t1, each etching cycle 400 includes multiple pulses of bias and gas source, and during the second duration t2, each etching cycle 400 does not have bias and gas source. In order to realize an uneven profile with a protruding portion in the hard mask structure 220a, the first duration t1 should be 85-95% of the total duration of the cyclic etching process, and the second duration t2 should be 5-15% of the total duration of the cyclic etching process. In one embodiment, each duration t1 in the etching cycle 400 is equal to or less than 90% of the total duration in the etching cycle 400. In other words, the ratio of t1 / (t1+t2) is equal to or less than 90%.

[0089] Continue to refer Figure 4 , each of the multiple pulses of the bias voltage and the gas source is separated by an off period. The multiple pulses of the bias voltage and the gas source are evenly distributed within the first duration t1. In addition, the bias pulse and the gas source pulse can be applied simultaneously during the duration t1. Therefore, the multiple pulses of the bias voltage and the gas flow are synchronized (or aligned) in time to enhance the etching effect. In some embodiments, in a cyclic process, the amplitudes of the multiple pulses of the bias voltage are the same, and in the cyclic process, the amplitudes of the multiple pulses of the gas source are the same.

[0090] With reference Figure 4 Similar to the plasma trimming step described above, the main plasma etching steps 110-1 and 110-3 can also each be a cyclic etching process. In the same manner, the cyclic etching process for the main plasma etching step can include applying multiple pulses of bias voltage and gas source to perform multiple etching cycles. The gas source for the main plasma etching step can be similar to the gas source for the plasma trimming step (e.g., both use Cl 2or HBr gas). However, the bias applied by the main plasma etching step may be different from the bias applied by the plasma trimming step. For example, the voltage applied by the main etching is higher than the voltage applied by the trimming. In addition, each etching cycle of the main plasma etching step may have a third duration t3 (whose pulse is active) and a fourth duration t4 (whose pulse is off). However, unlike the plasma trimming step, the main plasma etching step will have a very small duration t4 (compared to t2) where the cyclic etching process does not apply any bias or gas source. In one embodiment, there is no duration t4 at all, and there is only a duration t3 of the periodic pulses of the applied bias and gas source. In another embodiment, if there is any duration t3, the duration t3 is greater than 99% of the total duration of the etching cycle. In other words, the ratio of t3 / (t3+t4) is greater than 99%. In one embodiment, the total duration of each main plasma etching step etching cycle is substantially greater than the total duration of each plasma trimming step etching cycle (i.e., t3+t4 is substantially greater than t1+t2, such as 2 or more times). It should be noted that the main plasma etching step is a coarse etching step to form a generally patterned structure, while the plasma trimming step is a fine etching step to form a desired profile and surface. As described above, the main plasma etching step and the plasma trimming step can have different etching time profiles to achieve the above features. In addition, compared to the main plasma etching step, the plasma trimming step can include other more targeted parameters.

[0091] Reference now Figure 5A, after operation 110 and its multi-step etching process 110-1 to 110-7, method 100 forms gate spacers 224 on the sidewalls of the patterned stacked structure (i.e., the patterned hard mask structure 220a and the patterned dummy gate structure 214a) in operation 112. The gate spacer 224 can be formed by a spacer deposition process and a spacer etching process. For example, a spacer deposition process is performed to form a conformal spacer layer on the patterned stacked structure and on the top surface of the active area 204. The spacer deposition process can include processes such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, electroplating, other suitable methods or combinations thereof. A spacer etching process is then performed, which selectively etches the horizontal portion (x direction) of the spacer layer to form the gate spacer 224 only or substantially only on the sidewalls of the patterned stacked structure. In some embodiments, the spacer layer comprises a dielectric material including silicon, oxygen, carbon, nitrogen, other suitable materials or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or silicon oxynitride and carbonitride). In some embodiments, the spacer layer comprises a low-k dielectric material.

[0092] Reference now Figure 5B , and continuing with reference to operation 112, the gate spacer 224 may be further processed such that a top portion of the gate spacer 224 is removed. This removal process may include selectively etching the gate spacer 224 while substantially not etching the patterned hard mask structure 220a, the patterned dummy gate structure 214a, and the active area 204. In one embodiment, a portion of the gate spacer located on a sidewall of the patterned hard mask structure 220a is removed, while a remaining portion of the gate spacer 224 remains on a sidewall portion of the patterned dummy gate structure 214a. It should be noted that in some embodiments, the additional removal process may be omitted and the active area 204 may be removed. Figure 5A The structure of continues directly to operation 114 .

[0093] Reference now Figure 6, the method 100 uses a patterned hard mask layer (i.e., a patterned hard mask structure 220a), a patterned dummy gate layer (i.e., a patterned dummy gate structure 214a), and a gate spacer 224 as an etching mask to form a source / drain (S / D) trench 242 in operation 114. The S / D trench 242 is formed by applying a bulk etching gas 233 downward and between adjacent hard mask structures 220a. The bulk etching gas 233 is applied to the S / D region of the active area 204. In this way, the S / D region is recessed to form the S / D trench 242. The amount of the bulk etching gas reaching the S / D region is affected by the uneven profile of the patterned stacked structure. Specifically, due to the protruding portion of the patterned hard mask structure 220a (e.g., the patterned silicon nitride layer 216a), the amount of the bulk etching gas is reduced after the bulk etching gas passes between the adjacent protruding portions of the patterned hard mask structure. The reduction in overall etching gas, as shown by the change in the size of the white arrows, is attributed to the overhangs blocking and capturing some of the etching gas traveling to the S / D regions.

[0094] Continue to refer Figure 6 , the S / D trench 242 has a sidewall defined by the remaining portion of the active area 204. The S / D trench 242 can be formed by a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof. In some embodiments, the etching process can include alternating etchants to individually and alternately remove the semiconductor layer 204a and the semiconductor layer 204b. In some embodiments, the parameters of the etching process are configured to etch the S / D region of the active area 204 while minimally (or even without) etching the patterned stacked structure (i.e., the patterned dummy gate structure 214a and the patterned hard mask structure 220a and the gate spacer 224).

[0095] Continue to refer Figure 6 , the S / D trench 242 extends into the substrate 202, passing through the bottommost semiconductor layer 204b of the active region 204. However, due to the reduction of the overall etching gas, the depth of the extension into the substrate 202 is not deep, which is ideal for forming subsequent S / D features without epitaxial merging problems. Now refer to Fig. 9 (Shown with Figure 8114), note that the bulk etching gas will also partially etch the isolation structure 203. In the illustrated embodiment, the isolation structure 203 is etched deeper than the top surface of the protrusion 202a in the negative z-direction. It should be noted that after the S / D trenches 242 are formed, the isolation structure 203 still has a portion of the protrusion 202a that completely surrounds the substrate 202. Specifically, the remaining sidewall portions of the isolation structure 203 pad and protect the sidewalls of the protrusion 202a. The sidewall portions of the isolation structure 203 guide and direct the direction of subsequent S / D epitaxial component growth. If these sidewall portions are damaged or unstable due to over-etching, subsequent S / D epitaxial growth may result in undesirable horizontal growth, which will merge adjacent S / D epitaxial components.

[0096] Reference now Figure 7 , method 100 forms S / D epitaxial components 206 in S / D trenches 242 in operation 116. S / D epitaxial components 206 may include n-type source / drain components corresponding to n-type transistor regions or p-type source / drain components corresponding to p-type transistor regions. The source / drain components may be formed by an epitaxial process using CVD deposition techniques (e.g., vapor phase epitaxy (VPE) and / or UHV-CVD), molecular beam epitaxy, other suitable epitaxial growth processes, or combinations thereof. The epitaxial process may use gaseous and / or liquid precursors that interact with the composition of substrate 202 and / or active region 204 (specifically, semiconductor layer 204a). S / D epitaxial components 206 are doped with n-type dopants and / or p-type dopants. In some embodiments, for n-type transistors, S / D epitaxial features 206 include silicon and may be doped with carbon, phosphorus, arsenic, other n-type dopants, or combinations thereof (e.g., to form Si:C epitaxial source / drain features, Si:P epitaxial source / drain features, or SiC:P epitaxial source / drain features). In some embodiments, for p-type transistors, S / D epitaxial features 206 include silicon germanium or germanium and may be doped with boron, other p-type dopants, or combinations thereof (e.g., to form SiGe:B epitaxial source / drain features). In this embodiment, S / D epitaxial features 206 are p-type S / D features that are designed not to merge with adjacent p-type S / D features.

[0097] Reference now Fig.10 (Shown with Fig. 9 Continuing with the same cross-sectional view and referring to operation 116 ), the S / D epitaxial feature 206 is formed on the etched top surface of the protruding portion 202 a of the substrate 202 . Fig.10Two S / D epitaxial features 206 are shown formed in the S / D regions of two different adjacent active regions 204. Since the sidewall portions of the isolation structure 203 are still intact and surround the protruding portion 202a, the S / D epitaxial features 206 are guided to grow generally in a vertical direction and do not merge with corresponding adjacent S / D epitaxial features 206.

[0098] The method 100 performs additional manufacturing processes in operation 118 to form a functional semiconductor device. For example, the method 100 removes the patterned hard mask structure 220a and performs a gate replacement process to form a metal gate to replace the patterned dummy gate structure 214a. The gate replacement process may include etching the patterned dummy gate structure 214a to form a gate trench, and then filling the gate trench with a gate metal to form a gate electrode. The gate replacement process may also include a planarization process to planarize the top surface of the gate spacer 224 with the top surface of the gate electrode or the gate dielectric cap formed on the gate electrode. For a GAA device, the method 100 may also perform a channel release process to form a suspended channel before performing the gate replacement process. The method 100 may also include: forming metal contacts on the S / D epitaxial component 206 and forming metal contacts on the metal gate; forming interconnects with vias and metal lines on the corresponding metal contacts; forming a redistribution structure on the interconnects; and performing IC bonding and packaging processes. Additional operations may be provided before, during, and after the method 100. Furthermore, some operations described in this disclosure may be moved, replaced, or eliminated for additional embodiments of the method 100.

[0099] Fig.11 Another embodiment of the present disclosure incorporating the hard mask design and patterning process described is shown. Specifically, Fig.11A semiconductor structure 200 is shown, which includes a first S / D region having a shallow S / D trench 242a and a second S / D region having a deep S / D trench 242b. The shallow S / D trench 242a is similar to the previously described S / D trench 242. The shallow S / D trench 242a is formed due to the etching process in operation 110, which results in an uneven hard mask profile having a protruding portion to block the bulk etching gas when forming the S / D trench 242a. It should be noted that the uneven profile is caused by the plasma trimming steps 110-5 and / or 110-7 having a unique and targeted pulse pattern. On the other hand, the deep S / D trench 242b is formed due to the formation of the patterned hard mask structure 220b, which does not have an uneven hard mask profile and does not have a protruding portion. Therefore, more bulk etching gas passes through to form the deep trench 242b. As shown, the patterned hard mask structure 220b and the patterned dummy gate structure 214b have a flat profile. This may be the result of adjusting the plasma trimming steps 110-5 and / or 110-7 to be more similar to the main plasma etching steps 110-1 and 110-3, such as in terms of pulse timing and duration (e.g., the same t1 and t2 durations). In another embodiment, the plasma trimming steps may be omitted.

[0100] Continue to refer Fig.11 , the shallow S / D trench 242a and the deep trench 242b can be formed in different areas of the substrate 202 (i.e., they are not necessarily adjacent). For example, the shallow S / D trench 242a is formed in the S / D region for the p-type epitaxial S / D component, and the deep S / D trench 242b is formed in the S / D region for the n-type epitaxial S / D component. In some embodiments, the patterned dummy gate structures 214a and 214b and the patterned hard mask structures 220a and 220b are formed in separate process sequences, and the process sequence includes, for example, shielding the p-type S / D region when patterning to form the patterned dummy gate structure 214b and the patterned hard mask structure 220b, and shielding the n-type transistor region when forming the patterned dummy gate structure 214a and the patterned hard mask structure 220a in the p-type S / D region. Since the hard mask profiles of the patterned hard mask structures 220 a and 220 b are different, a single overall etching step may be performed to form the S / D trenches 242 a and 242 b , thereby improving the S / D engineering window.

[0101] Reference now Fig.12, due to the formation of shallow S / D trenches 242a and deep S / D trenches 242b, the subsequent S / D epitaxial growth process can form merged epitaxial S / D components 206b and non-merged epitaxial S / D components 206a. As described above, forming a deeper S / D trench may result in over-etching, in which the sidewall portion of the isolation structure 203 is damaged, while forming a shallower S / D trench avoids this problem. In the case of a damaged or fragile sidewall portion in the isolation structure 203, there may be horizontal epitaxial growth that breaks through the damaged sidewall and merges with the adjacent S / D component (refer to epitaxial S / D component 206b). The epitaxial merger can be located at the lower portion of the epitaxial S / D component 206b because the lower portions of the epitaxial S / D components 206b are closer to each other than the top. On the other hand, referring to the epitaxial S / D component 206a, when there is no over-etching problem and the sidewall portion of the isolation structure 203 remains solid, there is no merging problem because the lower portion of the epitaxial S / D component 206a does not break through the sidewall portion of the isolation structure 203. In one embodiment, the epitaxial S / D component 206a is a p-type S / D component designed not to merge, and the epitaxial S / D component 206b is an n-type S / D component designed to be free to merge or not merge. In some cases, it is desirable to merge the n-type S / D component to improve the via contact landing and reduce the contact resistance. As Fig.12 As shown, the bottom surface of each epitaxial S / D component 206a is located above the bottom surface of each epitaxial S / D component 206b. This is because the S / D trench formed for S / D component 206a is shallower than the S / D trench formed for S / D component 206b. The lower portion (i.e., the merged portion) of the epitaxial S / D component 206b breaks through the sidewall portion of the isolation structure 203. In this way, the sidewall portion of the isolation structure 203 can exist vertically between the lower and upper portions of the epitaxial S / D component 206b. It should be noted that these lower portions (merged portions) of the epitaxial S / D component 206b do not exist in the epitaxial S / D component 206a.

[0102] Although not intended to be limiting, some embodiments of the present disclosure provide benefits for forming epitaxial S / D components. One example benefit is the ability to adjust the source / drain trench depth by adjusting the hard mask profile when forming a dummy gate structure. For example, the present disclosure contemplates enlarging a portion of the hard mask profile to block excess bulk etching gas. Due to the gate hard mask profile design, the source / drain trenches are formed shallower and do not cause damage to the isolation structure, thereby preventing the undesirable source / drain epitaxial merging described in the embodiments. Another example embodiment combines different hard mask profile designs to form S / D components that are designed not to merge and S / D components that are designed to be freely merged.

[0103] In some embodiments, the present disclosure provides a method for forming a semiconductor structure, comprising: forming an active area on a substrate; forming a dummy gate layer on the active area; forming a hard mask layer on the dummy gate layer; forming a patterned photoresist on the hard mask layer; and performing an etching process on the hard mask layer and the dummy gate layer using the patterned photoresist to form a patterned hard mask structure and a patterned dummy gate structure, wherein the patterned hard mask structure is formed to have an uneven profile, the uneven profile having a protruding portion, wherein the protruding portion of each of the patterned hard mask structures has a first width, wherein the patterned dummy gate structures each have a second width, and the first width is greater than the second width.

[0104] In some embodiments, the dummy gate layer includes polysilicon or amorphous silicon, and the hard mask layer includes silicon oxide and silicon nitride.

[0105] In some embodiments, the hard mask layer includes a silicon oxide layer formed on a silicon nitride layer, and the protruding portion is the silicon nitride layer.

[0106] In some embodiments, the etching process is a multi-step etching process, the multi-step etching process comprising one or more main plasma etching steps, one or more plasma treatment steps, and one or more plasma trimming steps, wherein the main plasma etching step and the plasma trimming step comprise applying a plasma selected from Cl 2 Br 2 , HBr, HCl or a combination thereof, wherein the plasma treatment step comprises O 2 Ashing, CO 2 ashing, nitrogen plasma treatment or a combination thereof.

[0107] In some embodiments, one of the plasma trimming steps is a cyclic etching process, each cycle of the cyclic etching process has a pulse of the bias voltage and a pulse of the halogen-containing gas flow.

[0108] In some embodiments, each cycle of the cyclic etching process includes a first duration t1 and a second duration t2 after the first duration, the first duration of the cyclic etching process includes a pulse of a bias, and the second duration of the cyclic etching process does not have a bias, wherein the first duration t1 is 85-95% of the total duration of the cyclic etching process, and the second duration t2 is 5-15% of the total duration of the cyclic etching process.

[0109] In some embodiments, one of the plasma trimming steps forms respective protruding portions of the patterned hard mask structure.

[0110] In some embodiments, it also includes: forming gate spacers along the sidewalls of the patterned dummy gate structures; forming source / drain trenches between the patterned dummy gate structures and in the source / drain (S / D) regions of the active area; and forming source / drain epitaxial components in the source / drain trenches.

[0111] In some embodiments, wherein the active region is a first active region and the source / drain epitaxial component is a first epitaxial component, it also includes: forming a second active region on the substrate and adjacent to the first active region; forming a second source / drain trench between the patterned dummy gate structures and in a second source / drain region of the second active region; and forming a second source / drain epitaxial component in the second source / drain trench, wherein the first source / drain epitaxial component is not merged with the second source / drain epitaxial component.

[0112] In some embodiments, forming the source / drain trench includes etching through the source / drain region of the active area and partially etching an isolation structure, wherein the isolation structure surrounds a protruding portion of the substrate, wherein after forming the source / drain trench, the isolation structure still has a portion, and the portion completely surrounds the protruding portion of the substrate.

[0113] In other embodiments, the present disclosure provides a method for forming a semiconductor structure, comprising: depositing a dummy gate layer on an active area of ​​a semiconductor substrate; depositing a hard mask layer on the dummy gate layer, the hard mask layer comprising a first dielectric film and a second dielectric film on the first dielectric film; performing a patterning process on the hard mask layer and the dummy gate layer, wherein the patterning process comprises a first etching process, the first etching process having an etching step, and one of the etching steps is a cyclic etching process, the cyclic etching process being designed to form a patterned stack of the hard mask layer and the dummy gate layer having an uneven profile, such that the first dielectric film of each of the patterned stacks spans a first width w1, and the dummy gate layer of each of the patterned stacks spans a second width w2, the second width being less than the first width; and recessing the source / drain region of the active area by a second etching process, the second etching process being affected by the uneven profile of the patterned stack.

[0114] In other embodiments, the cyclic etching process includes applying a bias voltage and a gas flow of an etching chemical, each cycle of the cyclic etching process includes a first duration t1 and a second duration t2 after the first duration, and the first duration of the cyclic etching process includes a pulse of the bias voltage, and the second duration of the cyclic etching process does not have a bias voltage.

[0115] In other embodiments, a first ratio of the first duration t1 / (first duration t1 +second duration t2) is less than 90%, and a second ratio of the first width w1 / second width w2 is greater than 1.1.

[0116] In other embodiments, a first duration of the cyclic etch process includes a pulse of gas flow, and a second duration of the cyclic etch process is without gas flow.

[0117] In other embodiments, the pulses of the bias voltage and the pulses of the gas flow are synchronized.

[0118] In other embodiments, the pulses of the bias voltage are evenly distributed over the first duration.

[0119] In other embodiments, one of the etching steps is a second etching step, the cyclic etching process is a second cyclic etching process, the bias is a second bias, and the gas flow is a second gas flow, wherein the first etching process also includes a first etching step, and the first etching step is a first cyclic etching process performed before the second etching step, the first cyclic etching process includes applying a first bias and a first gas flow of etching chemicals, each cycle of the first cyclic etching process includes a third duration t3 and a fourth duration t4 after the third duration, the third duration of the first cyclic etching process includes a pulse of the first bias, and the fourth duration of the first cyclic etching process does not have the first bias, and a third ratio of the third duration t3 / (third duration t3+fourth duration t4) is greater than 99%.

[0120] In yet another embodiment, the present disclosure provides a semiconductor structure comprising: a first epitaxial source / drain (S / D) component on a first protruding portion of a substrate; a second epitaxial source / drain component on a second protruding portion of the substrate; a third epitaxial source / drain component on a third protruding portion of the substrate; a fourth epitaxial source / drain component on a fourth protruding portion of the substrate; and an isolation structure on the substrate, the isolation structure having a base and a sidewall portion, the base being on a top surface of the substrate, and the sidewall portion being on sidewalls of the first, second, third and fourth protruding portions of the substrate, wherein the first epitaxial source / drain component and the second epitaxial source / drain component are not merged, and wherein the third epitaxial source / drain component and the fourth epitaxial source / drain component are merged by breaking through the sidewall portion of the isolation structure.

[0121] In yet other embodiments, the third epitaxial source / drain feature and the fourth epitaxial source / drain feature are merged at a lower portion of the third epitaxial source / drain feature and the fourth epitaxial source / drain feature.

[0122] In yet other embodiments, the first and second epitaxial source / drain features are p-type source / drain features, and the third and fourth epitaxial source / drain features are n-type source / drain features.

[0123] The features of several embodiments are summarized above so that those skilled in the art can better understand the viewpoints of the embodiments of the present disclosure. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present disclosure to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art should also understand that such equivalent structures do not deviate from the spirit and scope of the embodiments of the present disclosure, and various changes, substitutions and replacements can be made without violating the spirit and scope of the embodiments of the present disclosure. Therefore, the scope of protection of the present disclosure shall be defined as defined by the appended claims.

Claims

1. A semiconductor structure, characterized in that: include: a first epitaxial source / drain feature on a first protruding portion of a substrate; a second epitaxial source / drain feature on a second protruding portion of the substrate; a third epitaxial source / drain feature on a third protruding portion of the substrate; a fourth epitaxial source / drain feature on a fourth protruding portion of the substrate; as well as an isolation structure on the substrate, the isolation structure having a base and a plurality of side wall portions, the base being on a top surface of the substrate, the plurality of side wall portions being on side walls of the first, second, third and fourth protruding portions of the substrate, wherein the first epitaxial source / drain component and the second epitaxial source / drain component are not merged, The third epitaxial source / drain feature and the fourth epitaxial source / drain feature are merged by breaking through the plurality of sidewall portions of the isolation structure.

2. The semiconductor structure according to claim 1, wherein: The third epitaxial source / drain feature and the fourth epitaxial source / drain feature merge at a lower portion of the third epitaxial source / drain feature and the fourth epitaxial source / drain feature.

3. The semiconductor structure according to claim 1, wherein: The first epitaxial source / drain component and the second epitaxial source / drain component are p-type source / drain components, and the third epitaxial source / drain component and the fourth epitaxial source / drain component are n-type source / drain components.

4. The semiconductor structure according to claim 1, wherein: There are a plurality of sidewall portions of the isolation structure vertically between an upper portion and a lower portion of the third epitaxial source / drain feature.

5. The semiconductor structure according to claim 1, wherein: There are a plurality of said sidewall portions of the isolation structure vertically between an upper portion and a lower portion of the fourth epitaxial source / drain feature.

6. The semiconductor structure according to any one of claims 1 to 5, characterized in that: A bottom surface of the first epitaxial source / drain feature is higher than a bottom surface of the third epitaxial source / drain feature.

7. The semiconductor structure according to any one of claims 1 to 5, characterized in that: A bottom surface of the first epitaxial source / drain feature is higher than a bottom surface of the fourth epitaxial source / drain feature.

8. The semiconductor structure according to any one of claims 1 to 5, characterized in that: A bottom surface of the second epitaxial source / drain feature is higher than a bottom surface of the third epitaxial source / drain feature.

9. The semiconductor structure according to any one of claims 1 to 5, characterized in that: A bottom surface of the second epitaxial source / drain feature is higher than a bottom surface of the fourth epitaxial source / drain feature.

10. The semiconductor structure according to any one of claims 1 to 5, characterized in that: Also included is a redistribution structure on the first epitaxial source / drain feature.

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