Semiconductor device

Abstract

A semiconductor device includes a substrate. A plurality of semiconductor channel layers are over the substrate. A gate structure encapsulates each of the plurality of semiconductor channel layers. A plurality of source / drain epitaxial structures are on opposite sides of the gate structure. A plurality of epitaxial seed layers are respectively under the plurality of source / drain epitaxial structures, wherein a lattice constant of the plurality of epitaxial seed layers is different from a lattice constant of the plurality of source / drain epitaxial structures. A plurality of isolation layers are over the substrate and vertically under the plurality of epitaxial seed layers, respectively.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced several generations of ICs. Each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs. During the evolution of ICs, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometric size (i.e., the smallest component (or wiring) that can be produced using a manufacturing process) has decreased. This scaling down process provides benefits by increasing production efficiency and reducing associated costs. However, as feature sizes continue to decrease, manufacturing processes continue to become more difficult to perform. Therefore, it is a challenge to form reliable semiconductor devices in increasingly smaller sizes. Utility Model Content

[0003] In some embodiments of the present disclosure, a semiconductor device includes a substrate. A plurality of semiconductor channel layers are above the substrate. A gate structure covers each of the plurality of semiconductor channel layers. A plurality of source / drain epitaxial structures are on a plurality of opposite sides of the gate structure. A plurality of epitaxial seed layers are respectively below the plurality of source / drain epitaxial structures, wherein a lattice constant of the plurality of epitaxial seed layers is different from a lattice constant of the plurality of source / drain epitaxial structures.

[0004] In some embodiments of the present disclosure, a semiconductor device includes a substrate. A plurality of semiconductor channel layers are above the substrate. A gate structure covers each of the plurality of semiconductor channel layers. A plurality of source / drain epitaxial structures are on a plurality of opposite sides of the gate structure. Epitaxial seed layers are respectively below the plurality of source / drain epitaxial structures. A plurality of dielectric layers are respectively above the substrate and vertically below the plurality of epitaxial seed layers, wherein an air gap is vertically between one of the plurality of epitaxial seed layers and one of the plurality of dielectric layers.

[0005] In some embodiments of the present disclosure, a semiconductor device includes a substrate. A plurality of semiconductor channel layers are above the substrate. A gate structure covers each of the plurality of semiconductor channel layers. A plurality of source / drain epitaxial structures are on a plurality of opposite sides of the gate structure. Epitaxial seed layers are respectively below the plurality of source / drain epitaxial structures. A plurality of dielectric layers are respectively above the substrate and vertically below the plurality of epitaxial seed layers, wherein an air gap is vertically between one of the plurality of epitaxial seed layers and one of the plurality of dielectric layers, wherein a top surface of one of the plurality of epitaxial seed layers is lower than a top surface of a bottommost semiconductor channel layer among the plurality of semiconductor channel layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of this disclosure are in the attached Figure 1 The following detailed description is best understood when read together. Please note that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figures 1 to 10 illustrates a method of forming a semiconductor device at various stages according to some embodiments of the present disclosure;

[0008] Fig.11 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0009] Fig. 12A and Fig. 12B is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0010] Fig.13 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

[0011]

Explanation of symbols

[0012] 100:Substrate

[0013] 102: Semiconductor layer

[0014] 104: Semiconductor layer

[0015] 115: Gate spacer

[0016] 115: Gate spacer

[0017] 116: Internal spacer

[0018] 130: dummy gate structure

[0019] 132: Dummy gate dielectric

[0020] 134: dummy gate electrode

[0021] 140: Source / drain epitaxial structure

[0022] 142: Epitaxial layer

[0023] 144: Isolation layer

[0024] 146: epitaxial seed layer

[0025] 152: Interlayer dielectric layer

[0026] 155: contact etching stop layer

[0027] 170: Gate structure

[0028] 172: Gate dielectric layer

[0029] 174: Work function metal layer

[0030] 176: Filler Metal

[0031] AG: Air Gap

[0032] CPP: Spacing

[0033] d Iso :depth

[0034] d S :distance

[0035] GT: Gate Trench

[0036] h gap :high

[0037] h Iso :high

[0038] h SL :high

[0039] h S :high

[0040] I gap :length

[0041] I Iso :length

[0042] I SL :length

[0043] I S :length

[0044] MA: Patterned Mask

[0045] O1: Source / Drain Opening

[0046] ST: Semiconductor stacking

[0047] θB :angle

[0048] θ I :angle

[0049] θ T :angle DETAILED DESCRIPTION

[0050] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these components and configurations are only examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first and second features are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first and second features so that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0051] Additionally, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and the like, may be used herein for ease of description to describe the relationship of one or more elements or features to another or further elements or features as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0052] A gate all around (GAA) transistor structure may be patterned by any suitable method. For example, the structure may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Generally, the double patterning or multiple patterning process combines photolithography and self-alignment processes, thereby allowing patterns to be produced, wherein the multiple patterns have a spacing that is, for example, smaller than the spacing otherwise obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed above a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure. Although the embodiments of the present disclosure are explained with respect to the GAA structure, the embodiments of the present disclosure may also be applied to a variety of metal oxide semiconductor transistors (e.g., complementary-field effect transistors (CFETs) and fin field effect transistors (FinFETs)).

[0053] Figures 1 to 10 Schematic diagram of a method of forming a semiconductor device at various stages according to some embodiments of the present disclosure. Figures 1 to 10 Described as a series of actions, it should be understood that these actions are not limited to the order of actions that can be changed in other embodiments, and the disclosed method can also be applied to other structures. In other embodiments, some actions illustrated and / or described can be omitted in whole or in part.

[0054] See also Figure 1 . Depicted is a substrate 100. Generally speaking, the substrate 100 may include a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulator layer below a thin semiconductor layer, which is an active layer of the SOI substrate. The semiconductor of the active layer and the bulk semiconductor typically include a crystalline semiconductor material silicon, but may include one or more other semiconductor materials, such as germanium, a silicon-germanium alloy, a compound semiconductor (e.g., GaAs, AlAs, InAs, GaN, AlN, and the like), or alloys thereof (e.g., Ga x Al 1-x As、Ga x Al 1-x N、In x Ga 1-x As and the like), oxide semiconductors (e.g., ZnO, SnO 2 、TiO 2 , Ga 2 O 3and the like), or a combination thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or hybrid oriented substrates. In some embodiments, substrate 100 may include a (100) crystal orientation or a (110) crystal orientation.

[0055] A semiconductor stack ST is formed over a substrate 100. The semiconductor stack ST includes alternating semiconductor layers 102 and 104. In some embodiments, the semiconductor layer 102 may be made of a pure silicon layer without germanium. The semiconductor layer 102 may also be a substantially pure silicon layer, such as a layer having a germanium percentage of less than about 1 percent. The semiconductor layer 104 may be made of silicon germanium. For example, the germanium percentage (atomic percentage concentration) of the semiconductor layer 104 is in the range of about 15% and about 40%. In some embodiments, the semiconductor layers 102 and 104 may be deposited using a suitable deposition process, such as selective epitaxial growth (SEG), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), or other suitable processes. In some embodiments, the semiconductor layer 104 may be removed during a replacement gate (RPG) process, and thus the semiconductor layer 104 may also be referred to as a sacrificial layer. In some embodiments, the semiconductor layer 102 may serve as a channel region of a transistor, and thus the semiconductor layer 102 may also be referred to as a semiconductor channel layer. In some embodiments, the semiconductor stack ST is patterned to form a fin-like structure protruding from the top surface of the substrate 100, and thus the semiconductor stack ST may also be referred to as a fin structure.

[0056] In some embodiments, depending on the geometric size, the semiconductor layer 102 may be interchangeably referred to as a nanosheet, a nanowire, a nanoslat, a nanoring, or a nanostructure having a nanoscale size (e.g., a few nanometers). It should be understood that the number of semiconductor layers 102 is for explanation only, and the present disclosure is not limited thereto. In some embodiments, the number of semiconductor layers 102 is in the range from about 1 to about 10.

[0057] See also Figure 2. The dummy gate structures 130 are formed above the substrate 100 and span the semiconductor stack ST. In some embodiments, each of the dummy gate structures 130 includes a dummy gate dielectric 132 and a dummy gate electrode 134 above the dummy gate dielectric 132. The dummy gate dielectric 132 may be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. The dummy gate electrode 134 may be a conductive or non-conductive material, and is selected from the group consisting of: amorphous silicon, polycrystalline silicon (poly-Si), polycrystalline titanium silicon germanium (poly-SiGe), metal nitride, metal silicide, metal oxide, and metal.

[0058] The dummy gate electrode 134 and the dummy gate dielectric 132 may be formed, for example, by depositing a dummy dielectric layer and a dummy gate layer over the substrate 100, forming a patterned mask MA over the dummy gate layer, and then performing an etching process on the dummy dielectric layer and the dummy gate layer by using the patterned mask MA as an etching mask. In some embodiments, the dummy gate electrode 134 may be deposited by physical vapor deposition (PVD), CVD, chemical vapor deposition (CVD), sputtering deposition, or other techniques for depositing a selected material. In some embodiments, the dummy gate dielectric 132 may be formed by thermal oxidation. In some embodiments, each of the patterned masks MA includes silicon nitride, silicon oxide, a combination thereof, or the like.

[0059] Gate spacers 115 are formed on opposite sidewalls of each of the dummy gate structures 130. In some embodiments, the gate spacers 115 may be formed of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In some embodiments, the gate spacers 115 may be formed by, for example, depositing a blanket spacer layer over a substrate, and then performing an anisotropic etching process to remove horizontal portions of the spacer layer, such that vertical portions of the spacer layer remain on the sidewalls of the dummy gate structures 130. In some embodiments, the remaining vertical portions of the spacer layer on the sidewalls of the dummy gate structures 130 may be referred to as gate spacers 115. In some embodiments, the spacer layer may be deposited using techniques such as CVD, ALD, or the like.

[0060] See also Figure 3 By using the dummy gate structure 130 and the gate spacer 115 as an etching mask, an etching process is performed to remove a portion of the semiconductor stack ST so as to form a source / drain opening O1 in the semiconductor stack ST. In some embodiments, the etching process may be dry etching, wet etching, or a combination thereof. In some embodiments, the bottommost end of the source / drain opening O1 may be lower than the top surface of the substrate 100.

[0061] After forming the source / drain openings O1, the semiconductor layer 104 is laterally etched to form sidewall recesses. In some embodiments, the sidewalls of the semiconductor layer 104 can be etched using an isotropic etching process such as wet etching or the like. In some embodiments where the semiconductor layer 104 includes, for example, SiGe and the semiconductor layer 102 includes, for example, Si, the sidewalls of the semiconductor layer 104 can be etched using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH 4 An etching process such as OH) or the like may be used to etch the sidewalls of the semiconductor layer 104.

[0062] Next, inner spacers 116 are formed in the sidewall recesses on opposite ends of each of the semiconductor layers 104. In some embodiments, the inner spacers 116 may be formed by, for example, depositing an inner spacer layer blanket over the substrate 100 and filling the sidewall recesses, and then performing an anisotropic etch to remove portions of the inner spacer layer outside the sidewall recesses, thereby leaving the remaining portions of the inner spacer layer in the sidewall recesses as the inner spacers 116. The inner spacers 116 may be deposited by a conformal deposition process such as CVD, ALD, or the like. The inner spacer layer may include materials such as SiN, SiOCN, SiCN, SIOC, although any suitable material may be utilized, such as a low-dielectric constant (low-k) material having a k value of less than about 3.5.

[0063] The epitaxial layer 142 is formed at the bottom of the source / drain opening O1. The epitaxial layer 142 may be made of silicon (Si). In some embodiments, forming the epitaxial layer 142 may include a plurality of deposition cycles, wherein each deposition cycle may include a selective epitaxial growth (SEG) process and an etching process. In some embodiments, the SEG process may selectively grow semiconductor material on exposed semiconductor surfaces, such as the exposed surface of the substrate 100 and the exposed surface of the semiconductor layer 102. However, because the exposed area of ​​the substrate 100 is larger than the exposed area of ​​each of the semiconductor layers 102, the semiconductor material may include a higher growth rate on the exposed area of ​​the substrate 100 compared to the exposed area of ​​each of the semiconductor layers 102. That is, a larger amount of semiconductor material will grow on the exposed area of ​​the substrate 100 than on the exposed area of ​​each of the semiconductor layers 102. Therefore, the etching process in each deposition cycle of the epitaxial layer 142 may remove a portion of the semiconductor material formed on the exposed area of ​​each of the semiconductor layers 102, while a plurality of portions of the semiconductor material may remain above the substrate 100 after the etching process. Therefore, performing several deposition cycles may allow for bottom-up deposition for the epitaxial layer 142. That is, the epitaxial layer 142 may be formed from the bottom of the source / drain opening O1 via a bottom-up approach. In some embodiments, the epitaxial layer 142 may be formed without performing an implantation process, and thus the epitaxial layer 142 is undoped.

[0064] See also Figure 4 The isolation layer 144 is formed in the source / drain openings O1 and is located above the respective epitaxial layers 142. In some embodiments, the isolation layer 144 may be made of a dielectric material such as silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), aluminum oxide (Al 2 O 3 ) or the like. In some embodiments, the isolation layer 144 may be formed by a suitable deposition process and an etching process. The isolation layer 144 may contact the bottommost inner spacer 116 vertically between the substrate 100 and the bottommost semiconductor layer 102, while other inner spacers 116 of the bottommost inner spacer 116 may not be covered by the isolation layer 144. The isolation layer 144 provides an overlapping source / drain structure (e.g., Figure 8 Electrical isolation between the epitaxial seed layer 146 and the source / drain epitaxial structure 140) and the substrate 100.

[0065] See also Figure 5. The epitaxial seed layer 146 is formed in the source / drain openings O1 and is located above the respective isolation layers 144. In some embodiments, the epitaxial seed layer 146 may include a crystalline structure. For example, the epitaxial seed layer 146 may be made of silicon or silicon germanium. In embodiments where the device is an N-type device (NMOS), the epitaxial seed layer 146 may be made of substantially pure silicon, such as having a germanium percentage of less than about 1%. In embodiments where the device is a P-type device (PMOS), the epitaxial seed layer 146 may be made of silicon germanium (SiGe). 1-x Ge x ), the silicon germanium having a germanium concentration ranging from about 0% to 50% (x=0% to 50%). The epitaxial seed layer 146 may be N-type doped (for N-type devices), P-type doped (for P-type devices), and the dopant concentration may be about 10 17 Atom / cm 3 to about 10 21 Atom / cm 3 . Exemplary N-type dopants may be phosphorus (P), arsenic (As), or antimony (Sb), or the like. Exemplary P-type dopants may be boron (B), gallium (Ga), indium (In), aluminum (Al), or the like. The epitaxial seed layer 146 may be doped in situ or may be doped ex situ. In some embodiments, the epitaxial seed layer 146 and the epitaxial layer 142 may be made of the same material, such as silicon.

[0066] The epitaxial seed layer 146 may be deposited using a suitable deposition process, such as a selective epitaxial growth (SEG) process. In some embodiments, the epitaxial seed layer 146 may be deposited using a silicon-containing precursor (silicon source) and / or a germanium-containing precursor (germanium source). Exemplary silicon-containing precursors may include SiH 4 、Si 2 H 6 、Si x H 2x+2 , H 2 SiCl 2 or the like. Exemplary silicon-containing precursors may include GeH 4 ,Ge 2 H 6 Or the like. The deposition process is performed at a temperature ranging from about 300° C. to about 900° C. The deposition process is performed at a pressure ranging from about 0.1 Torr to about 300 Torr.

[0067] See also Figure 6The etch-back process is performed to lower the lower top surface of the epitaxial seed layer 146 to a desired position. In the depicted embodiment, the top surface of the etched epitaxial seed layer 146 can be substantially flush with the top surface of the topmost semiconductor layer of the semiconductor layer 102. In other embodiments, the top surface of the etched epitaxial seed layer 146 can be lower than the top surface of the bottommost semiconductor layer of the semiconductor layer 102 (see Fig.11 of the embodiment of the invention).

[0068] The etch-back process may be wet etching, dry etching, or the like. In some embodiments, the etch-back process may include reactive-ion etching (RIE). RIE etching may use materials such as Cl, HCl, BCl 3 , SF 6 CF 4 , C 4 F 8 The RIE etch may be performed at a pressure ranging from about 0.01 Torr to about 100 Torr or at a pressure ranging from about 0.1 mTorr to about 100 mTorr.

[0069] See also Figure 7 . The source / drain epitaxial structure 140 is formed in the source / drain opening O1 and above the respective epitaxial seed layer 146. The source / drain epitaxial structure 140 may be formed by a suitable deposition process, such as a selective epitaxial growth (SEG) process. In some embodiments, the SEG process may selectively grow semiconductor material on exposed semiconductor surfaces, such as the exposed surface of the epitaxial seed layer 146 and the exposed surface of the semiconductor layer 102. In some embodiments, an implantation process may be performed on the source / drain epitaxial structure 140. For example, when the device is an N-type device, the source / drain epitaxial structure 140 may be doped with an n-type dopant, such as phosphorus (P), arsenic (As), or antimony (Sb), or the like. Alternatively, when the device is a P-type device, the source / drain epitaxial structure 140 may be doped with a p-type dopant, such as boron (B), gallium (Ga), indium (In), aluminum (Al), or the like. In some embodiments, the source / drain epitaxial structure 140 may include a material different from the epitaxial seed layer 146. For example, the epitaxial seed layer 146 may be made of silicon, while the source / drain epitaxial structure 140 may be made of silicon germanium. That is, the source / drain epitaxial structure 140 includes a higher germanium concentration than the epitaxial seed layer 146. In some embodiments, the dopant concentration of the source / drain epitaxial structure 140 may be higher than the dopant concentration of the epitaxial seed layer 146. For example, the dopant concentration of the source / drain epitaxial structure 140 is about 1×10 17 Atom / cm 3 About 1×1022 Atom / cm 3 within the range.

[0070] In some embodiments, the material of the source / drain epitaxial structure 140 has a different lattice constant than the material of the epitaxial seed layer 146, so that strain can be generated in the source / drain epitaxial structure 140. For example, the source / drain epitaxial structure 140 can be a strained silicon germanium (SiGe) layer. Generally speaking, when a first semiconductor material is grown on a single crystal of a second semiconductor layer, strain is generated when the two semiconductor materials are lattice mismatched with each other. Silicon and germanium are lattice mismatched with each other, so that the growth of silicon and silicon germanium on each other produces strain that can be tensile or compressive. In the depicted embodiment, silicon germanium (e.g., source / drain epitaxial structure 140) is epitaxially grown on silicon (e.g., epitaxial seed layer 146) so as to have a crystal structure that is aligned with the silicon crystal structure. Because silicon germanium normally has a larger crystal structure than the silicon crystal structure, the epitaxially grown silicon germanium becomes intrinsically compressed. Therefore, the source / drain epitaxial structure 140 is strained, which in turn improves device performance. In some embodiments where the epitaxial seed layer 146 is omitted, the underlying isolation layer 144 may not induce strain to the source / drain epitaxial structure 140 .

[0071] See also Figure 8 A contact etch stop layer 155 is formed to cover the source / drain epitaxial structure 140. Thereafter, an interlayer dielectric layer 152 is formed over the contact etch stop layer 155. Next, a planarization process such as CMP is performed to remove excess material of the contact etch stop layer 155 and the interlayer dielectric layer 152, so that the top surface of the dummy gate structure 130 is exposed.

[0072] In some embodiments, the contact etch stop layer 155 may be a dielectric material including silicon nitride, silicon oxynitride, or other suitable materials. In some embodiments, the interlayer dielectric layer 152 may include silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric materials, and / or other suitable dielectric materials. Examples of low-k dielectric materials include, but are not limited to, fluorinated silica glass (FSG), carbon-doped silicon oxide, amorphous fluorinated carbon, polyparaxylene, bis-benzocyclobutenes (BCB), or polyimide. The contact etch stop layer 155 and the interlayer dielectric layer 152 may be formed using, for example, CVD, ALD, or other suitable techniques.

[0073] See also Fig. 9 The dummy gate structure 130 is removed to form a gate trench GT between each pair of gate spacers 115. Next, an etching process is performed to remove the semiconductor layer 104 through the gate trench GT so that the semiconductor layer 102 is suspended above the substrate 100. In some embodiments, the dummy gate structure 130 and the semiconductor layer 102 may be etched using a suitable process such as dry etching, wet etching, or the like.

[0074] See also Fig.10 The metal gate structure 170 is formed in the gate trench GT and covers each of the semiconductor layers 102. In some embodiments, each of the metal gate structures 170 includes an interface layer (not shown), a gate dielectric layer 172, a work function metal layer 174, and a filling metal 176. Next, a planarization process such as CMP is performed to remove excess material of the gate dielectric layer 172, the work function metal layer 174, and the filling metal 176 until the interlayer dielectric layer 152 is exposed.

[0075] In some embodiments, the interface layer may be made of an oxide, such as aluminum oxide (Al 2 O 3 ), silicon oxide (SiO 2 ) or the like. In some embodiments, the gate dielectric layer 172 may include a high-k dielectric. Examples of high-k dielectric materials include HfO 2 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、zirconia、alumina、titanium oxide、hafnium dioxide-alumina (HfO 2 —Al 2 O 3 ) alloys, other suitable high-k dielectric materials, and / or combinations thereof.

[0076] The work function metal layer 174 can be an n-type or p-type work function layer. Exemplary p-type work function metals include TiN, TaN, Ru, Mo, Al, WN, ZrSi 2 、MoSi 2 、TaSi 2 、NiSi 2 , WN, other suitable p-type work function materials, or combinations thereof. Exemplary n-type work function metals include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. The work function layer may include multiple layers. Fill metal 176 may include tungsten (W), aluminum (Al), copper (Cu), or another suitable conductive material.

[0077] The metal gate structure 170, the source / drain epitaxial structure 140 (and / or the epitaxial seed layer 146, if doped) on the opposite side of the metal gate structure 170, and the semiconductor layer 102 (and / or the epitaxial seed layer 146, if doped) in contact with the source / drain epitaxial structure 140 can collectively act as a transistor.

[0078] Fig.11 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. Please note that Fig.11 Some of the elements in Figures 1 to 10 Where elements are described, such elements are labeled identically and the related details will not be repeated for the sake of brevity.

[0079] like Fig.11 As shown in FIG. 1 , the air gap AG is vertically formed between the isolation layer 144 and the epitaxial seed layer 146. This is because when the epitaxial seed layer 146 is formed by a selective epitaxial growth (SEG) process, the SEG process can selectively grow semiconductor materials on semiconductor surfaces, such as the exposed surface of the semiconductor layer 102. However, the semiconductor material has a low growth rate or substantially zero growth rate on the dielectric surface, such as the exposed surface of the isolation layer 144. Therefore, in the case of Figure 5 During the formation of the epitaxial seed layer 146 as discussed in the above, the epitaxial seed layer 146 can be grown from the semiconductor layer 102 at a relatively high growth rate, and the epitaxial seed layer 146 can seal the air gap AG. Fig.11 The air gap AG between the isolation layer 144 and the epitaxial seed layer 146 can be beneficial to device performance because leakage current and parasitic capacitance can be reduced.

[0080] In some embodiments, the epitaxial seed layer 146 may contact the bottom portion of the sidewall of the bottommost semiconductor layer 102, and the source / drain epitaxial structure 140 may contact the top portion of the sidewall of the bottommost semiconductor layer 102. That is, all semiconductor layers 102 are in contact with the source / drain epitaxial structure 140. This may be beneficial to device performance because the source / drain epitaxial structure 140 may include a higher dopant concentration than the epitaxial seed layer 146, and the contact between the source / drain epitaxial structure 140 and the bottommost semiconductor layer 102 may increase the current flowing through the bottommost semiconductor layer 102. In some embodiments, the top surface of the epitaxial seed layer 146 is lower than the top surface of the bottommost semiconductor layer 102, and the bottom surface of the epitaxial seed layer 146 is higher than the top surface of the substrate 100.

[0081] Reference semiconductor layer 102. The height h of semiconductor layer 102 S The length I of the semiconductor layer 102 is in the range of about 2 nm to about 20 nm. SThe distance d between two adjacent semiconductor layers 102 is in the range of about 10 nm to about 200 nm. S It is in the range of about 2 nm to about 20 nm.

[0082] See gate structure 170. The pitch CPP of gate structure 170 is in the range of about 30 nm to about 90 nm.

[0083] See the epitaxial seed layer 146. The height h of the epitaxial seed layer 146 is SL The length I of the epitaxial seed layer 146 is in the range of about 1 nm to about 30 nm. SL It is in the range of about 5 nm to about 75 nm.

[0084] In some embodiments, the top surface of the epitaxial seed layer 146 may be a concave surface, such as Fig.11 In other embodiments, the top surface of the epitaxial seed layer 146 may be a convex surface or a flat surface. For example, a tangent line at the intersection between the top surface of the epitaxial seed layer 146 and the semiconductor layer 102 and a horizontal line substantially parallel to the top surface of the substrate 100 may form an angle θ T In some embodiments, the angle θ T It is in the range of about -70° to 70°.

[0085] In some embodiments, the bottom surface of the epitaxial seed layer 146 may be a concave surface, such as Fig.11 In other embodiments, the bottom surface of the epitaxial seed layer 146 may be a convex surface or a flat surface. For example, a tangent line at the intersection between the bottom surface of the epitaxial seed layer 146 and the semiconductor layer 102 and a horizontal line substantially parallel to the top surface of the substrate 100 may form an angle θ B In some embodiments, the angle θ B It is in the range of about -70° to about 70°.

[0086] See the isolation layer 144. The length I of the isolation layer 144 is Iso The height h of the isolation layer 144 is in the range of about 5 nm to about 75 nm. Iso In some embodiments, the isolation layer 144 may include a portion of the substrate 100, and the depth d of the isolation layer 144 in the substrate 100 is about 100 nm. Iso It is in the range of about 0 nm to about 30 nm.

[0087] In some embodiments, the top surface of the isolation layer 144 may be a concave surface, such as Fig.11In other embodiments, the top surface of the isolation layer 144 may be a convex surface or a flat surface. For example, a tangent line at the intersection between the top surface of the isolation layer 144 and the inner spacer 116 and a horizontal line substantially parallel to the top surface of the substrate 100 may form an angle θ I In some embodiments, the angle θ I It is in the range of about -70° to 70°.

[0088] See air gap AG. The height h of air gap AG gap The length I of the isolation layer 144 is in the range of about 0 nm to about 20 nm. gap It is in the range of about 0 nm to about 75 nm.

[0089] Fig. 12A and Fig. 12B is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. Please note that Fig.11 Some of the elements in Figures 1 to 10 Where elements are described, such elements are labeled identically and the related details will not be repeated for the sake of brevity.

[0090] exist Fig. 12A In FIG. 1 , the top surface of the isolation layer 144 is a convex surface. That is, the angle θ I Greater than 0°. Fig. 12B In FIG. 1 , the top surface of the isolation layer 144 is a concave surface. That is, the angle θ I In some embodiments, the bottommost inner spacer 116 may be exposed to the air gap AG. That is, the entirety of the isolation layer 144 is vertically separated from the epitaxial seed layer 146 via the air gap AG.

[0091] Fig.13 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. Please note that Fig.11 Some of the elements in Figures 1 to 10 For elements described herein, such elements are labeled identically and the related details will not be repeated for the sake of brevity. Fig.13 In the embodiment, the isolation layer 144 is in contact with the epitaxial seed layer 146. That is, no air gap is formed between the isolation layer 144 and the epitaxial seed layer 146.

[0092] Based on the aforementioned embodiments, it can be seen that the present disclosure provides advantages in manufacturing integrated circuits. However, it should be understood that other embodiments may provide additional advantages, and not all advantages are necessarily disclosed herein, and no specific advantages are required for all embodiments. Embodiments of the present disclosure include forming an epitaxial seed layer in the source / drain openings. The source / drain epitaxial structure is then formed above the epitaxial seed layer. Due to the lattice mismatch between the epitaxial seed layer and the source / drain epitaxial structure, strain is induced in the source / drain epitaxial structure, which in turn improves device performance. In some embodiments of the present disclosure, an air gap may be formed between the isolation layer and the epitaxial seed layer, and the air gap may be beneficial to device performance because leakage current and parasitic capacitance may be reduced.

[0093] In some embodiments of the present disclosure, a semiconductor device includes a substrate. A plurality of semiconductor channel layers are above the substrate. A gate structure covers each of the plurality of semiconductor channel layers. A plurality of source / drain epitaxial structures are on a plurality of opposite sides of the gate structure. A plurality of epitaxial seed layers are respectively below the plurality of source / drain epitaxial structures, wherein a lattice constant of the plurality of epitaxial seed layers is different from a lattice constant of the plurality of source / drain epitaxial structures.

[0094] In some embodiments, one of the plurality of epitaxial seed layers and one of the plurality of isolation layers are both in contact with a bottommost semiconductor channel layer among the plurality of semiconductor channel layers.

[0095] In some embodiments, one of the plurality of source / drain epitaxial structures is in contact with all of the plurality of semiconductor channel layers.

[0096] In some embodiments, the semiconductor device further includes epitaxial layers respectively in the substrate and vertically below the plurality of isolation layers.

[0097] In some embodiments, the plurality of epitaxial layers and the plurality of epitaxial seed layers are made of a same material.

[0098] In some embodiments, the semiconductor device further includes isolation layers respectively above the substrate and vertically below the plurality of epitaxial seed layers.

[0099] In some embodiments, an air gap is vertically between one of the plurality of epitaxial seed layers and one of the plurality of isolation layers.

[0100] In some embodiments, the semiconductor device further includes an inner spacer in contact with the gate structure and a bottom surface of a bottommost semiconductor channel layer among the plurality of semiconductor channel layers, wherein the inner spacer is exposed to the air gap.

[0101] In some embodiments of the present disclosure, a semiconductor device includes a substrate. A plurality of semiconductor channel layers are above the substrate. A gate structure covers each of the plurality of semiconductor channel layers. A plurality of source / drain epitaxial structures are on a plurality of opposite sides of the gate structure. Epitaxial seed layers are respectively below the plurality of source / drain epitaxial structures. A plurality of dielectric layers are respectively above the substrate and vertically below the plurality of epitaxial seed layers, wherein an air gap is vertically between one of the plurality of epitaxial seed layers and one of the plurality of dielectric layers.

[0102] In some embodiments, the plurality of source / drain epitaxial structures have a higher germanium concentration than the plurality of epitaxial seed layers.

[0103] In some embodiments, the epitaxial seed layer of the plurality of epitaxial seed layers has a recessed bottom surface, and the one of the plurality of dielectric layers has a recessed top surface.

[0104] In some embodiments, a top surface of an epitaxial seed layer among the plurality of epitaxial seed layers is lower than a top surface of a bottommost semiconductor channel layer among the plurality of semiconductor channel layers.

[0105] In some embodiments, the semiconductor device further includes epitaxial layers respectively in the substrate and contacting bottom surfaces of the dielectric layers, wherein the epitaxial layers and the epitaxial seed layers are made of a same material.

[0106] In some embodiments, an entirety of the one of the plurality of epitaxial seed layers is separated from the one of the plurality of dielectric layers by the air gap.

[0107] In some embodiments, a bottom surface of the plurality of epitaxial seed layers is higher than a top surface of the substrate.

[0108] In some embodiments of the present disclosure, a method includes: forming multiple semiconductor layers one above another above a substrate; performing an etching process to form a source / drain opening in the multiple semiconductor layers and the substrate; forming an epitaxial seed layer in the source / drain opening; forming a source / drain epitaxial structure above the epitaxial seed layer and in contact with the multiple semiconductor layers, wherein the source / drain epitaxial structure and the epitaxial seed layer are formed of different materials so that strain is generated in the source / drain epitaxial structure; and forming a gate structure above the multiple semiconductor layers.

[0109] In some embodiments, the step of forming the epitaxial seed layer includes the following steps: depositing an epitaxial material in the source / drain opening; and etching back the epitaxial material to expose the sidewalls of the semiconductor layers.

[0110] In some embodiments, the step of etching back the epitaxial material is performed until a bottommost semiconductor layer among the plurality of semiconductor layers is exposed.

[0111] In some embodiments, before the step of forming the epitaxial seed layer, the method further comprises the following steps: forming an epitaxial layer in a bottom portion of the source / drain opening; and forming an isolation layer over the epitaxial layer.

[0112] In some embodiments, an air gap is vertically formed between the epitaxial seed layer and the isolation layer.

[0113] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and such equivalent constructions may be variously modified, substituted, and replaced herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: Include: a substrate; a plurality of semiconductor channel layers above the substrate; a gate structure covering each of the plurality of semiconductor channel layers; a plurality of source / drain epitaxial structures on opposite sides of the gate structure; and A plurality of epitaxial seed layers are respectively disposed under the plurality of source / drain epitaxial structures, wherein a lattice constant of the plurality of epitaxial seed layers is different from a lattice constant of the plurality of source / drain epitaxial structures.

2. The semiconductor device according to claim 1, wherein One of the plurality of epitaxial seed layers is in contact with a bottommost semiconductor channel layer among the plurality of semiconductor channel layers.

3. The semiconductor device according to claim 1, wherein One of the plurality of source / drain epitaxial structures is in contact with all of the plurality of semiconductor channel layers.

4. The semiconductor device according to claim 1, wherein: Further included are a plurality of epitaxial layers respectively in the substrate and below the plurality of epitaxial seed layers, wherein the plurality of epitaxial seed layers are vertically spaced apart from the plurality of epitaxial layers.

5. The semiconductor device according to claim 1, wherein Further included are a plurality of isolation layers above the substrate and vertically below the plurality of epitaxial seed layers.

6. A semiconductor device, characterized in that: Include: a substrate; a plurality of semiconductor channel layers above the substrate; a gate structure covering each of the plurality of semiconductor channel layers; a plurality of source / drain epitaxial structures on opposite sides of the gate structure; a plurality of epitaxial seed layers respectively disposed below the plurality of source / drain epitaxial structures; and A plurality of dielectric layers are respectively disposed above the substrate and vertically below the plurality of epitaxial seed layers, wherein an air gap is vertically disposed between one of the plurality of epitaxial seed layers and one of the plurality of dielectric layers.

7. The semiconductor device according to claim 6, wherein: The one of the plurality of epitaxial seed layers has a recessed bottom surface, and the one of the plurality of dielectric layers has a recessed top surface.

8. The semiconductor device according to claim 6, wherein: A top surface of an epitaxial seed layer among the plurality of epitaxial seed layers is lower than a top surface of a bottommost semiconductor channel layer among the plurality of semiconductor channel layers.

9. The semiconductor device according to claim 6, wherein: A bottom surface of the plurality of epitaxial seed layers is higher than a top surface of the substrate.

10. A semiconductor device, characterized in that: Include: a substrate; a plurality of semiconductor channel layers above the substrate; a gate structure covering each of the plurality of semiconductor channel layers; a plurality of source / drain epitaxial structures on opposite sides of the gate structure; a plurality of epitaxial seed layers respectively disposed below the plurality of source / drain epitaxial structures; and A plurality of dielectric layers are respectively disposed above the substrate and vertically below the plurality of epitaxial seed layers, wherein an air gap is vertically disposed between one of the plurality of epitaxial seed layers and one of the plurality of dielectric layers, wherein a top surface of one of the plurality of epitaxial seed layers is lower than a top surface of a bottommost semiconductor channel layer among the plurality of semiconductor channel layers.

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