Semiconductor element

Abstract

A semiconductor device includes: a gate stack over a substrate; a metal dielectric pad over the gate stack; a gate mask over the metal dielectric pad; a first oxide layer over the substrate, a top surface of the first oxide layer being flush with a top surface of the gate mask; a dielectric layer over the gate mask and the first oxide layer, the dielectric layer being made of a material different from that of the gate mask; a second oxide layer over the dielectric layer; a first conductive feature extending through the first oxide layer, a top surface of the first conductive feature being flush with a top surface of the gate mask; and a second conductive feature extending through the second oxide layer and the dielectric layer, the second conductive feature being in contact with the first conductive feature.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers over a semiconductor substrate and patterning the various material layers using lithography to form circuit elements and components thereon.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, thereby allowing more components to be packed into a given area. However, as the minimum feature size decreases, additional challenges arise that may be addressed. Utility Model Content

[0004] In some embodiments, a semiconductor element includes: a gate stack located above a substrate; a metal dielectric liner located above the gate stack; a gate mask located above the metal dielectric liner; a first oxide layer located above the substrate, the top surface of the first oxide layer being flush with the top surface of the gate mask; a dielectric layer located above the gate mask and the first oxide layer, the dielectric layer being a different material from the gate mask; a second oxide layer located above the dielectric layer; a first conductive feature extending through the first oxide layer, the top surface of the first conductive feature being flush with the top surface of the gate mask; and a second conductive feature extending through the second oxide layer and the dielectric layer, the second conductive feature being in physical contact with the first conductive feature.

[0005] In some embodiments, a semiconductor device includes: a substrate; a first epitaxial source / drain region located in the substrate; a first interlayer dielectric located above the first epitaxial source / drain region; a gate stack located above the substrate and adjacent to the first interlayer dielectric; a gate mask located above the gate stack; a first source / drain plug passing through the first interlayer dielectric and electrically connected to the first epitaxial source / drain region; a dielectric layer located above the gate mask and the first interlayer dielectric; a second interlayer dielectric located above the dielectric layer; and a conductive feature passing through the second interlayer dielectric and the dielectric layer and contacting the first source / drain plug and the gate mask.

[0006] In some embodiments, a semiconductor element includes: a substrate; a first epitaxial region located in the substrate; a second epitaxial region located in the substrate; a first oxide layer located above the first epitaxial region and the second epitaxial region; a first gate stack located above the substrate; a second gate stack located above the substrate, wherein the first gate stack is inserted between the first epitaxial region and the second epitaxial region; a nitride mask located above the first gate stack; a first conductive feature located above the first epitaxial region; a second conductive feature located above the second epitaxial region; an etch stop layer located above the nitride mask and the first oxide layer; the second oxide layer located above the etch stop layer; a gate plug located above the first gate stack and in contact with the first gate stack; and a third conductive feature passing through the second oxide layer and the etch stop layer and in contact with the first conductive feature. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In practice, the sizes of various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 An example of a FinFET according to some embodiments is illustrated in a three-dimensional view;

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Fig. 8A , Figure 8B , Fig.9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig. 10C , Fig. 10D , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , Fig.13A , Fig. 13B , Fig.14A , Fig. 14B , Fig. 14C , Fig.15A , Fig. 15B , Fig.16A , Fig. 16B , Fig.17A , Fig. 17B , Fig.18A , Fig.18B , Fig.19A , Fig.19B , Fig. 20A , Fig. 20B , Fig.21A , Fig. 21B , Fig.22A , Fig. 22B , Fig.23A , Fig. 23B , Fig.24A , Fig. 24B , Fig.25A , Fig.25B , Fig.25C , Fig.25D , Fig.25E , Fig.25F , Fig.26A , Fig.26B , Fig.26C , Fig.26D , Fig.26E , Fig.26F , Fig.27A , Fig.27B , Fig.27C , Fig.27D , Fig.27E and Fig.27F is a cross-sectional view of an intermediate stage in fabricating a FinFET device according to some embodiments;

[0010] Figure 25G and Figure 26G is a schematic plan view of an intermediate stage of manufacturing a FinFET device according to some embodiments;

[0011] Fig.26H and Fig.26I is a diagram of various components at intermediate stages in fabricating a FinFET component according to some embodiments.

[0012]

Explanation of symbols

[0013] 50: Base material

[0014] 50N, 50P, 89: Area

[0015] 51: Divider

[0016] 52: Fin

[0017] 54: Insulation material

[0018] 56: Quarantine

[0019] 58: Channel area

[0020] 60: Virtual dielectric layer

[0021] 62: Virtual gate layer

[0022] 64: Mask layer

[0023] 72: Virtual Gate

[0024] 74:Mask

[0025] 80: Gate sealing spacer

[0026] 82: Source / drain region

[0027] 86: Gate spacer

[0028] 87: Contact Etch Stop Layer

[0029] 88, 106: ILD

[0030] 90, 118, 126, 126A, 126B, 126C, 126D, 128, 128M, 128R: Open

[0031] 91: Interface layer

[0032] 92: Gate dielectric layer

[0033] 94: Gate electrode

[0034] 94A: cushion layer

[0035] 94B: Work function adjustment layer

[0036] 94C: Conductive filling layer

[0037] 96: Gate Stack

[0038] 98: Groove

[0039] 99: Gate contact layer

[0040] 100:Metal dielectric liner

[0041] 102, 104: dielectric layer

[0042] 120: Silicide layer

[0043] 122, 130, 130A, 130B, 130C, 130D, 132, 132D, 132M, 132R:

[0044] Conductive characteristics

[0045] 134: Interconnection structure

[0046] 136: Metallization layer

[0047] 136P: Power rail

[0048] AA, BB, CC: cross section DETAILED DESCRIPTION

[0049] The following disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these specific embodiments or examples are only examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are directly contacted, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be directly contacted. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0050] Additionally, for ease of description, spatially relative terms, such as "below," "beneath," "bottom," "above," "upper," and the like, may be used herein to describe the relationship of one component or feature to another component or feature as illustrated in the accompanying drawings. The spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the drawings. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein interpreted accordingly.

[0051] Embodiments are described in the specific context of integrated circuit dies containing fin field-effect transistors (finFETs). However, various embodiments may be applied to dies containing other types of transistors (e.g., nanoFETs, such as nanowire FETs, nanosheet FETs, or the like), planar transistors, or the like) instead of or in combination with finFETs. Furthermore, various embodiments presented herein are discussed in the context of fin field effect transistor (FinFET) elements formed using a gate-last process. In other embodiments, a gate-first process may be used.

[0052] Embodiments herein provide the formation of a contact plug structure of a semiconductor element and a method for forming the same. According to some embodiments, an etch stop layer including a dielectric material is formed above a gate stack of a semiconductor element. The dielectric material is selected to have a high etch selectivity, wherein a gate mask overlies the gate stack. One or more dielectric layers may be formed above the etch stop layer. An opening is etched in the overlying dielectric layer, and a conductive feature is formed above the source / drain contact plug and electrically connected to the source / drain contact plug. The conductive feature may be formed to have a shape that improves electrical connection with the corresponding source / drain contact plug and reduces resistance. The high selectivity of the etch stop layer facilitates the formation of an opening (and the conductive feature therein), so that the gate mask remains unetched and reduces leakage between the gate stack and the conductive feature (and the source / drain contact plug). The various embodiments discussed herein allow for various shapes of conductive features (including extending directly above some gate stacks) while improving the electrical performance of the semiconductor element.

[0053] Figure 1 An example of a FinFET according to some embodiments is illustrated in a three-dimensional view. The FinFET includes a fin 52 on a substrate 50 (e.g., a semiconductor substrate). An isolation region 56 is disposed in the substrate 50, and the fin 52 protrudes above and between adjacent isolation regions 56. Although the isolation region 56 is described / illustrated as being separate from the substrate 50, as used herein, the term "substrate" may be used to refer only to the semiconductor substrate or the semiconductor substrate including the isolation region. Additionally, although the fin 52 is described as being a single continuous material of the substrate 50, the fin 52 and / or the substrate 50 may include a single material or multiple materials. In this context, the fin 52 refers to the portion extending between adjacent isolation regions 56.

[0054] Gate dielectric layer 92 is along the sidewalls of fin 52 and over the top surface of fin 52, and gate electrode 94 is over gate dielectric layer 92. Source / drain regions 82 are disposed on opposite sides of fin 52 relative to gate dielectric layer 92 and gate electrode 94. Figure 1 Reference cross sections used in the following figures are further described. Cross section AA is along the longitudinal axis of the gate electrode 94 and in a direction, for example, perpendicular to the direction of current flow between the source / drain regions 82 of the FinFET. Cross section BB is perpendicular to cross section AA and along the longitudinal axis of the fin 52 and in a direction of current flow between the source / drain regions 82 of the FinFET. Cross section CC is parallel to cross section AA and extends through the source / drain regions 82 of the FinFET. For clarity, the following figures refer to these reference cross sections.

[0055] Figures 2 to 27F 1 is a cross-sectional view, a plan view, and a diagram of an intermediate stage of manufacturing a FinFET device according to some embodiments. In addition to multiple fins / FinFETs, Figures 2 to 7 Instructions along the Figure 1 In addition to multiple fins / FinFETs, FIG. 8A to FIG. 24A , Fig.25A , Fig.25C , Fig.25E , Fig.26A , Fig.26C , Fig.26E , Fig.27A , Fig.27C and Fig.27E It is along Figure 1 In addition to the plurality of gates, FIG. 8B to FIG. 24B , Fig. 14C , Fig.25B , Fig.25D , Fig.25F , Fig.26B , Fig.26D , Fig.26F , Fig.27B , Fig.27D and Fig.27F It is along Figure 1 In addition to multiple fins / FinFETs, Fig. 10C and Fig. 10D It is along Figure 1 The reference cross section CC illustrated in FIG. Figure 25G and Figure 26G Describe a schematic top view (eg, plan view). Fig.26H and Fig.26I is a diagram of various components formed around a FinFET component and electrically connected to the FinFET component according to some embodiments.

[0056] exist Figure 2In the embodiment, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, and the semiconductor substrate may be doped (e.g., doped with a p-type or n-type dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a semiconductor material layer formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is disposed on a substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; a compound semiconductor, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof.

[0057] Substrate 50 has region 50N and region 50P. Region 50N can be used to form n-type devices, such as NMOS transistors, for example, n-type FinFETs. Region 50P can be used to form p-type devices, such as PMOS transistors, for example, p-type FinFETs. Region 50N can be physically separated from region 50P (as shown by separator 51), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be placed between region 50N and region 50P.

[0058] exist Figure 3 In the embodiment of the present invention, fins 52 are formed in substrate 50. Fins 52 are semiconductor strips. In some embodiments, fins 52 can be formed in substrate 50 by etching trenches in substrate 50. Etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), combinations thereof, or the like. The etching process can be anisotropic.

[0059] The fin 52 may be formed using any suitable method. For example, the fin 52 may be formed using one or more lithography processes including a double patterning or multi-patterning process. Typically, the double patterning or multi-patterning process combines photolithography with a self-alignment process, allowing the creation of a pattern having a pitch smaller than that obtainable using a single direct photolithography process, for example. For example, in one embodiment, a sacrificial layer is formed over the substrate 50 and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used as a mask to form the fin 52.

[0060] exist Figure 4 , an insulating material 54 is formed over the substrate 50 and between adjacent fins 52. The insulating material 54 may be an oxide such as silicon oxide, a nitride, a combination thereof, or the like, and may be formed using high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system and post-curing to convert it to another material such as an oxide), a combination thereof, or the like. Other insulating materials formed using any acceptable process may be used. In the illustrated embodiment, the insulating material 54 is silicon oxide formed using an FCVD process. Once the insulating material is formed, an annealing process may be performed. In an embodiment, the insulating material 54 is formed such that excess insulating material 54 covers the fins 52. Although the insulating material 54 is illustrated as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not shown) may first be formed along the surface of the substrate 50 and the fins 52. Thereafter, a fill material such as those discussed above may be formed over the liner.

[0061] exist Figure 5 In the process, a removal process is applied to the insulating material 54 to remove the excess portion of the insulating material 54 above the fin 52. In some embodiments, a planarization process may be utilized, such as a chemical mechanical polish (CMP) process, an etch-back process, a combination thereof, or the like. The planarization process exposes the fin 52 so that after the planarization process is completed, the top surface of the fin 52 and the top surface of the insulating material 54 are substantially coplanar or flush (within the process variation range of the planarization process).

[0062] exist Figure 6 Insulating material 54 (see Figure 5 ) are recessed to form shallow trench isolation (STI) regions 56. Insulating material 54 is recessed so that upper portions of fins 52 in regions 50N and 50P protrude from between adjacent STI regions 56. In addition, the top surface of STI regions 56 may have a flat surface as described, a convex surface, a concave surface (such as a dished surface), or a combination thereof. The top surface of STI regions 56 may be formed to be flat, convex, and / or concave using appropriate etching. STI regions 56 may be recessed using an acceptable etching process, such as an etching process that is selective to the material of insulating material 54 (e.g., etches the material of insulating material 54 at a faster rate than the material of fin 52). For example, chemical oxide removal using a suitable etching process such as dilute hydrofluoric acid (dHF) may be used.

[0063] Reference Figures 2 to 6 The process described is only one example of how fin 52 may be formed. In some embodiments, the fin may be formed using an epitaxial growth process. For example, a dielectric layer may be formed over the top surface of substrate 50, and a trench may be etched through the dielectric layer to expose the underlying substrate 50. A homoepitaxial structure may be epitaxially grown in the trench, and the dielectric layer may be recessed so that the homoepitaxial structure protrudes from the dielectric layer to form the fin. Additionally, in some embodiments, a heteroepitaxial structure may be used for the fin. For example, Figure 5 The fin 52 in the substrate 50 may be recessed, and a material different from the fin 52 may be epitaxially grown over the recessed fin 52. In such embodiments, the fin includes a recessed material and an epitaxially grown material disposed over the recessed material. In further embodiments, a dielectric layer may be formed over the top surface of the substrate 50, and a trench may be etched through the dielectric layer. Subsequently, a heteroepitaxial structure may be epitaxially grown in the trench using a material different from the substrate 50, and the dielectric layer may be recessed so that the heteroepitaxial structure protrudes from the dielectric layer to form a fin. In some embodiments of epitaxial growth of homoepitaxial or heteroepitaxial structures, although in-situ doping and implantation doping may be used together, the epitaxially grown material may be in-situ doped during growth, which may avoid prior and subsequent implantation.

[0064] Furthermore, it may be advantageous to epitaxially grow a different material in region 50N than in region 50P. In various embodiments, the upper portion of fin 52 may be made of silicon germanium (Si x Ge 1-x , where x may be in the range of 0 to 1), silicon carbide, pure or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, or the like. For example, available materials for forming III-V compound semiconductors include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like.

[0065] In addition, Figure 6In the embodiment of the present invention, appropriate wells (not shown) may be formed in the fin 52 and / or the substrate 50. In some embodiments, a P well may be formed in the region 50N, and an N well may be formed in the region 50P. In some embodiments, a P well or an N well is formed in both the region 50N and the region 50P. In embodiments with different well types, a photoresist or other mask (not shown) may be used to implement different implantation steps for the region 50N and the region 50P. For example, a first photoresist may be formed over the fin 52 and the STI region 56 in both the region 50N and the region 50P. The first photoresist is patterned to expose the region 50P of the substrate 50. The first photoresist may be formed by using a spin coating technique and may be patterned using an acceptable photolithography technique. Once the first photoresist is patterned, n-type impurity implantation is performed in the region 50P, and the remaining portion of the first photoresist acts as a mask to substantially prevent n-type impurities from being implanted into the region 50N. The n-type impurity may be phosphorus, arsenic, antimony or the like, and the dosage implanted into the region 50P is equal to or less than 10 15 cm -2 , such as between about 10 12 cm -2 With about 10 15 cm -2 In some embodiments, the n-type impurities may be implanted at an implantation energy of about 1 keV to about 10 keV. After implantation, the first photoresist is removed, such as by an acceptable ashing process followed by a wet cleaning process.

[0066] After implanting region 50P, a second photoresist is formed over fins 52 and STI regions 56 in both region 50P and region 50N. The second photoresist is patterned to expose region 50N of substrate 50. The second photoresist may be formed using a spin coating technique and may be patterned using an acceptable photolithography technique. Once the second photoresist is patterned, p-type impurity implantation is performed in region 50N, while the remaining portion of the second photoresist acts as a mask to substantially prevent p-type impurities from being implanted into region 50P. The p-type impurity may be boron, BF 2 , indium or the like, the dosage implanted into the region 50N is equal to or less than 10 15 cm -2 , such as between about 10 12 cm -2 With about 10 15 cm -2 In some embodiments, the p-type impurities may be implanted at an implantation energy of about 1 keV to about 10 keV. After implantation, the second photoresist may be removed, such as by an acceptable ashing process followed by a wet cleaning process.

[0067] After performing the implantation of regions 50N and 50P, an annealing process may be performed to activate the implanted p-type and / or n-type impurities. In some embodiments, although in-situ doping and implantation doping may be used together, the growth material of the epitaxial fin may be in-situ doped during growth, which may avoid implantation.

[0068] exist Figure 7 In the embodiment of the present invention, a dummy dielectric layer 60 is formed on the fin 52. The dummy dielectric layer 60 may be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to an acceptable technique. A dummy gate layer 62 is formed over the dummy dielectric layer 60, and a mask layer 64 is formed over the dummy gate layer 62. The dummy gate layer 62 may be deposited over the dummy dielectric layer 60, and then planarized using, for example, a CMP process. The mask layer 64 may be deposited over the dummy gate layer 62. The dummy gate layer 62 may be a conductive material, and may be selected from a group including amorphous silicon, polycrystalline silicon (polycrystalline-silicon / polysilicon), polycrystalline silicon germanium (poly-crystalline silicon-germanium / poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 62 may be deposited using physical vapor deposition (PVD), CVD, sputtering deposition, or other known techniques in the art for depositing conductive materials. The dummy gate layer 62 may be made of other materials having a higher etch selectivity than the material of the STI region 56. The mask layer 64 may include, for example, one or more layers of silicon oxide, SiN, SiON, combinations thereof, or the like. In some embodiments, the mask layer 64 may include a silicon nitride layer and a silicon oxide layer above the silicon nitride layer. In some embodiments, a single dummy gate layer 62 and a single mask layer 64 are formed across the region 50N and the region 50P. It should be noted that the dummy dielectric layer 60 is shown as covering only the fin 52 for illustration purposes only. In some embodiments, the dummy dielectric layer 60 may be deposited so that the dummy dielectric layer 60 covers the STI region 56, thereby extending between the dummy gate layer 62 and the STI region 56.

[0069] FIG. 8A to FIG. 26F Various additional steps for fabricating FinFET elements according to some embodiments are described. These figures illustrate features in either region 50N and region 50P. For example, the structures illustrated may apply to both region 50N and region 50P. The differences in the structures of region 50N and region 50P, if any, are described in the text of each figure.

[0070] exist Fig. 8A and Figure 8B In the embodiment, the mask layer 64 may be patterned using acceptable photolithography and etching techniques (see Figure 7 ) to form a mask 74. In some embodiments, the etching technique may include one or more anisotropic etching processes, such as reactive ion etching (RIE), neutral beam etching (NBE), a combination thereof, or the like. Subsequently, the pattern of the mask 74 may be transferred to the dummy gate layer 62 (see Figure 7 ) to form a dummy gate 72. In some embodiments, the pattern of the mask 74 can also be transferred to the dummy dielectric layer 60 using an acceptable etching technique. The dummy gate 72 covers the channel region 58 of the fin 52. The pattern of the mask 74 can be used to physically separate each of the dummy gates 72 from an adjacent dummy gate. The dummy gate 72 can also have a length direction that is substantially perpendicular to the length direction of a corresponding one of the fins 52. As described in more detail below, the dummy gate 72 is a sacrificial gate and is subsequently replaced by a replacement gate. Therefore, the dummy gate 72 can also be referred to as a sacrificial gate. In other embodiments, some of the dummy gates 72 are not replaced, but remain in the final structure of the embodiment FinFET element.

[0071] In addition, Fig. 8A and Figure 8B In the embodiment, the gate sealing spacer 80 can be formed on the exposed surface of the dummy gate 72, the mask 74 and / or the fin 52. Thermal oxidation or deposition and subsequent anisotropic etching can form the gate sealing spacer 80. The gate sealing spacer 80 may include silicon oxide, silicon nitride, SiCN, SiOC, SiOCN, a combination thereof, or the like. After forming the gate sealing spacer 80, implantation of a lightly doped source / drain (LDD) region (not explicitly described) can be performed. In embodiments with different device types, similar to the above in Figure 6 50P, and an appropriate type of impurity (e.g., p-type) may be implanted into the exposed fins 52 in the regions 50P. The mask may then be removed. A mask such as a photoresist may then be formed over the regions 50P, while exposing the regions 50N, and an appropriate type of impurity (e.g., n-type) may be implanted into the exposed fins 52 in the regions 50N. The mask may then be removed. The n-type impurity may be any of the n-type impurities discussed previously, and the p-type impurity may be any of the p-type impurities discussed previously. The lightly doped source / drain regions may have a doping capacity of about 10 12 cm -2 to about 10 16 cm -2 In some embodiments, suitable impurities may be implanted at an implantation energy of about 1 keV to about 10 keV. Annealing may be used to activate the implanted impurities.

[0072] exist Fig.9A and Fig. 9B , a gate spacer 86 is formed on the gate sealing spacer 80 along the sidewalls of the dummy gate 72 and the mask 74. The gate spacer 86 can be formed by conformal deposition of an insulating material and subsequent anisotropic etching of the insulating material. The insulating material of the gate spacer 86 may include silicon oxide, silicon nitride, SiCN, SiOC, SiOCN, a combination thereof, or the like. In some embodiments, the gate spacer 86 may include a plurality of layers (not shown) so that the layers include different materials.

[0073] It should be noted that the above disclosure generally describes processes for forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be utilized, a different sequence of steps may be utilized (e.g., gate seal spacer 80 may not be etched prior to forming gate spacer 86, thereby producing an "L-shaped" gate seal spacer, spacers may be formed and removed, and / or the like). In addition, different structures and steps may be used to form n-type and p-type devices. For example, LDD regions for n-type devices may be formed prior to forming gate seal spacer 80, while LDD regions for p-type devices may be formed after forming gate seal spacer 80.

[0074] exist Fig. 10A and Fig. 10B In the embodiment, epitaxial source / drain regions 82 are formed in the fins 52 to apply stress in the corresponding channel regions 58 to improve device performance. The epitaxial source / drain regions 82 are formed in the fins 52 so that each dummy gate 72 is disposed between a corresponding adjacent pair of epitaxial source / drain regions 82. In some embodiments, the epitaxial source / drain regions 82 may extend into the fins 52 and may also penetrate the fins 52. In some embodiments, gate spacers 86 are used to separate the epitaxial source / drain regions 82 from the dummy gates 72 by an appropriate lateral distance so that the epitaxial source / drain regions 82 do not short-circuit a subsequently formed gate of the embodiment FinFET device.

[0075] The epitaxial source / drain region 82 in the region 50N can be formed by masking the region 50P and etching the source / drain region of the fin 52 in the region 50N to form a groove in the fin 52. Subsequently, the epitaxial source / drain region 82 in the region 50N is epitaxially grown in the groove. The epitaxial source / drain region 82 can include any acceptable material, such as a material suitable for n-type FinFET. For example, if the fin 52 is silicon, the epitaxial source / drain region 82 in the region 50N can include a material that applies tensile strain in the channel region 58, such as silicon, SiC, SiCP, SiP, a combination thereof, or the like. The epitaxial source / drain region 82 in the region 50N can have a surface that protrudes from the corresponding surface of the fin 52 and can have a small face.

[0076] The epitaxial source / drain region 82 in the region 50P may be formed by masking the region 50N and etching the source / drain region of the fin 52 in the region 50P to form a recess in the fin 52. Subsequently, the epitaxial source / drain region 82 in the region 50P is epitaxially grown in the recess. The epitaxial source / drain region 82 may include any acceptable material, such as a material suitable for a p-type FinFET. For example, if the fin 52 is silicon, the epitaxial source / drain region 82 in the region 50P may include a material that applies compressive strain in the channel region 58, such as SiGe, SiGeB, Ge, GeSn, a combination thereof, or the like. The epitaxial source / drain region 82 in the region 50P may also have a surface that protrudes from the corresponding surface of the fin 52 and may have a small face.

[0077] The epitaxial source / drain regions 82 and / or the fins 52 may be implanted with dopants to form source / drain regions, similar to the process previously discussed for forming lightly doped source / drain regions, followed by annealing. The source / drain regions 82 may have a surface area of ​​about 10 19 cm -3 With about 10 21 cm -3 The n-type and / or p-type impurities used for the epitaxial source / drain regions 82 may be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 82 may be in-situ doped during growth.

[0078] As a result of the epitaxial process used to form epitaxial source / drain regions 82 in regions 50N and 50P, the upper surfaces of epitaxial source / drain regions 82 have facets that extend laterally outward beyond the sidewalls of fin 52. In some embodiments, these facets result in the merging of adjacent epitaxial source / drain regions 82 of the same FinFET, such as Fig. 10C In other embodiments, after the epitaxy process is completed, adjacent epitaxy source / drain regions 82 remain separated, such as Fig. 10D As described. Fig. 10C and Fig. 10DIn the embodiment illustrated in FIG. 1 , gate spacer 86 is formed to cover a portion of the sidewalls of fin 52 extending over STI region 56, thereby blocking epitaxial growth. In other embodiments, the spacer etch used to form gate spacer 86 can be adjusted to remove spacer material from the sidewalls of fin 52 to allow the epitaxial growth region to extend to the surface of STI region 56.

[0079] exist Fig.11A and Fig. 11B In the ILD 88 is deposited on Fig. 10A and Fig. 10B . ILD 88 may be formed of a dielectric material and may be deposited using any suitable method, such as CVD, plasma-enhanced CVD (PECVD), FCVD, combinations thereof, or the like. The dielectric material may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), combinations thereof, or the like. Other insulating materials formed using any acceptable process may also be used. In some embodiments, a contact etch stop layer (CESL) 87 is disposed between ILD 88 and epitaxial source / drain regions 82, mask 74, and gate spacer 86. The CESL 87 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, combinations thereof, or the like, that has a different etch rate than the material of the overlying ILD 88 .

[0080] exist Fig. 12A and Fig. 12B In the embodiment, a planarization process such as a CMP process may be performed to make the top surface of the ILD 88 flush with the top surface of the dummy gate 72 or the mask 74 (see FIG. Fig.11A and Fig. 11B ). The planarization process may also remove the mask 74 on the dummy gate 72 and portions of the gate sealing spacer 80 and gate spacer 86 along the sidewalls of the mask 74. After the planarization process, within the process variation range of the planarization process, the top surfaces of the dummy gate 72, the gate sealing spacer 80, the gate spacer 86, and the ILD 88 are substantially coplanar or flush with each other. Therefore, the top surface of the dummy gate 72 is exposed through the ILD 88. In some embodiments, the mask 74 may remain, in which case the planarization process makes the top surface of the ILD 88 flush with the top surface of the mask 74.

[0081] exist Fig.13A and Fig. 13B In the etching step, the dummy gate 72 and the mask 74 (if present) are removed in an etching step so that an opening 90 is formed. In some embodiments, portions of the dummy dielectric layer 60 in the opening 90 may also be removed. In other embodiments, only the dummy gate 72 is removed, and the dummy dielectric layer 60 remains and is exposed by the opening 90. In some embodiments, the dummy dielectric layer 60 is removed from the opening 90 in a first region of the die (e.g., a core logic region) and remains in the opening 90 in a second region of the die (e.g., an input / output region). In some embodiments, the dummy gate 72 is removed using an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the dummy gate 72 without etching the ILD 88 or the gate spacer 86. Each opening 90 exposes a channel region 58 of a corresponding fin 52. Each channel region 58 is disposed between adjacent pairs of epitaxial source / drain regions 82. During removal, the dummy dielectric layer 60 may serve as an etch stop layer when etching the dummy gate 72. Subsequently, after removing the dummy gate 72 , the dummy dielectric layer 60 may be removed as appropriate.

[0082] exist Fig.14A and Fig. 14B In the opening 90, an interface layer 91, a gate dielectric layer 92 and a gate electrode 94 are formed (see Fig.13A and Fig. 13B ) to form a gate stack 96. The gate stack 96 may also be referred to as a replacement gate stack. Fig. 14C illustrate Fig. 14B Detailed view of region 89. In some embodiments, interface layer 91 is formed in opening 90 (see Fig.13A and Fig. 13B ). The interface layer 91 may include silicon oxide and may be formed using a chemical deposition process such as ALD, CVD, or the like, or using an oxidation process. In some embodiments where the interface layer 91 is formed using a deposition process, the interface layer 91 extends along the exposed surfaces of the fin 52, the STI region 56, and the gate sealing spacer 80. In some embodiments where the interface layer 91 is formed using an oxidation process, the interface layer 91 extends along the exposed surfaces of the fin 52 and does not extend along the exposed surfaces of the STI region 56 and the gate sealing spacer 80. In some embodiments, the interface layer 91 has a thickness of less than about Thickness.

[0083] In some embodiments, a gate dielectric layer 92 is deposited in the opening 90 above the interface layer 91. The gate dielectric layer 92 may also be formed on the top surface of the ILD 88. According to some embodiments, the gate dielectric layer 92 includes silicon oxide, silicon nitride, or a multilayer thereof. In some embodiments, the gate dielectric layer 92 includes a high-k dielectric material, and in these embodiments, the gate dielectric layer 92 may have a k value greater than about 7.0 and may include a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The formation method of the gate dielectric layer 92 may include molecular-beam deposition (MBD), ALD, PECVD, combinations thereof, or the like.

[0084] In addition, Fig.14A and Fig. 14B In the embodiment, gate electrode 94 is deposited over gate dielectric layer 92 and fills the remaining portion of opening 90 (see Fig.13A and Fig. 13B ). Fig. 14B The single-layer gate electrode 94 is described in the figure, but the gate electrode 94 may include any number of liner layers 94A, any number of work function adjustment layers 94B and conductive filling layers 94C, such as Fig. 14C As described. The liner layer 94A may include TiN, TiO, TaN, TaC, combinations thereof, multiple layers thereof, or the like, and may be formed using PVD, CVD, ALD, combinations thereof, or the like. In the region 50N, the work function regulating layer 94B may include Ti, Ag, Al, TiAl, TiAlN, TiAlC, TaC, TaCN, TaSiN, TaAlC, Mn, Zr, combinations thereof, multiple layers thereof, or the like, and may be formed using PVD, CVD, ALD, combinations thereof, or the like. In the region 50P, the work function regulating layer 94B may include TiN, WN, TaN, Ru, Co, combinations thereof, multiple layers thereof, or the like, and may be formed using PVD, CVD, ALD, combinations thereof, or the like. In some embodiments, the conductive filling layer 94C may include Co, Ru, Al, Ag, Au, W, Ni, Ti, Cu, Mn, Pd, Re, Ir, Pt, Zr, alloys thereof, combinations thereof, multilayers thereof, or the like, and may be formed using PVD, CVD, ALD, electroplating, combinations thereof, or the like.

[0085] In the filling opening 90 (see Fig.13A and Fig. 13B), a planarization process such as CMP may be performed to remove excess portions of the gate dielectric layer 92, the gate electrode 94, and / or the interface layer 91 that are above the top surface of the ILD 88. Thus, the remaining portions of the gate electrode 94, the gate dielectric layer 92, and the interface layer 91 form a gate stack 96 of the embodiment FinFET device. The gate stack 96 may extend along the sidewalls of the channel region 58 of the fin 52.

[0086] The formation of the gate dielectric layer 92 in the region 50N and the region 50P may occur simultaneously so that the gate dielectric layer 92 in each region is formed of the same material. In other embodiments, the gate dielectric layer 92 in each region may be formed using different processes so that the gate dielectric layer 92 in different regions may be formed of different materials. The formation of the conductive fill layer 94C in the region 50N and the region 50P may occur simultaneously so that the conductive fill layer 94C in each region is formed of the same material. In other embodiments, the conductive fill layer 94C in each region may be formed using different processes so that the conductive fill layer 94C in different regions may be formed of different materials. When different processes are used, various masking steps may be used to mask and expose the appropriate regions.

[0087] exist Fig.15A and Fig. 15B In some embodiments, the gate stack 96 is recessed below the top surface of the ILD 88 to form a recess 98. In some embodiments, the gate stack 96 is recessed below the top surface of the ILD 88. In some embodiments, the gate stack 96 is recessed to a depth between about 10 nm and about 100 nm. In some embodiments, the gate stack 96 is recessed using one or more etching processes. The one or more etching processes may include one or more dry etching processes, one or more wet etching processes, combinations thereof, or the like. The one or more etching processes may include an anisotropic etching process. In some embodiments, a etchant such as Cl may be used. 2 , HCl, F 2 , HF, CF 4 、SiCl 4 , CH x F y , Ar, N 2 , O 2 , BCl 3 NF 3 , combinations thereof, or the like to perform one or more etching processes.

[0088] Once the gate stack 96 has been recessed, a gate contact layer 99 may be formed of tungsten, such as fluorine-free tungsten (FFW), which may be deposited using a selective deposition process, such as a selective CVD process. The gate contact layer 99 may be considered to be part of the gate stack 96. However, the gate contact layer 99 may include other conductive materials, such as ruthenium, cobalt, copper, molybdenum, nickel, combinations thereof, or the like, and may be deposited using a suitable deposition process (e.g., ALD, CVD, PVD, or the like). As illustrated, the gate contact layer 99 may extend mostly or substantially between the gate seal spacer 80 and a portion or all of the surface of the gate dielectric layer 92 and the interfacial layer 91 (if exposed). The FFW may have a thickness of 8 nm to 10 nm, such as 8.5 nm.

[0089] According to some embodiments, Fig.16A and Fig. 16B In the embodiment of the present invention, a metal dielectric liner 100 is deposited in the recess 98 and above the recessed gate stack 96 (e.g., along the gate contact layer 99), as appropriate. The metal dielectric liner 100 will provide a self-alignment advantage during the subsequent formation of the gate contact plug. In some embodiments, the metal dielectric liner 100 includes a metal oxide or a silicate, wherein the metal may be hafnium, aluminum, zirconium, or the like. For example, the metal dielectric liner 100 may be hafnium oxide, aluminum oxide, or zirconium silicate. The metal dielectric liner 100 may be formed using ALD, MBD, PECVD, or any suitable method, and may have a thickness ranging from 1 nm to 4 nm, such as ranging from 1 nm to 2 nm or ranging from 2 nm to 4 nm.

[0090] exist Fig.17A and Fig. 17B In the embodiment, the dielectric layer 102 is formed in the groove 98 (see Fig.15A and Fig. 15B ) and ILD 88 and metal dielectric liner 100 (if present). In some embodiments, dielectric layer 102 overfills recess 98. In some embodiments, dielectric layer 102 includes a material that does not include oxygen. In some embodiments, dielectric layer 102 includes silicon nitride (SiN), silicon carbide (SiC), silicon carbonitride (SiCN), combinations thereof, or the like, and may be formed using ALD, CVD, combinations thereof, or the like. According to some embodiments discussed herein, the dielectric layer includes silicon nitride and may be referred to as a gate mask or a nitride mask.

[0091] exist Fig.18A and Fig.18BIn the embodiment of the present invention, a planarization process is performed on the dielectric layer 102 and the metal dielectric liner 100 (if present) to expose the top surface of the ILD 88. After the planarization process, within the process variation range of the planarization process, the top surfaces of the dielectric layer 102, the metal dielectric liner 100, and the ILD 88 are substantially flush or coplanar. In some embodiments, the planarization process may include a CMP process, an etch-back process, a polishing process, a combination thereof, or the like. After the planarization process, the dielectric layer 102 has a thickness between about 10 nm and about 100 nm. In some embodiments (not specifically described), the dielectric layer 102 may be a multilayer dielectric including nitride and oxide. In such embodiments, after the planarization process is performed, the topmost layer is silicon nitride.

[0092] Fig.19A and Fig.19B 1 and 12. The patterning process of ILD 88 and CESL 87 to form opening 118 is described. Opening 118 exposes the top surface of the corresponding epitaxial source / drain region 82. In some embodiments, the patterning process may include one or more suitable etching processes while using the patterned mask stack as an etching mask. The one or more etching processes may include one or more dry etching processes or the like. The etching process may be anisotropic. In some embodiments, a CF 4 , CHF 3 , CH 2 F 2 , C 4 F 6 , C 4 F 8 , Ar, O 2 、N 2 , H 2 , combinations thereof, or the like to perform one or more etching processes.

[0093] In some embodiments, after the opening 118 is formed, the remaining portion of the patterned mask stack is removed using, for example, a suitable etching process that is selective to the remaining material of the patterned mask stack. In some embodiments, the etching process includes a dry etching process, a wet etching process, a combination thereof, or the like. In some embodiments, a molten metal such as HCl, H 2 O 2 , combinations thereof, or the like to perform a suitable etching process.

[0094] exist Fig. 20A and Fig. 20BIn the embodiment of the present invention, after forming the opening 118, a silicide layer 120 is formed through the opening 118 above the epitaxial source / drain region 82. In some embodiments, a metal material is deposited in the opening 118. The metal material may include Ti, Co, Ni, NiCo, Pt, NiPt, Ir, PtIr, Er, Yb, Pd, Rh, Nb, a combination thereof, or the like, and may be formed using PVD, sputtering, a combination thereof, or the like. Subsequently, an annealing process is performed to form the silicide layer 120. In some embodiments where the epitaxial source / drain region 82 includes silicon, the annealing process causes the metal material to react with the silicon to form a silicide of the metal material at the interface between the metal material and the epitaxial source / drain region 82. After forming the silicide layer 120, for example, the unreacted portion of the metal material may be removed using a suitable removal process, such as a suitable etching process, as appropriate.

[0095] After forming the silicide layer 120, a conductive feature 122 is formed in the opening 118. The conductive feature 122 provides an electrical connection to the corresponding epitaxial source / drain region 82. In some embodiments, the conductive feature 122 is formed by first forming a barrier layer (not shown separately) in the opening 118. The barrier layer may extend along the bottom and sidewalls of the opening 118. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, combinations thereof, multiple layers thereof, or the like, and may be formed using ALD, CVD, PVD, sputtering, combinations thereof, or the like. Subsequently, an adhesion layer (not specifically described) is formed over the barrier layer within the opening 118. The adhesion layer may include cobalt, ruthenium, alloys thereof, combinations thereof, multiple layers thereof, or the like, and may be formed using ALD, CVD, PVD, sputtering, combinations thereof, or the like. After forming the adhesion layer, a seed layer (not shown separately) is formed over the adhesion layer within the opening 118. The seed layer may include copper, titanium, nickel, gold, manganese, combinations thereof, multiple layers thereof, or the like, and may be formed using ALD, CVD, PVD, sputtering, combinations thereof, or the like. Subsequently, a conductive fill material (not separately shown) is formed over the seed layer within the opening 118. In some embodiments, the conductive fill material overfills the opening 118. The conductive fill material may include copper, aluminum, tungsten, ruthenium, cobalt, combinations thereof, alloys thereof, multiple layers thereof, or the like, and may be formed using, for example, electroplating, ALD, CVD, PVD, or other suitable methods.

[0096] Still refer to Fig. 20A and Fig. 20BAfter forming the conductive filling material, a planarization process is performed to remove the barrier layer, the adhesion layer, the seed layer, and the portion of the conductive filling material that overfills the opening 118 and is disposed above the dielectric layer 102. The remaining portions of the barrier layer, the adhesion layer, the seed layer, and the conductive filling material form a conductive feature 122 in the opening 118. The planarization process may include a CMP process, an etch-back process, a polishing process, a combination thereof, or the like. After performing the planarization process, within the process variation range of the planarization process, the top surface of the conductive feature 122 and the top surface of the dielectric layer 102 are substantially flush or coplanar.

[0097] exist Fig.21A and Fig. 21B , dielectric layer 104 is formed over dielectric layer 102 and ILD 88. In some embodiments, dielectric layer 104 includes a material that does not include oxygen. For example, dielectric layer 104 can be formed using similar materials and methods as dielectric layer 102. In some embodiments, dielectric layer 102 and dielectric layer 104 include different materials. For example, dielectric layer 102 (e.g., the topmost layer of dielectric layer 102 if multi-layered) can be silicon nitride, and dielectric layer 104 can be silicon carbonitride (SiCN). In addition, in some embodiments, dielectric layer 104 can include oxygen. For example, dielectric layer 102 can be any of the materials described above, and dielectric layer 104 can be an oxide, carbonate, or carbide, such as silicon carbonate (SiCO) or silicon oxycarbide (SiOC). In various embodiments, dielectric layer 104 has a high etch selectivity to various adjacent features (such as dielectric layer 102, CESL 87, gate spacer 86, and gate seal spacer 80). For example, the etch selectivity to silicon nitride material may be greater than or equal to 10 (eg, 10 times).

[0098] exist Fig.22A and Fig. 22B In the embodiment, an ILD 106 is formed over the dielectric layer 104. In some embodiments, the ILD 106 may be formed using the same method as described above with reference to FIG. Fig.11A and Fig. 11B The ILD 88 is formed by similar materials and methods as described above, and will not be described again herein. In some embodiments, the ILD 88 and the ILD 106 include the same materials. In other embodiments, the ILD 88 and the ILD 106 include different materials.

[0099] exist Fig.23A and Fig. 23B In the process, an opening 128 is formed to expose the gate stack 96. In a subsequent step, the opening 128 will be filled with a conductive material to form a gate contact plug. In some embodiments, the patterning process includes a suitable photolithography and etching process, and extreme ultraviolet (EUV) lithography can be used.

[0100] As illustrated, the openings 128 extend through the ILD 106, the dielectric layer 104, and the dielectric layer 102. In addition, the final etching process is used to extend the openings 128 through the metal dielectric liner 100 to expose the corresponding gate stack 96 or the gate contact layer 99 (if present). Therefore, the metal dielectric liner 100 acts as an etch stop layer to prevent damage to the gate contact layer 99 during the patterning process. In some embodiments, the final etching process is not performed to extend some of the openings 128R. These particular openings 128R can be referred to as redundant openings 128R because these particular openings 128R can accommodate redundant conductive features of the gate stack 96 (e.g., redundant gate contact plugs, as discussed in more detail below).

[0101] As further illustrated, some of the openings 128 may be misaligned with corresponding portions of the gate stack 96. These particular openings 128M may be referred to as misaligned openings 128M because these particular openings 128M may accommodate misaligned conductive features (e.g., misaligned gate contact plugs, as discussed in more detail below) of the gate stack 96. When patterning the misaligned openings 128M, the metal dielectric liner 100 protects adjacent features (e.g., the gate sealing spacer 80) from being etched.

[0102] In some embodiments, the patterning process is performed by first forming a mask stack (not specifically illustrated) over the ILD 106. The mask may be a multi-layer mask, wherein the lower layer is a metal layer including a metal nitride (such as TiN, MoN, WN, or the like), a metal carbide (such as WC, WBC, or the like), a boron-containing material (such as BSi, BC, BN, BCN, or the like), a combination thereof, or the like, and may be formed using ALD, CVD, a combination thereof, or the like. The middle layer of the mask stack may be a dielectric layer, and may include SiO x , SiN, SiCN, SiOC, combinations thereof, or the like, and may be formed using ALD, CVD, combinations thereof, or the like. The upper layer of the mask stack may include amorphous silicon (a-Si), a boron-containing material (such as BSi, BC, BN, BCN, or the like), combinations thereof, or the like, and may be formed using ALD, CVD, combinations thereof, or the like. The mask stack is then used to pattern the ILD 106, the dielectric layer 104, and the dielectric layer 102 to form openings 128 for subsequently formed conductive features that provide electrical connections to the gate stack 96. Suitable etching processes (including the final etching process) may include one or more dry etching processes. The etching process may be anisotropic. In some embodiments, a CF 4 , CHF 3 , CH2 F 2 , C 4 F 6 , C 4 F 8 , Ar, O 2 、N 2 , H 2 , combinations thereof, or the like to perform a suitable etching process.

[0103] exist Fig.24A and Fig. 24B , a conductive feature 132 is formed in the opening 128. The conductive feature 132 provides an electrical connection to the corresponding gate stack 96. Therefore, the conductive feature 132 may also be referred to as a gate contact plug or a gate plug. In some embodiments, the conductive feature 132 may be formed using materials and methods similar to those of the conductive feature 122 described above, and the description is not repeated herein. In some embodiments, the conductive fill material of the conductive feature 132 is the same as the conductive fill material of the conductive feature 122. In other embodiments, the conductive fill material of the conductive feature 132 is different from the conductive fill material of the conductive feature 122, such as a conductive feature 132 comprising tungsten, which may or may not include first forming a barrier layer. For example, the conductive feature 132 may be formed of tungsten and deposited using CVD or any suitable method.

[0104] After forming the conductive fill material of the conductive feature 132, a planarization process is performed to remove the liner layer (e.g., barrier layer, adhesion layer, and seed layer, if present) and the portion of the conductive fill material that overfills the opening 128. The remaining portion of the liner layer and the conductive fill material forms the conductive feature 132 in the opening 128. The planarization process may include a CMP process, an etch-back process, a polishing process, a combination thereof, or the like. After performing the planarization process, within the process variation range of the planarization process, the top surface of the conductive feature 132 and the top surface of the ILD 106 are substantially flush or coplanar.

[0105] As described above, the conductive features 132 formed in the misaligned openings 128M may be referred to as misaligned conductive features 132M (e.g., misaligned contact gate plugs). In addition, the conductive features 132 formed in the redundant openings 128R may be referred to as redundant conductive features 132R. As illustrated, the redundant conductive features 132R are separated from the gate stack 96 (e.g., gate contact layer 99) by the metal dielectric liner 100. The redundant conductive features 132R may not be functional electrical elements of the integrated circuit unless later activated after the semiconductor element is manufactured. For example, it may be determined later (e.g., based on wafer testing of the semiconductor element) that some of the redundant conductive features 132R are needed as functional electrical elements. In this way, a high voltage stress (e.g., by a process called eFuse writing) is sent through those redundant conductive features 132R to cause dielectric breakdown of the metal dielectric liner 100 that separates the redundant conductive features 132R from the corresponding gate stack 96 (e.g., gate contact layer 99).

[0106] In some embodiments, the mask stack may be patterned using a suitable etchant for each layer. In addition, the pattern of the mask stack is then transferred to the ILD 106 and may be terminated at the dielectric layer 104, which may be used as an etch stop layer. The etching process may be isotropic, anisotropic, or a combination thereof. For example, the topmost layer of the mask stack (e.g., amorphous silicon) may be dry etched in an anisotropic etching process, and the underlying layers of the mask stack (e.g., dielectric layers and metal layers) may be etched in an isotropic etching process to transfer the pattern. The pattern may then be transferred through the ILD 106 using an isotropic etching process. As illustrated, the dielectric layer 104 may be partially etched before the pattern is fully transferred to the ILD 106.

[0107] exist FIG. 25A to FIG. 25G In the embodiment of the present invention, ILD 106 is patterned to form openings 126 in ILD 106. Openings 126 expose corresponding conductive features 122. In some embodiments, the patterning process includes suitable photolithography (e.g., using EUV lithography) and an etching process, and may include forming a mask stack (not specifically described) similar to that discussed above in conjunction with opening 128. Suitable etching processes may include one or more dry etching processes. The etching process may be anisotropic. In some embodiments, using a CF 4 , CHF 3 , CH 2 F 2 , C 4 F 6 , C 4 F 8 , Ar, O 2 、N 2 , H2 , combinations thereof, or the like to perform a suitable etching process. As described in more detail above, dielectric layers 102 and 104 are formed of different materials and have different etching selectivities. Thus, the material of dielectric layer 104 is selected so that dielectric layer 104 acts as an etch stop layer when forming opening 126. In addition, the high etching selectivity ensures that when the etching process is performed to extend opening 126 through dielectric layer 104, dielectric layer 102, CESL 87, and any other exposed silicon nitride layer remain substantially unetched. Thus, leakage between conductive features subsequently formed in opening 126 and adjacent gate stack 96 is reduced. In some embodiments, for the etching process used to form opening 126, the ratio of the etching rate of dielectric layer 104 (e.g., including SiN) to the etching rate of dielectric layer 102 (e.g., including SiCN or SiCO) is about or greater than 10.

[0108] FIG. 25A to FIG. 25F Description Figure 25G The various cross sections identified in the top-down schematic diagram (e.g., plan view) provided. It should be noted that Fig.25E and Fig.25F Continuation Fig.24A and Fig. 24B However, FIG. 25A to FIG. 25F Any structure is intended to represent Fig.24A and Fig. 24B 1 is a continuation of the exemplary cross-section of in order to illustrate various embodiment conductive features that will be subsequently formed in opening 126 .

[0109] Reference Fig.25A , Fig.25B and Figure 25G, openings 126A may have a rectangular shape and / or an oval shape (or a rounded rectangular shape), and may be formed directly over corresponding conductive features 122 (e.g., corresponding epitaxial source / drain regions 82). In some embodiments, openings 126A may be centered over conductive features 122, or in the illustrated embodiment, some of openings 126A may be directly over underlying conductive features 122 but laterally displaced (e.g., misaligned) relative to underlying conductive features 122, such that the central axis of opening 126A is laterally displaced relative to the central axis of underlying conductive features 122. In some embodiments, due to the displacement, openings 126A may extend below the top surface of underlying conductive features 122 and partially or completely extend through dielectric layer 104 (e.g., exposing dielectric layer 102). In some embodiments, due to dielectric layer 104 acting as an etch stop layer, openings 126A do not extend below the top surface of conductive features 122. In addition, when the opening 126A has a rectangular shape, the opening 126A may have the same or similar length and width (e.g., relative to the upper portion of the opening 126A), and thus have a square shape. When the opening 126A has an elliptical shape, the opening 126A may have the same or similar major and minor axes, and thus have a circular shape. For example, the length, width, and / or axis may range from 10 nm to 30 nm, including 15 nm to 25 nm, such as about 15 nm.

[0110] Reference Fig.25A , Fig.25B and Figure 25G , opening 126B may have a slot shape (e.g., an elongated rectangular shape) and may be formed above the corresponding conductive feature 122 and above the gate stack 96. As illustrated, opening 126B extends beyond the lateral edge of the underlying conductive feature 122. As such, opening 126B may extend below the top surface of the underlying conductive feature 122 and partially or completely extend through dielectric layer 104. In addition, because a portion of opening 126B may be directly above the adjacent gate stack 96, opening 126B may expose dielectric layer 102. In some embodiments, due to dielectric layer 104 acting as an etch stop layer, opening 126B does not extend below the top surface of conductive feature 122. In addition, the length of opening 126B may be greater than or equal to twice the width of opening 126B (e.g., relative to the upper portion of opening 126B). In some embodiments, the length of opening 126B may be up to three times the width of opening 126B. For example, the width of opening 126B may be the same as the width of opening 126A, such as ranging from 10 nm to 20 nm (eg, approximately 15 nm), and the length of opening 126B may range from 30 nm to 60 nm (eg, approximately 45 nm).

[0111] Reference Fig.25C , Fig.25D and Figure 25G , opening 126C may have a slot shape (e.g., an elongated rectangular shape) and may be formed over a plurality of conductive features 122, such as over two conductive features 122. In some embodiments (not specifically described), opening 126C may also be formed over gate stack 96, similar to that discussed with respect to opening 126B. As described, opening 126C extends beyond the lateral edge of the underlying conductive feature 122. As such, opening 126C may extend below the top surface of the underlying conductive feature 122 and partially or completely extend through dielectric layer 104. In addition, portions of opening 126C may expose dielectric layer 102. In some embodiments, due to dielectric layer 104 acting as an etch stop layer, opening 126C does not extend below the top surface of conductive feature 122. In addition, the length and width of opening 126C (e.g., relative to the upper portion of opening 126C) may have similar sizes and proportions as described above in conjunction with opening 126B.

[0112] Reference Fig.25E , Fig.25F and Figure 25G , opening 126D may have a slot shape (e.g., an elongated rectangular shape) and may be formed above the corresponding conductive feature 122 to subsequently form a docking contact, as discussed in more detail below. As illustrated, opening 126D extends beyond the lateral edge of the underlying conductive feature 122. As such, opening 126D may extend below the top surface of the underlying conductive feature 122 and partially or completely extend through dielectric layer 104. In addition, a portion of opening 126D may expose dielectric layer 102. In some embodiments, due to dielectric layer 104 acting as an etch stop layer, opening 126D does not extend below the top surface of conductive feature 122. In addition, the length and width of opening 126D (e.g., relative to the upper portion of opening 126D) may have similar dimensions and proportions as described above in conjunction with openings 126B, 126C. As further illustrated, because some of conductive features 132D are exposed during the process of forming opening 126D, the patterning process may etch a portion of conductive feature 132D. Thus, the conductive features 132D may be recessed from the top surface of the ILD 106 .

[0113] exist FIG. 26A to FIG. 26I, conductive feature 130 is formed in opening 126. Conductive feature 130 provides electrical connection to corresponding epitaxial source / drain regions 82 through conductive feature 122 (and in some cases, provides electrical connection to some of gate stack 96 through conductive feature 132). Therefore, the combination of conductive feature 130 and corresponding conductive feature 122 may also be referred to as source / drain contact plug or source / drain plug. In addition, conductive feature 122 may be referred to as a lower plug, and conductive feature 130 may be referred to as an upper plug. As illustrated, conductive feature 130A is formed in opening 126A, conductive feature 130B is formed in opening 126B, conductive feature 130C is formed in opening 126C, and conductive feature 130D is formed in opening 126D.

[0114] In some embodiments, opening 126 is formed after forming conductive feature 132. In such embodiments, conductive feature 132 may be protected by, for example, a mask (e.g., similar to the above description in conjunction with FIG. 1 ). Fig.23A and Fig. 23B 126B and 126C and corresponding conductive features 130A, 130B, 130C are formed before opening 126D and conductive feature 130D. In addition, any of conductive features 130A, 130B, 130C may also be formed separately and in any suitable order.

[0115] After forming the conductive fill material of the conductive feature 130, a planarization process is performed to remove the liner layer (e.g., barrier layer, adhesion layer, and seed layer, if present) and the portion of the conductive fill material that overfills the opening 126. The remaining portion of the liner layer and the conductive fill material forms the conductive feature 130 in the opening 126. The planarization process may include a CMP process, an etch-back process, a polishing process, a combination thereof, or the like. After performing the planarization process, within the process variation range of the planarization process, the top surfaces of the conductive feature 130 and the ILD 106 are substantially flush or coplanar.

[0116] In some embodiments, conductive features 130 and 132 may be formed using materials and methods similar to those of conductive feature 122 described above, and are not described again herein. In some embodiments, the conductive fill material of conductive feature 130 is the same as the conductive fill material of conductive feature 132. In other embodiments, the conductive fill material of conductive feature 130 is different from the conductive fill material of conductive feature 132. In some embodiments, the conductive fill material of conductive feature 130 and the conductive fill material of conductive feature 132 are the same as the conductive fill material of conductive feature 122. In other embodiments, the conductive fill material of conductive feature 130 and the conductive fill material of conductive feature 132 are different from the conductive fill material of conductive feature 122. In some embodiments, the top surfaces of conductive features 130 and 132 and the top surface of ILD 106 are substantially flush or coplanar.

[0117] Reference Fig.26A , Fig.26B and Figure 26G , conductive feature 130A may have the same rectangular or oval shape as described above in connection with opening 126A. In addition, conductive feature 130A may be centered or laterally displaced above conductive feature 122. In addition, conductive feature 130A may have the size and proportions as described above in connection with opening 126A. Fig.26H 1. The resistance between conductive feature 130 and conductive feature 122 may be affected by the interface area between their corresponding conductive fill materials. In addition, the liner layer of any one of conductive features 130, 122 may have a higher resistance than the counterpart. For example, the groove shape of conductive feature 130B reduces the resistance by preventing misalignment between conductive feature 130B and conductive feature 122. By increasing the interface area of ​​the corresponding conductive fill materials of conductive features 130B, 122, the resistance is further reduced. Therefore, the interface of conductive features 130A, 122 may have a resistance between 125 ohms and 150 ohms, such as 140 ohms, while the interface of conductive features 130B, 122 may have a resistance between 40 ohms and 50 ohms, such as 50 ohms. In some embodiments, the interface of conductive features 130B, 122 may have a resistance that is about three times or more smaller than the resistance between conductive features 130A, 122.

[0118] Reference FIG. 26A to FIG. 26D , Figure 26G and Fig.26I, the conductive features 130B, 130C can have the same slot shape as described above in conjunction with the corresponding openings 126B, 126C. In addition, the conductive features 130B, 130C can extend laterally beyond the corresponding conductive feature 122, as illustrated and discussed above. In addition, the conductive features 130B, 130C can have the size and proportions as described above in conjunction with the openings 126B, 126C. As discussed above, the slot shape allows for a larger interface area for low resistance electrical connection between the conductive features 130B, 130C and the corresponding conductive feature 122. In particular, the corresponding conductive fill material has a lower resistance than the corresponding liner layer. As Fig.26I As described in the foregoing, the groove shape increases the interface area between the conductive fill material of conductive features 130B, 130C and the conductive fill material of conductive feature 122. Therefore, the interface of conductive features 130C, 122 can have a resistance that is about three times or more less than the resistance between conductive features 130A, 122. For example, the resistance between conductive features 130C, 122 can be between 40 ohms and 50 ohms, such as 46 ohms. An additional advantage of these embodiments (e.g., the groove shape of conductive features 130B, 130C) is that a ring oscillator boost of up to about 1% is obtained.

[0119] Reference Fig.26E , Fig.26F and Figure 26G , conductive feature 130D can have the same slot shape and docking contact configuration as described above in conjunction with opening 126D. Conductive feature 130D can therefore be referred to as a docking contact because conductive feature 130D can contact both corresponding conductive feature 132D and corresponding conductive feature 122. In addition, conductive feature 130D can extend laterally beyond corresponding conductive feature 122, which achieves the benefits discussed above in conjunction with the contact configuration that allows docking with conductive feature 132. In addition, conductive feature 130D can have the size and proportions as described above in conjunction with opening 126D. It should be further understood that the slot shape and docking contact configuration of conductive feature 130D provide a similar resistance reduction as described above in conjunction with conductive features 130B, 130C. It should be understood that conductive feature 130D can be utilized with transistors formed in a static RAM (e.g., SRAM) layout.

[0120] In some embodiments (not specifically described), after forming conductive feature 130, additional conductive features may be formed through ILD 106, dielectric layer 104, dielectric layer 102, and metal dielectric liner 100 to form electrical connections to one of gate stacks 96 and one of conductive features 122 (e.g., to underlying epitaxial source / drain regions 82). Processing may be performed similarly to that described above in connection with conductive features 122, 130, 132, including similar photolithography steps (e.g., using EUV lithography). However, conductive feature 130D (e.g., butt contact) has the added advantage that it can be used as a substitute for these additional conductive features. Thus, the formation of conductive feature 130D eliminates photolithography steps, thereby reducing costs and improving the efficiency and yield of semiconductor devices.

[0121] exist FIG. 27A to FIG. 27F In some embodiments, interconnect structure 134 is formed over conductive features 130 and 132 and ILD 106. In some embodiments, interconnect structure 134 includes multiple dielectric layers, such as inter-metal dielectrics (IMDs) (not separately illustrated) and conductive features within the IMDs (not separately illustrated). The IMDs may be used as described above with reference to Fig.11A and Fig. 11B The conductive features include conductive lines and conductive vias, and can be formed using a single damascene method, a dual damascene method, a combination thereof, or the like. The conductive features of the interconnect structure 134 are in electrical contact with the conductive features 130 and 132.

[0122] As further illustrated, the interconnect structure 134 may include a metallization layer 136, which is the lowest metallization layer that physically contacts some of the conductive features 130, 132. In some embodiments, the metallization layer 136 may include one or more power rails 136P that provide power to various underlying components. For example, some of the power rails of the metallization layer 136 may extend longer than the underlying conductive features 130. In addition, as shown in FIG. Fig.27D , some of the underlying conductive features 130 may extend the same length as the power rail 136P. In addition, the respective widths of the conductive features 130 and the metallization layer 136 may be substantially the same. As such, certain conductive features (e.g., conductive feature 130D) may be considered to be part of the overlying power rail 136P. However, in some embodiments, the conductive features 130 may include tungsten while the power rail 136P includes copper, or the conductive features 130 and the power rail 136P may include substantially the same material.

[0123] Embodiments can achieve advantages. In some embodiments, source / drain contact plugs can be formed in various configurations to reduce resistance between elements, such as a lower plug (e.g., conductive feature 122) and an upper plug (e.g., conductive feature 130). In particular, conductive feature 130 can have a groove shape to prevent misalignment and increase the surface area of ​​the interface between conductive feature 130 and the corresponding conductive fill material of conductive feature 122, thereby reducing resistance therebetween. In addition, conductive feature 130 can extend over other integrated circuit elements such as gate stack 96. Thus, in order to prevent leakage between conductive feature 130 and gate stack 96, the material of dielectric layer 104 is selected to have a high etch selectivity to the gate mask (e.g., dielectric layer 102). In addition, metal dielectric liner 100 reduces the risk of misalignment of gate stack 96 by the formation of conductive feature 132M, while or alternatively providing the versatility of redundant conductive feature 132R.

[0124] In one embodiment, a method for forming a semiconductor device includes: forming an epitaxial source / drain region in a substrate; forming a first interlayer dielectric above the epitaxial source / drain region; forming a gate stack above the substrate and adjacent to the first interlayer dielectric; forming a gate mask above the gate stack; forming a source / drain plug through the first interlayer dielectric and electrically connected to the epitaxial source / drain region; depositing a dielectric layer over the gate mask and the first interlayer dielectric, the dielectric layer having a different etch selectivity than the gate mask; forming a second interlayer dielectric over the dielectric layer; etching an opening through the second interlayer dielectric and the dielectric layer, the opening exposing the source / drain plug and the gate mask; and forming a conductive feature in the opening, the conductive feature electrically connected to the source / drain plug. In another embodiment, forming the gate mask includes: recessing the gate stack; depositing a metal dielectric liner over the gate stack; and depositing a nitride layer over the metal dielectric liner. In another embodiment, the method further includes: forming additional epitaxial source / drain regions in the substrate; and forming additional source / drain plugs through the first interlayer dielectric and electrically connected to the additional epitaxial source / drain regions, wherein the conductive features are in physical contact with the source / drain plugs and the additional source / drain plugs. In another embodiment, the method further includes: forming a gate plug through the second interlayer dielectric and electrically connected to the gate stack, wherein forming the conductive features includes forming the conductive features as contacts that interface with the gate plug and the source / drain plugs. In another embodiment, the method further includes: before forming the conductive features, performing an etching process to etch through the second interlayer dielectric and the dielectric layer, wherein the dielectric layer acts as an etching stop layer during the etching process. In another embodiment, after performing the etching process, the gate mask remains substantially unetched. In another embodiment, the dielectric layer and the gate mask may have an etching selectivity greater than or equal to 10. In another embodiment, the gate mask includes silicon nitride, and wherein the dielectric layer includes silicon carbonate or silicon carbonitride.

[0125] In an embodiment, a method for forming a semiconductor device includes: forming a first epitaxial region and a second epitaxial region in a substrate; forming a first oxide layer above the first epitaxial region and the second epitaxial region; forming a first gate stack and a second gate stack above the substrate, the first gate stack being interposed between the first epitaxial region and the second epitaxial region; forming a nitride mask above the first gate stack; etching the first oxide layer to expose the first epitaxial region and the second epitaxial region; forming a first conductive feature above the first epitaxial region and a second conductive feature above the second epitaxial region; forming an etch stop layer above the nitride mask and the first oxide layer; forming a second oxide layer above the etch stop layer; forming a gate plug above the first gate stack and physically contacting the first gate stack; and forming a third conductive feature through the second oxide layer and the etch stop layer, the third conductive feature physically contacting the first conductive feature. In another embodiment, the etch stop layer has an etch selectivity of 10 or greater compared to the nitride mask. In another embodiment, in a plan view, the third conductive feature has a rectangular shape, and wherein the length of the rectangular shape is two to three times greater than the width of the rectangular shape. In another embodiment, the third conductive feature is directly above the first epitaxial region, the first gate stack and the second gate stack. In another embodiment, the third conductive feature is directly above the first epitaxial region and the second epitaxial region. In another embodiment, the third conductive feature is in physical contact with the gate plug.

[0126] In an embodiment, a semiconductor device includes: a gate stack over a substrate; a metal dielectric liner over the gate stack; a gate mask over the metal dielectric liner; a first oxide layer over the substrate, the top surface of the first oxide layer being flush with the top surface of the gate mask; a dielectric layer over the gate mask and the first oxide layer, the dielectric layer being a different material than the gate mask; a second oxide layer over the dielectric layer; a first conductive feature extending through the first oxide layer, the top surface of the first conductive feature being flush with the top surface of the gate mask; and a second conductive feature extending through the second oxide layer and the dielectric layer, the second conductive feature being in physical contact with the first conductive feature. In another embodiment, the gate mask comprises silicon nitride, and wherein the dielectric layer comprises silicon carbonitride. In another embodiment, the gate mask comprises silicon nitride, and wherein the dielectric layer comprises silicon carbonate. In another embodiment, in a plan view, the second conductive feature has a length that is two to three times greater than its width. In another embodiment, the semiconductor device further includes a third conductive feature extending through the gate mask and physically contacting the gate stack, wherein the second conductive feature and the third conductive feature form a butting contact. In another embodiment, the second conductive feature is directly above the first conductive feature and directly above the gate stack, and wherein the gate mask is electrically interposed between the second conductive feature and the gate stack.

[0127] In some embodiments, a semiconductor device includes: a substrate; a first epitaxial source / drain region located in the substrate; a first interlayer dielectric located above the first epitaxial source / drain region; a gate stack located above the substrate and adjacent to the first interlayer dielectric; a gate mask located above the gate stack; a first source / drain plug passing through the first interlayer dielectric and electrically connected to the first epitaxial source / drain region; a dielectric layer located above the gate mask and the first interlayer dielectric; a second interlayer dielectric located above the dielectric layer; and a conductive feature passing through the second interlayer dielectric and the dielectric layer and contacting the first source / drain plug and the gate mask. In some embodiments, the gate mask includes: a metal dielectric liner located above the gate stack; and a nitride layer located above the metal dielectric liner. In some embodiments, the semiconductor device further includes: a second epitaxial source / drain region located in the substrate; and a second source / drain plug passing through the first interlayer dielectric and electrically connected to the second epitaxial source / drain region, wherein the conductive feature contacts the first source / drain plug and the second source / drain plug.

[0128] In some embodiments, a semiconductor device includes: a substrate; a first epitaxial region located in the substrate; a second epitaxial region located in the substrate; a first oxide layer located above the first epitaxial region and the second epitaxial region; a first gate stack located above the substrate; a second gate stack located above the substrate, wherein the first gate stack is inserted between the first epitaxial region and the second epitaxial region; a nitride mask located above the first gate stack; a first conductive feature located above the first epitaxial region; a second conductive feature located above the second epitaxial region; an etch stop layer located above the nitride mask and the first oxide layer; a second oxide layer located above the etch stop layer; a gate plug located above the first gate stack and in contact with the first gate stack; and a third conductive feature passing through the second oxide layer and the etch stop layer and in contact with the first conductive feature. In some embodiments, in a plan view, the third conductive feature has a rectangular shape, and wherein the length of the rectangular shape is two to three times greater than the width of the rectangular shape. In some embodiments, the third conductive feature is directly above the first epitaxial region, the first gate stack, and the second gate stack.

[0129] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that those skilled in the art can make various changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor element, characterized in that: include: A gate stack is disposed above a substrate; a metal dielectric liner over the gate stack; a gate mask disposed above the metal dielectric liner; A first oxide layer is disposed above the substrate, wherein a top surface of the first oxide layer is flush with a top surface of the gate mask; A dielectric layer is located above the gate mask and the first oxide layer, and the dielectric layer is a material different from that of the gate mask; a second oxide layer located above the dielectric layer; a first conductive feature extending through the first oxide layer, a top surface of the first conductive feature being flush with the top surface of the gate mask; and A second conductive feature extends through the second oxide layer and the dielectric layer, and the second conductive feature contacts the first conductive feature.

2. The semiconductor device according to claim 1, wherein: In a plan view, the second conductive feature has a length that is two to three times greater than a width.

3. The semiconductor device according to claim 1, wherein: The method further includes a third conductive feature extending through the gate mask and contacting the gate stack, wherein the second conductive feature and the third conductive feature form a pair of contact points.

4. The semiconductor device according to claim 1, wherein: The second conductive feature is directly above the first conductive feature and directly above the gate stack, and the gate mask is electrically inserted between the second conductive feature and the gate stack.

5. A semiconductor element, characterized in that: include: a substrate; a first epitaxial source / drain region located in the substrate; a first interlayer dielectric disposed above the first epitaxial source / drain region; a gate stack disposed above the substrate and adjacent to the first interlayer dielectric; a gate mask located above the gate stack; a first source / drain plug passing through the first interlayer dielectric and electrically connected to the first epitaxial source / drain region; a dielectric layer located above the gate mask and the first interlayer dielectric; a second interlayer dielectric disposed above the dielectric layer; and A conductive feature passes through the second interlayer dielectric and the dielectric layer and contacts the first source / drain plug and the gate shield.

6. The semiconductor device according to claim 5, wherein: The gate mask includes: a metal dielectric liner located above the gate stack; and A nitride layer is located above the metal dielectric liner.

7. The semiconductor device according to claim 5, wherein: Further including: a second epitaxial source / drain region located in the substrate; and A second source / drain plug passes through the first interlayer dielectric and is electrically connected to the second epitaxial source / drain region, wherein the conductive feature contacts the first source / drain plug and the second source / drain plug.

8. A semiconductor element, characterized in that: include: a substrate; a first epitaxial region located in the substrate; a second epitaxial region located in the substrate; a first oxide layer located above the first epitaxial region and the second epitaxial region; a first gate stack located above the substrate; a second gate stack located above the substrate, wherein the first gate stack is interposed between the first epitaxial region and the second epitaxial region; a nitride mask located above the first gate stack; a first conductive feature located above the first epitaxial region; a second conductive feature located above the second epitaxial region; an etch stop layer located above the nitride mask and the first oxide layer; a second oxide layer located above the etch stop layer; a gate plug located above the first gate stack and in contact with the first gate stack; and A third conductive feature passes through the second oxide layer and the etch stop layer and contacts the first conductive feature.

9. The semiconductor device according to claim 8, wherein: In a plan view, the third conductive feature has a rectangular shape, and a length of the rectangular shape is two to three times greater than a width of the rectangular shape.

10. The semiconductor device according to claim 9, wherein The third conductive feature is located directly above the first epitaxial region, the first gate stack and the second gate stack.

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