Semiconductor device

Abstract

A semiconductor device includes an n-type buried layer, a p-type well region over the n-type buried layer, an n-type channel MOSFET including an n-type drain region, and a vertical NPN BJT. The vertical NPN BJT has a collector that is an n-type drain region and a base that is a p-type well region. The p-type well region is floating.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to an electrostatic discharge protection device with a bipolar junction transistor. Background Art

[0002] Semiconductor devices are becoming faster and smaller. In one aspect, semiconductor manufacturers improve the performance of semiconductor devices and reduce the size of semiconductor devices by shrinking process geometries. Generally speaking, semiconductor devices with smaller process geometries are more susceptible to degradation and damage due to electrostatic discharge (ESD). In order to protect the device from ESD degradation and damage, ESD protection devices are added to semiconductor devices. Generally, ESD implants are included in metal-oxide semiconductor field-effect transistor (MOSFET) semiconductor devices (e.g., resistive protective oxide (RPO) MOSFET devices) for ESD protection. However, one or more additional masks used to manufacture the ESD implants increase the cost of the semiconductor device. Utility Model Content

[0003] The present disclosure provides a semiconductor device. The semiconductor device includes an n-type buried layer, a p-type well region located above the n-type buried layer, an n-type channel metal oxide semiconductor field effect transistor including an n-type drain region, and a vertical NPN bipolar junction transistor. The collector of the vertical NPN bipolar junction transistor is an n-type drain region, and the base is a p-type well region. The p-type well region is floating.

[0004] In some embodiments, an emitter of the vertical NPN bipolar junction transistor is electrically connected to the n-type buried layer of a reference voltage, and a source region included in the n-type channel metal oxide semiconductor field effect transistor is electrically connected to the reference voltage, and the semiconductor device further includes a lateral NPN bipolar junction transistor, a collector of the lateral NPN bipolar junction transistor is the n-type drain region, an emitter is the source region, and a base is the floating p-type well region.

[0005] In some embodiments, the vertical NPN bipolar junction transistor has an emitter that is electrically connected to the n-type buried layer of a power voltage.

[0006] In some embodiments, the n-channel metal oxide semiconductor field effect transistor includes a source region electrically connected to a reference voltage, and the semiconductor device further includes a lateral NPN bipolar junction transistor, the lateral NPN bipolar junction transistor having a collector as the n-type drain region, an emitter as the source region, and a base as the floating p-type well region.

[0007] The present disclosure provides a semiconductor device. The semiconductor device includes an n-type buried layer electrically connected to a reference voltage Vss or a power supply voltage Vdd; a p-type well region located above the n-type buried layer; an n-type channel metal oxide semiconductor field effect transistor including an n-type drain region electrically connected to an input / output pad; and a vertical NPN bipolar junction transistor. The vertical NPN bipolar junction transistor has a collector that is an n-type drain region, an emitter that is an n-type buried layer, and a base that is a p-type well region. The p-type well region is floating.

[0008] In some embodiments, the n-channel MOSFET includes a floating source.

[0009] In some embodiments, the n-type buried layer is electrically connected to the reference voltage.

[0010] In some embodiments, the n-channel metal oxide semiconductor field effect transistor includes a source region electrically connected to the reference voltage, and the semiconductor device further includes a lateral NPN bipolar junction transistor, the lateral NPN bipolar junction transistor having a collector as the n-type drain region, an emitter as the source region, and a base as the floating p-type well region.

[0011] In some embodiments, the n-type buried layer is electrically connected to the power voltage.

[0012] In some embodiments, the n-channel metal oxide semiconductor field effect transistor includes a source region electrically connected to the reference voltage Vss, and the semiconductor device further includes a lateral NPN bipolar junction transistor, the lateral NPN bipolar junction transistor having a collector as the n-type drain region, an emitter as the source region, and a base as the floating p-type well region. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The aspects of the present disclosure can be better understood from the subsequent embodiments and drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the sizes of various features may be arbitrarily increased or decreased to make the discussion clear and understandable. In addition, the drawings are intended as illustrative examples of embodiments of the present disclosure and are not intended to be limiting.

[0014] Figure 1 is a diagram according to some embodiments of the present disclosure, schematically showing a cross section of a semiconductor device including a parasitic vertical NPN BJT for releasing ESD current.

[0015] Figure 2 is a diagram according to some embodiments of the present disclosure, schematically showing a snapback device Figure 1 semiconductor device.

[0016] Figure 3 is a diagram according to some embodiments of the present disclosure, schematically showing an IV curve of a parasitic vertical NPN BJT.

[0017] Figure 4 is a diagram according to some embodiments of the present disclosure, schematically showing a Figure 1 A semiconductor device of a semiconductor device.

[0018] Figure 5 is a diagram according to some embodiments of the present disclosure, schematically showing a MOSFET and a parasitic vertical NPN BJT Figure 1 semiconductor device.

[0019] Figure 6 is a diagram according to some embodiments of the present disclosure, schematically showing a MOSFET, a parasitic vertical NPN BJT and a parasitic lateral NPN BJT Figure 1 semiconductor device.

[0020] Figure 7 is a diagram according to some embodiments of the present disclosure, schematically showing another ESD scheme Figure 4 semiconductor device.

[0021] Figure 8 is a diagram according to some embodiments of the present disclosure, schematically showing a circuit configured to release the ESD current to a reference voltage Vss and to a power supply voltage Vdd Figure 1 semiconductor device.

[0022] Fig. 9 is a diagram showing a method of operating an ESD protection device according to some embodiments of the present disclosure.

[0023] Fig.10 is a block diagram according to some embodiments of the present disclosure, schematically showing an example of a computer system configured to provide the semiconductor device and method of the present disclosure.

[0024] Fig.11 It is a block diagram according to some embodiments of the present disclosure, schematically showing a semiconductor device manufacturing system and a semiconductor device manufacturing process related thereto.

[0025] The reference numerals are described as follows:

[0026] 20: Semiconductor devices

[0027] 22: Parasitic Vertical NPN BJT

[0028] 24: MOSFET

[0029] 26: p-type well region

[0030] 28: n-type buried layer

[0031] 30: n-type drain region

[0032] 32: n-type source region

[0033] 34: Gate

[0034] 36: p+ contact

[0035] 38: Isolation Area

[0036] 40: Parasitic Lateral NPN BJT

[0037] 42: Base resistance

[0038] 50: I / O pad

[0039] 54: IV Curve

[0040] 56: x-axis

[0041] 58: y-axis

[0042] 60: Semiconductor devices

[0043] 62: Internal Circuit

[0044] 64: ESD clamp

[0045] 80: Operation

[0046] 82: Operation

[0047] 84: Operation

[0048] 100: Computer Systems

[0049] 102: Processor

[0050] 104: Computer readable storage media

[0051] 106: Instructions

[0052] 108: Manufacturing Machine

[0053] 110: Bus

[0054] 112: I / O interface

[0055] 114: Network interface

[0056] 116: Network

[0057] 118: Database

[0058] 120: UI

[0059] 122: Manufacturing System

[0060] 124: Design Studio

[0061] 126: Mask Studio

[0062] 128: Semiconductor device manufacturing plant

[0063] 130: Semiconductor device design layout pattern

[0064] 132: Data Preparation

[0065] 134: Mask manufacturing

[0066] 136: Photomask

[0067] 138: Semiconductor wafer

[0068] 140: Wafer Manufacturing

[0069] 142: Semiconductor devices

[0070] Vdd: power supply voltage

[0071] Vss: reference voltage

[0072] Vh: Holding voltage

[0073] Vt1: ESD trigger voltage

[0074] Vt2: Destructive voltage of the victim DETAILED DESCRIPTION

[0075] The following disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific examples of the various components and arrangements of the present disclosure are described below to simplify the description. Of course, these are merely examples and are not intended to limit the present disclosure. For example, if the description has a first feature formed on or above a second feature, it may include an embodiment in which the first feature and the second feature are formed in direct contact, and it may also include an embodiment in which an additional feature is formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in multiple examples. The purpose of this repetition is to simplify and clarify, and does not itself specify the relationship between the various embodiments and / or configurations discussed.

[0076] Further, the present disclosure may use spatially relative terms, such as "below," "below," "below," "above," "above," and the like, to describe the relationship of one element or feature to other elements or features in the drawings. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be oriented in different orientations (rotated 90 degrees or at other orientations), and the spatially relative terms used herein interpreted accordingly.

[0077] Embodiments disclosed herein provide a semiconductor device including a parasitic vertical NPN bipolar junction transistor (BJT) for discharging ESD current. Advantages of the parasitic vertical NPN BJT for ESD protection include a lower ESD triggering voltage Vt1. In some embodiments, the semiconductor device is an RPO MOS device.

[0078] The semiconductor device includes an n-type buried layer, a p-type well region above the n-type buried layer, and a snapback device for ESD protection. The snapback device includes an n-type channel MOSFET, which includes an n-type drain region and an n-type source region. The parasitic vertical NPN BJT includes a collector located at the n-type drain region, an emitter located at the n-type buried layer, and a base located at the p-type well region, wherein the p-type well region is floating and is not connected to a reference voltage or a power voltage. Through the floating p-type well region, the parasitic vertical NPN BJT has a lower ESD trigger voltage Vt1. In some embodiments, the n-type drain region is a heavily doped n-type (n+) drain region, and in some embodiments, the n-type source region is an n+ source region.

[0079] Figure 1 2 is a diagram showing a cross section of a semiconductor device 20 including a parasitic vertical NPN BJT 22 for releasing ESD current according to some embodiments of the present disclosure. The semiconductor device 20 is a snapback device for releasing ESD current. The semiconductor device 20 includes a MOSFET 24 located above a p-type well region 26, wherein the p-type well region 26 is located above an n-type buried layer 28. In some embodiments, the MOSFET 24 is an RPO MOSFET.

[0080] MOSFET 24 includes an n-type drain region 30, an n-type source region 32, and a gate 34. P-type well region 26 includes a p+ contact 36, and MOSFET 24 further includes an isolation region 38 located on each side of MOSFET 24 and adjacent to p+ contact 36. In some embodiments, n-type drain region 30 is an n+ drain region, and in some embodiments, n-type source region 32 is an n+ source region.

[0081] The n-type drain region 30 is the collector of the parasitic vertical NPN BJT 22, and the n-type buried layer 28 is the emitter of the parasitic vertical NPN BJT 22. The p-type well region 26 is the base of the parasitic vertical NPN BJT 22. In some embodiments, the n-type drain region 30 is electrically connected to an input / output (I / O) pad. In addition, the n-type source region 32 is electrically connected to the gate 34.

[0082] In operation, the n-type buried layer 28 is electrically connected to a reference voltage (e.g., ground), while the p-type well region 26 and the p+ contact 36 are floating and not connected to a reference voltage or a power supply voltage. When an ESD event strikes the n-type drain region 30 that can be electrically connected to the I / O pad, the parasitic vertical NPN BJT 22 is biased on, for example, due to an avalanche breakdown through the collector to the base and emitter. With the base floating, the ESD trigger voltage Vt1 used to bias the parasitic vertical NPN BJT 22 is lower, causing the parasitic vertical NPN BJT 22 to be biased on more quickly. The lower ESD trigger voltage Vt1 biases the parasitic vertical NPN BJT 22, which provides an early ESD discharge path through the parasitic vertical NPN BJT 22 to the n-type buried layer 28.

[0083] The parasitic vertical NPN BJT 22 is biased on at a lower ESD trigger voltage Vt1 than the ESD trigger voltage Vt1 used to bias on the parasitic lateral NPN BJT 40 in a different configuration of the semiconductor device 20. In this different configuration, the parasitic lateral NPN BJT 40 includes an n-type drain region 30 as a collector, an n-type source region 32 as an emitter, and a p-type well region 26 as a base. However, in order to discharge the ESD current using the parasitic lateral NPN BJT 40, each of the p+ contact 36 and the n-type source region 32 is electrically connected to a reference voltage (e.g., ground). This provides a base resistance 42 between the base of the parasitic lateral NPN BJT 40 and the p+ contact 36. When an ESD event strikes the n-type drain region 30, the parasitic lateral NPN BJT 40 is biased on, for example due to a sudden collapse through the collector and base to the p+ contact 36. The base current through the base resistor 42 establishes a base voltage at the base, which biases the parasitic lateral NPN BJT 40 to discharge the ESD current to the n-type source region 32 via the parasitic lateral NPN BJT 40. The ESD trigger voltage Vt1 for biasing the parasitic lateral NPN BJT 40 is higher than the ESD trigger voltage Vt1 for biasing the parasitic vertical NPN BJT 22.

[0084] Figure 2 is a diagram according to some embodiments of the present disclosure, schematically showing a snapback device Figure 1 The semiconductor device 20 is electrically connected to the I / O pad 50 and the reference voltage Vss. In some embodiments, the reference voltage Vss is grounded.

[0085] The n-type drain region 30 is electrically connected to the I / O pad 50 and serves as the collector of the parasitic vertical NPN BJT 22. The n-type buried layer (NBL) 28 serves as the emitter of the parasitic vertical NPN BJT 22, and the p-type well region 26 serves as the base of the parasitic vertical NPN BJT 22.

[0086] In operation, the n-type buried layer 28 is electrically connected to a reference voltage Vss (e.g., ground), and the p-type well region 26 is floating. When an ESD event strikes the I / O pad 50, the parasitic vertical NPN BJT 22 is biased on, for example, due to a sudden breakdown through the collector to the base and emitter. With the base floating, the ESD trigger voltage Vt1 used to bias on the parasitic vertical NPN BJT 22 is lower, causing the parasitic vertical NPN BJT 22 to be biased faster. This provides an early ESD discharge path through the parasitic vertical NPN BJT 22 to the n-type buried layer 28 and the reference voltage Vss.

[0087] Figure 3 is a diagram schematically showing an IV curve 54 of a parasitic vertical NPN BJT 22 according to some embodiments of the present disclosure. The IV curve includes a voltage along an x-axis 56 and a current along a y-axis 58 .

[0088] When the voltage across the parasitic vertical NPN BJT 22 reaches the ESD trigger voltage Vt1, the parasitic vertical NPN BJT 22 is biased on. The biased-on parasitic vertical NPN BJT 22 provides an ESD current path through the parasitic vertical NPN BJT 22 to the reference voltage Vss, and the voltage across the parasitic vertical NPN BJT 22 decreases to a holding voltage Vh from the n-type drain region 30 to the n-type source region 32. As the ESD trigger voltage Vt1 is less than the destructive voltage (e.g., the victim's destructive voltage Vt2), the parasitic vertical NPN BJT 22 prevents the ESD event from damaging the semiconductor device 20.

[0089] Figure 4 is a diagram according to some embodiments of the present disclosure, schematically showing a Figure 1 The semiconductor device 60 includes the semiconductor device 20, an internal circuit 62, and an ESD clamp 64. The semiconductor device 20 is Figure 1 and Figure 2 In some embodiments, the ESD clamp 64 is an ESD power supply clamp. In other embodiments, the snapback device may be a different semiconductor device.

[0090] Each of the internal circuit 62 and the ESD clamp 64 is electrically connected to the power supply voltage Vdd and the reference voltage Vss. Each of the internal circuit 62 and the semiconductor device 20 is electrically connected to the I / O pad 50, and the semiconductor device 20 is electrically connected to the reference voltage Vss.

[0091] In operation, an ESD event strikes I / O pad 50 and semiconductor device 20 discharges the ESD current through semiconductor device 20 to reference voltage Vss before the ESD event has a chance to degrade or damage internal circuit 62. In some embodiments, this is referred to as PS mode.

[0092] Figure 5 2 is a diagram according to some embodiments of the present disclosure, schematically showing a semiconductor device 20 having a MOSFET 24 and a parasitic vertical NPN BJT 22. The MOSFET 24 includes an n-type drain region 30 electrically connected to an I / O pad 50, wherein the n-type drain region 30 is a collector of the parasitic vertical NPN BJT 22. The MOSFET 24 further includes a gate 34 electrically connected to an n-source region 32, wherein the n-source region 32 is electrically connected to a p-type well region 26, all of which are floating. The n-type buried layer 28 is an emitter of the parasitic vertical NPN BJT 22, wherein the n-type buried layer 28 is electrically connected to a reference voltage Vss, and the p-type well region 26 is a base of the parasitic vertical NPN BJT 22, wherein the p-type well region 26 is floating.

[0093] In operation, when an ESD event strikes the I / O pad 50, the parasitic vertical NPN BJT 22 is biased on, for example, due to a sudden breakdown through the collector to the base and emitter. With the base floating, the ESD trigger voltage Vt1 used to bias on the parasitic vertical NPN BJT 22 is lower, causing the parasitic vertical NPN BJT 22 to be biased faster. This provides an early ESD discharge path through the parasitic vertical NPN BJT 22 to the n-type buried layer 28 and the reference voltage Vss.

[0094] Figure 6 FIG. 2 is a diagram showing a semiconductor device 20 having a MOSFET 24 , a parasitic vertical NPN BJT 22 , and a parasitic lateral NPN BJT 40 according to some embodiments of the present disclosure.

[0095] MOSFET 24 includes an n-type drain region 30 electrically connected to I / O pad 50, wherein n-type drain region 30 is a collector of parasitic vertical NPN BJT 22 and a collector of parasitic lateral NPN BJT 40. MOSFET 24 further includes a gate 34 electrically connected to n-type source region 32, wherein n-source region 32 is electrically connected to reference voltage Vss. n-type source region 32 is an emitter of parasitic lateral NPN BJT 40. n-type buried layer 28 is an emitter of parasitic vertical NPN BJT 22, wherein n-type buried layer 28 is electrically connected to reference voltage Vss. p-type well region 26 is a base of parasitic vertical NPN BJT 22 and a base of parasitic lateral NPN BJT 40. p-type well region 26 is floating.

[0096] In operation, when an ESD event strikes the I / O pad 50, the parasitic vertical NPN BJT 22 is biased on, for example, due to a sudden collapse through the collector to the base and emitter, and the parasitic lateral NPN BJT 40 is biased on, for example, due to a sudden collapse through the collector to the base and emitter. When the parasitic vertical NPN BJT 22 and the parasitic lateral NPN BJT 40 are biased on, the ESD trigger voltage Vt1 is further reduced, so that the ESD current is released faster. This provides an earlier ESD discharge path through the parasitic vertical NPN BJT 22 and the parasitic lateral NPN BJT 40 to the reference voltage Vss.

[0097] Figure 7 is a diagram according to some embodiments of the present disclosure, schematically showing a semiconductor device 60 in another ESD scheme. In this scheme, an ESD event impacts an I / O pad 50 and flows through a snapback device to a reference voltage Vss. Then, the ESD current flows through an ESD clamp 64 to a power supply voltage Vdd. The ESD current has a path to the power supply voltage Vdd via a metal bus of a reference voltage Vss and a body diode of the ESD clamp 64. Therefore, the ESD current flows from the I / O pad 50 to the power supply voltage Vdd. In some embodiments, this is referred to as a PD mode.

[0098] To accommodate this solution, the semiconductor device 20 is configured to release the ESD current to the reference voltage Vss and the power supply voltage Vdd. The semiconductor device 60 includes the semiconductor device 20, an internal circuit 62, and an ESD clamp 64. Each of the semiconductor device 20, the internal circuit 62, and the ESD clamp 64 is electrically connected to the power supply voltage Vdd and the reference voltage Vss. Each of the internal circuit 62 and the semiconductor device 20 is electrically connected to the I / O pad 50.

[0099] In operation, before the ESD event has a chance to degrade or damage the internal circuit 62, the ESD event strikes the I / O pad 50, and the semiconductor device 20 discharges the ESD current to the reference voltage Vss and the power supply voltage Vdd through the semiconductor device 20.

[0100] Figure 8 is a diagram according to some embodiments of the present disclosure, schematically showing a semiconductor device 20 (shown in FIG. 1 ) configured to release ESD current to a reference voltage Vss and to a power supply voltage Vdd. Figure 7 ). The semiconductor device 20 includes a MOSFET 24, a parasitic vertical NPN BJT 22, and a parasitic lateral NPN BJT 40.

[0101] MOSFET 24 includes an n-type drain region 30 electrically connected to an I / O pad 50, wherein the n-type drain region 30 is a collector of the parasitic vertical NPN BJT 22 and a collector of the parasitic lateral NPN BJT 40. MOSFET 24 further includes a gate 34 electrically connected to an n-type source region 32, wherein the n-type source region 32 is electrically connected to a reference voltage Vss. The n-type source region 32 is an emitter of the parasitic lateral NPN BJT 40. The n-type buried layer 28 is an emitter of the parasitic vertical NPN BJT 22, wherein the n-type buried layer 28 is electrically connected to a power supply voltage Vdd. The p-type well region 26 is a base of the parasitic vertical NPN BJT 22 and a base of the parasitic lateral NPN BJT 40. The p-type well region 26 is floating.

[0102] In operation, when an ESD event strikes the I / O pad 50, the parasitic vertical NPN BJT 22 is biased on, for example, due to a sudden collapse through the collector to the base and emitter, and the parasitic lateral NPN BJT 40 is biased on, for example, due to a sudden collapse through the collector to the base and emitter. The parasitic vertical NPNBJT 22 is biased on to discharge the ESD current to the power supply voltage Vdd, and the parasitic lateral NPNBJT 40 is biased on to discharge the ESD current to the reference voltage Vss. When the parasitic vertical NPNBJT 22 and the parasitic lateral NPN BJT 40 are biased on, the ESD trigger voltage Vt1 is reduced, so that the ESD current is discharged faster. This provides an earlier ESD discharge path through the parasitic vertical NPN BJT 22 to the power supply voltage Vdd and through the parasitic lateral NPN BJT 40 to the reference voltage Vss.

[0103] Fig. 9 is a diagram according to some embodiments of the present disclosure, schematically showing a method of operating an ESD protection device. In some embodiments, the ESD protection device is similar to Figure 1 A semiconductor device 20 is provided.

[0104] At operation 80, the method includes receiving an ESD strike at an n-type drain region of an n-type channel MOSFET. In some embodiments, this n-type drain region is similar to n-type drain region 30 (shown in FIG. Figure 1 In some embodiments, this n-channel MOSFET is similar to the n-channel MOSFET 24 (shown in FIG. Figure 1 ).

[0105] In operation 82, the method includes biasing a parasitic vertical NPN BJT in response to an ESD strike. The parasitic vertical NPN BJT has a collector that is an n-type drain region and a base that is a p-type well region, wherein the p-type well region is located above an n-type buried layer in the semiconductor device. The p-type well region is floating to reduce an ESD trigger voltage Vt1 of the vertical NPN BJT for ESD protection. In some embodiments, the p-type well region is similar to the p-type well region 26 (shown in FIG. Figure 1 In some embodiments, the n-type buried layer is similar to the n-type buried layer 28 (shown in FIG. Figure 1 In some embodiments, this parasitic vertical NPN BJT is similar to the parasitic vertical NPN BJT 22 (shown in FIG. Figure 1 ).

[0106] In operation 84, the method includes releasing the ESD via the emitter of the parasitic vertical NPN BJT to the n-type buried layer. In some embodiments, releasing the ESD via the emitter of the parasitic vertical NPN BJT includes releasing the ESD to the n-type buried layer at a reference voltage Vss. In some embodiments, releasing the ESD via the emitter of the parasitic vertical NPN BJT includes releasing the ESD to the n-type buried layer at a power supply voltage Vdd. In some embodiments, the method includes releasing the ESD via a parasitic lateral NPN BJT having a collector that is an n-type drain region, an emitter that is a source region of an n-type channel MOSFET, and a base that is a p-type well region.

[0107] Fig.10 1 is a block diagram showing an example of a computer system 100 configured to provide the semiconductor device and method of the present disclosure according to some embodiments of the present disclosure. Some or all of the design, layout, and manufacturing of a semiconductor device (also referred to as a semiconductor circuit) may be performed by or using the computer system 100. In some embodiments, the computer system 100 includes an electronic design automation (EDA) system. In some embodiments, the semiconductor device is an integrated circuit (IC).

[0108] In some embodiments, computer system 100 is a general purpose computing device including processor 102 and non-transitory computer readable storage medium 104. Computer readable storage medium 104 may be encoded with, for example, storage, computer program code, such as executable instructions 106. Execution of instructions 106 by processor 102 provides design tools that (at least in part) perform some or all of the functions of computer system 100, such as pre-layout simulation, post-layout simulation, routing, rerouting, and final wiring for manufacturing. Further, fabrication machine 108 is included to further perform layout and physically perform the design and manufacture of semiconductor devices. In some embodiments, execution of instructions 106 by processor 102 provides design tools that (at least in part) perform some or all of the functions of computer system 100. In some embodiments, computer system 100 includes a commercial router. In some embodiments, computer system 100 includes an automatic place and route (APR) system.

[0109] The processor 102 is electrically coupled to the computer readable storage medium 104 via the bus 110, and is electrically coupled to the I / O interface 112 via the bus 110. The network interface 114 is also electrically coupled to the processor 102 via the bus 110. The network interface 114 is connected to the network 116, so that the processor 102 and the computer readable storage medium 104 can be connected to external components using the network 116. The processor 102 is configured to execute computer program code or instructions 106 encoded in the computer readable storage medium 104 to enable the computer system 100 to perform some or all of the functions of the computer system 100, such as providing the semiconductor device and method of the present disclosure or other functions of the computer system 100. In some embodiments, the processor 102 is a central processing unit (CPU), a multiprocessor, a distributed processing system (distributed processing system), an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0110] In some embodiments, the computer-readable storage medium 104 is an electronic, magnetic, optical, electromagnetic, infrared and / or semiconductor system or device or apparatus. For example, the computer-readable storage medium 104 includes semiconductor or solid-state memory, magnetic tape, removable computer diskette, random access memory (RAM), read-only memory (ROM), rigid magnetic disk and / or optical disk. In some embodiments using optical disks, the computer-readable storage medium 104 may include compact disk-read only memory (CD-ROM), compact disk-read / write (CD-R / W), and / or digital video disc (DVD).

[0111] In some embodiments, the computer readable storage medium 104 stores computer program code or instructions 106 configured to cause the computer system 100 to perform some or all of the functions of the computer system 100. In some embodiments, the computer readable storage medium 104 also stores information that facilitates the performance of some or all of the functions of the computer system 100. In some embodiments, the computer readable storage medium 104 stores a database 118 that includes one or more of a component library, a digital circuit cell library, and a database.

[0112] The computer system 100 includes an I / O interface 112. The I / O interface 112 is coupled to an external circuit. In some embodiments, the I / O interface 112 includes a keyboard, a keypad, a mouse, a trackball, a trackpad, and / or cursor arrow keys for transmitting information and commands to the processor 102.

[0113] The network interface 114 is coupled to the processor 102 and allows the computer system 100 to communicate with a network 116, where one or more other computer systems are connected to the network 116. The network interface 114 includes a wireless network interface, such as BLUETOOTH, WIFI, WIMAX (Worldwide Interoperability for Microwave Access), GPRS (General Packet Radio Service), or WCDMA (Wideband Code Division Multiple Access); or includes a wired network interface, such as ETHERNET, USB, or IEEE-1364. In some embodiments, some or all of the functions of the computer system 100 can be performed in two or more systems similar to the computer system 100.

[0114] The computer system 100 is configured to receive information via the I / O interface 112. The information received via the I / O interface 112 includes one or more of instructions, data, design criteria, libraries of components and units, and / or other parameters for processing by the processor 102. This information is transmitted to the processor 102 via the bus 110. In addition, the computer system 100 is configured to receive information related to a user interface (UI) via the I / O interface 112. This UI information can be stored in the computer-readable storage medium 104 as UI 120.

[0115] In some embodiments, some or all of the functions of computer system 100 are implemented as a standalone software application executed by a processor. In some embodiments, some or all of the functions of computer system 100 are implemented as a software application that is part of an additional software application. In some embodiments, some or all of the functions of computer system 100 are implemented as a plug-in for a software application. In some embodiments, at least one function of computer system 100 is implemented as a software application that is part of an EDA tool. In some embodiments, some or all of the functions of computer system 100 are implemented as a software application used by computer system 100. In some embodiments, the tool used to generate the layout pattern, such as the one available from CADENCE DESIGN SYSTEMS, Inc. Or other suitable layout generation tool.

[0116] In some embodiments, routing, layout and other processes are implemented as functions of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, such as one or more optical discs such as digital video discs or digital versatile discs (DVDs), magnetic disks such as hard disks, semiconductor memories such as ROM and RAM, and memory cards, etc.

[0117] As described above, the embodiment of the computer system 100 includes a fabrication tool 108 for performing a fabrication process of the computer system 100. For example, based on the final layout, a lithography mask can be generated, and the lithography mask is used to fabricate a semiconductor device by the fabrication tool 108.

[0118] A further aspect of device fabrication combines Fig.11 To be made public, Fig.11 FIG. 1 is a block diagram showing a semiconductor device manufacturing system 122 and a semiconductor device manufacturing process related thereto according to some embodiments. In some embodiments, the manufacturing system 122 is used to manufacture one or more semiconductor masks and / or at least one component in a semiconductor device thin layer based on a layout pattern.

[0119] exist Fig.11 In the present invention, a semiconductor device manufacturing system 122 (hereinafter referred to as "system 122") includes multiple entities, such as a design studio 124, a mask studio 126, and a semiconductor device manufacturer / fabricator ("fab") 128, which interact with each other in the design, development, and manufacturing cycle and / or services related to manufacturing semiconductor devices (e.g., the semiconductor devices described herein). The entities in the system 122 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to one or more other entities or receives services from one or more other entities. In some embodiments, two or more of the design studio 124, the mask studio 126, and the semiconductor device manufacturing plant 128 are owned by a single larger company. In some embodiments, two or more of the design studio 124 , the mask studio 126 , and the semiconductor device fabrication facility 128 are co-located in a common facility and utilize common resources.

[0120] The design studio (or design team) 124 generates a semiconductor device design layout pattern 130. The semiconductor device design layout pattern 130 includes various geometric patterns, or semiconductor device layout patterns designed for semiconductor devices. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute various components of the semiconductor structure to be manufactured. Various thin layers are combined to form various semiconductor device features. For example, a portion of the semiconductor device design layout pattern 130 includes various semiconductor device features to be formed in a semiconductor substrate (e.g., a silicon wafer) and in various material layers disposed on the semiconductor substrate, such as diagonal vias, active regions or regions, gate electrodes, sources and drains, metal lines, area vias, and openings for bonding pads. The design studio 124 executes a design program to generate the semiconductor device design layout pattern 130. The semiconductor device design layout pattern 130 is presented in one or more data files having geometric pattern information. For example, the semiconductor device design layout pattern 130 can be represented in a graphic database system II (GDS II) file format or a DF II file format. In some embodiments, the design process includes analog circuit design, digital circuit design, logic circuit design, standard cell circuit design, power distribution network (PDN) design including power via design, supply voltage track design and reference voltage rail design, placement and routing routines, and physical layout design.

[0121] The mask studio 126 includes data preparation 132 and mask manufacturing 134. The mask studio 126 uses the semiconductor device design layout pattern 130 to manufacture one or more masks 136 for manufacturing various thin layers of semiconductor devices or semiconductor structures. The mask studio 126 performs data preparation 132 for the mask, wherein the semiconductor device design layout pattern 130 is converted into a representative data file (RDF). The mask data preparation 132 provides the RDF to the mask manufacturing 134. The mask manufacturing 134 includes a mask writer that converts the RDF into an image on a substrate, such as a mask (reticle) 136 or a semiconductor wafer 138. The IC design layout 130 is manipulated by the mask data preparation 132 to conform to the specific characteristics of the mask writer and / or the standards of the semiconductor device manufacturing plant 128. In Fig.11 1, reticle data preparation 132 and reticle manufacturing 134 are shown as separate elements. In some embodiments, reticle data preparation 132 and reticle manufacturing 134 may be collectively referred to as reticle data preparation.

[0122] In some embodiments, the data preparation 132 of the mask includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, etc. OPC adjusts the semiconductor device design layout pattern 130. In some embodiments, the data preparation 132 of the mask further includes resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shifting masks, other suitable techniques, etc., or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0123] In some embodiments, the mask data preparation 132 includes a mask rule checker (MRC) that checks the semiconductor device design layout pattern 130 that has undergone the OPC process using a set of mask creation rules, wherein the mask creation rules include specific geometric and / or connection constraints to ensure sufficient margins to account for variability in the semiconductor manufacturing process, etc. In some embodiments, the MRC modifies the semiconductor device design layout pattern 130 to compensate for the constraints during mask fabrication 134, which can undo some of the modifications performed by the OPC to meet the mask creation rules.

[0124] In some embodiments, the mask data preparation 132 includes a lithography process checking (LPC), which simulates a process to be performed by the semiconductor device manufacturing plant 128. LPC simulates this process based on the semiconductor device design layout pattern 130 to create a simulated manufactured device. The process parameters in the LPC simulation may include parameters related to various processes in the semiconductor device manufacturing cycle, parameters related to the machine used to manufacture the semiconductor device, and / or other aspects of the manufacturing process. LPC considers various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, etc., or combinations thereof. In some embodiments, after the simulated manufactured device has been created by LPC, if the simulated device is not close enough in shape to meet the design criteria, OPC and / or MRC may be repeated to further refine the semiconductor device design layout pattern 130.

[0125] For clarity of explanation, the above description of the data preparation 132 of the photomask has been simplified. In some embodiments, the data preparation 132 includes additional features such as logic operations (LOP) to modify the semiconductor device design layout pattern 130 according to manufacturing criteria. In addition, the processes applied to the semiconductor device design layout pattern 130 during the data preparation 132 can be performed in various different orders.

[0126] After the data preparation 132 of the mask and during the mask manufacturing 134, a mask 136 or a group of multiple masks 136 are manufactured based on the modified semiconductor device design layout pattern 130. In some embodiments, the mask manufacturing 134 includes performing one or more lithographic exposures based on the semiconductor device design layout pattern 130. In some embodiments, an electron beam (e-beam) or multiple electron beam mechanisms are used to form a pattern on a mask (photomask or reticle) 136 based on the modified semiconductor device design layout pattern 130. The mask 136 can be formed using various techniques. In some embodiments, the mask 136 is formed using a binary technology. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam, such as an ultraviolet (UV) beam, used to expose an image sensitive material layer (e.g., photoresist) coated on a wafer is blocked by the opaque area and transmitted through the transparent area. In one example, a binary mask version of the mask 136 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chrome) coated in the opaque areas of the binary mask. In other examples, the mask 136 is formed using a phase shift technique. In a phase shift mask (PSM) version of the mask 136, various features in the pattern formed on the phase shift mask are configured to have an appropriate phase difference to improve resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The mask produced by the mask manufacturing 134 is used in various processes. For example, this (or these) mask is used in an ion implantation process to form various doped regions in the semiconductor wafer 138, used in an etching process to form various etched regions in the semiconductor wafer 138, and / or used in other suitable processes.

[0127] Semiconductor device manufacturing plant 128 includes wafer fabrication 140. Semiconductor device manufacturing plant 128 is a semiconductor device manufacturing enterprise, including one or more manufacturing facilities for manufacturing various semiconductor device products. In some embodiments, semiconductor device manufacturing plant 128 is a semiconductor foundry. For example, there may be a manufacturing facility for front-end-of-line (FEOL) manufacturing of multiple semiconductor device products, while a second manufacturing facility may provide back-end-of-line (BEOL) manufacturing for interconnection and packaging of semiconductor device products, and a third manufacturing facility that provides other services to the foundry enterprise.

[0128] The semiconductor device manufacturing plant 128 uses the mask 136 manufactured by the mask studio 126 to manufacture the semiconductor structure or semiconductor device 142 of the present disclosure. Therefore, the semiconductor device manufacturing plant 128 at least indirectly uses the semiconductor device design layout pattern 130 to manufacture the semiconductor structure or semiconductor device 142 of the present disclosure. In addition, the semiconductor wafer 138 includes a silicon substrate or other suitable substrate having a material layer formed thereon, and the conductor wafer 138 further includes one or more of various doped regions, dielectric features, multi-level interconnects, etc. (formed in subsequent manufacturing operations). In some embodiments, the semiconductor wafer 138 is manufactured by the semiconductor device manufacturing plant 128 using the mask 136 to form the semiconductor structure or semiconductor device 142 of the present disclosure. In some embodiments, the manufacture of the semiconductor device includes performing one or more lithography exposures based at least indirectly on the semiconductor device design layout pattern 130.

[0129] Embodiments disclosed in the present application provide a semiconductor device including a parasitic vertical NPN BJT for releasing ESD current. The parasitic vertical NPN BJT is configured to release the ESD current to a reference voltage Vss or a power supply voltage Vdd. In some embodiments, the semiconductor device includes a parasitic lateral NPN BJT for releasing the ESD current. In some embodiments, the parasitic vertical NPN BJT and the parasitic lateral NPN BJT both release the ESD current simultaneously. In some embodiments, the semiconductor device is an RPO MOS device.

[0130] The semiconductor device includes an n-type buried layer, a p-type well region above the n-type buried layer, and a snapback device for ESD protection. The snapback device includes an n-type channel MOSFET, which includes an n-type drain region and an n-type source region. The parasitic vertical NPN BJT includes a collector located in the n-type drain region, an emitter located in the n-type buried layer, and a base located in the p-type well region, wherein the p-type well region is floating and not connected to a reference voltage or a power supply voltage. Through the floating p-type well region, the parasitic vertical NPNBJT has a lower ESD trigger voltage Vt1. In some embodiments, the semiconductor device includes a parasitic lateral NPNBJT, which includes a collector located in the n-type drain region, an emitter located in the n-type source region, and a base located in the p-type well region, wherein the p-type well region is floating and not connected to a reference voltage or a power supply voltage.

[0131] According to some embodiments, the present disclosure provides a semiconductor device. The semiconductor device includes an n-type buried layer, a p-type well region located above the n-type buried layer, an n-type channel metal oxide semiconductor field effect transistor including an n-type drain region, and a vertical NPN bipolar junction transistor. The vertical NPN bipolar junction transistor has a collector that is an n-type drain region and a base that is a p-type well region. The p-type well region is floating.

[0132] In some embodiments, the emitter of the vertical NPN bipolar junction transistor is an n-type buried layer. In some embodiments, the n-type buried layer is electrically connected to a reference voltage Vss.

[0133] In some embodiments, the n-type drain region is electrically connected to an input / output pad. In some embodiments, the n-type drain region includes an n+ region. In some embodiments, the n-channel metal oxide semiconductor field effect transistor includes a floating source.

[0134] In some embodiments, the vertical NPN bipolar junction transistor has an emitter electrically connected to an n-type buried layer of a reference voltage Vss, and the n-type channel metal oxide semiconductor field effect transistor includes a source region electrically connected to the reference voltage Vss, and the above-mentioned semiconductor device further includes a lateral NPN bipolar junction transistor, the lateral NPN bipolar junction transistor has a collector that is an n-type drain region, an emitter that is a source region, and a base that is a floating p-type well region.

[0135] In some embodiments, the vertical NPN bipolar junction transistor has an emitter that is electrically connected to an n-type buried layer of a power supply voltage Vdd.

[0136] In some embodiments, the source region included in the n-channel metal oxide semiconductor field effect transistor is electrically connected to a reference voltage Vss, and the above-mentioned semiconductor device further includes a lateral NPN bipolar junction transistor, the lateral NPN bipolar junction transistor has a collector that is an n-type drain region, an emitter that is a source region, and a base that is a floating p-type well region.

[0137] According to a further embodiment, the present disclosure provides a semiconductor device. The semiconductor device includes an n-type buried layer electrically connected to a reference voltage Vss or a power supply voltage Vdd; a p-type well region located above the n-type buried layer; an n-type channel metal oxide semiconductor field effect transistor including an n-type drain region electrically connected to an input / output pad; and a vertical NPN bipolar junction transistor. The vertical NPN bipolar junction transistor has a collector that is an n-type drain region, an emitter that is an n-type buried layer, and a base that is a p-type well region. The p-type well region is floating.

[0138] In some embodiments, the n-type channel metal oxide semiconductor field effect transistor includes a floating source. In some embodiments, the n-type buried layer is electrically connected to a reference voltage Vss.

[0139] In some embodiments, the source region included in the n-channel metal oxide semiconductor field effect transistor is electrically connected to a reference voltage Vss, and the above-mentioned semiconductor device further includes a lateral NPN bipolar junction transistor, the lateral NPN bipolar junction transistor has a collector that is an n-type drain region, an emitter that is a source region, and a base that is a floating p-type well region.

[0140] In some embodiments, the n-type buried layer is electrically connected to a power supply voltage Vdd. In some embodiments, the source region of the n-type channel metal oxide semiconductor field effect transistor is electrically connected to a reference voltage Vss, and the semiconductor device further comprises a lateral NPN bipolar junction transistor, the collector of the lateral NPN bipolar junction transistor is an n-type drain region, the emitter is a source region, and the base is a floating p-type well region.

[0141] According to further disclosed aspects, the present disclosure provides an operating method for an electrostatic discharge protection device. The operating method for the electrostatic discharge protection device includes: receiving electrostatic discharge at an n-type drain region of an n-channel metal oxide semiconductor field effect transistor; as a response to the electrostatic discharge, biasing a vertical NPN bipolar junction transistor, the vertical NPN bipolar junction transistor having a collector as an n-type drain region and a base as a p-type well region located above an n-type buried layer, wherein the p-type well region is floating; and releasing the electrostatic discharge to the n-type buried layer via the emitter of the vertical NPN bipolar junction transistor.

[0142] In some embodiments, discharging the electrostatic discharge through the emitter of the vertical NPN bipolar junction transistor includes discharging the electrostatic discharge to an n-type buried layer at a reference voltage Vss.

[0143] In some embodiments, the operating method of the electrostatic discharge protection device further includes: releasing electrostatic discharge through a lateral NPN bipolar junction transistor, wherein the collector of the lateral NPN bipolar junction transistor is an n-type drain region, the emitter is a source region of an n-type channel metal oxide semiconductor field effect transistor, and the base is a p-type well region.

[0144] In some embodiments, discharging the electrostatic discharge through the emitter of the vertical NPN bipolar junction transistor includes discharging the electrostatic discharge to an n-type buried layer at a power supply voltage Vdd.

[0145] In some embodiments, the operating method of the electrostatic discharge protection device further includes: releasing electrostatic discharge through a lateral NPN bipolar junction transistor, wherein the collector of the lateral NPN bipolar junction transistor is an n-type drain region, the emitter is a source region of an n-type channel metal oxide semiconductor field effect transistor, and the base is a p-type well region.

[0146] The foregoing disclosure summarizes the features of multiple embodiments so that those with ordinary knowledge in the art can better understand the aspects of the present disclosure. Those with ordinary knowledge in the art should understand that they can easily design or modify other processes and structures based on the present disclosure to accomplish the same purposes and / or achieve the same advantages as the embodiments or examples introduced herein. Those with ordinary knowledge in the art should also understand that these equivalent structures do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications may be made to the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: include: an n-type buried layer; a p-type well region located above the n-type buried layer; an n-channel MOSFET including an n-type drain region; and A vertical NPN bipolar junction transistor has a collector as the n-type drain region and a base as the p-type well region, wherein the p-type well region is floating.

2. The semiconductor device according to claim 1, wherein The vertical NPN bipolar junction transistor has an emitter electrically connected to the n-type buried layer of a reference voltage, and the n-type channel metal oxide semiconductor field effect transistor includes a source region electrically connected to the reference voltage, and the semiconductor device further includes a lateral NPN bipolar junction transistor, the lateral NPN bipolar junction transistor has a collector that is the n-type drain region, an emitter that is the source region, and a base that is the floating p-type well region.

3. The semiconductor device according to claim 1, wherein: The vertical NPN bipolar junction transistor has an emitter which is electrically connected to the n-type buried layer of a power supply voltage.

4. The semiconductor device according to claim 3, wherein: The n-channel metal oxide semiconductor field effect transistor includes a source region electrically connected to a reference voltage, and the semiconductor device further includes a lateral NPN bipolar junction transistor, wherein the lateral NPN bipolar junction transistor has a collector as the n-type drain region, an emitter as the source region, and a base as the floating p-type well region.

5. A semiconductor device, characterized in that: include: an n-type buried layer electrically connected to a reference voltage or a power supply voltage; a p-type well region located above the n-type buried layer; an n-channel metal oxide semiconductor field effect transistor including an n-type drain region electrically connected to an input / output pad; as well as a vertical NPN bipolar junction transistor, having a collector as the n-type drain region, an emitter as the n-type buried layer, and a base as the p-type well region, The p-type well region is floating.

6. The semiconductor device according to claim 5, wherein: The n-type channel metal oxide semiconductor field effect transistor includes a floating source.

7. The semiconductor device according to claim 5, wherein: The n-type buried layer is electrically connected to the reference voltage.

8. The semiconductor device according to claim 7, wherein: The n-channel metal oxide semiconductor field effect transistor includes a source region electrically connected to the reference voltage, and the semiconductor device further includes a lateral NPN bipolar junction transistor, wherein the lateral NPN bipolar junction transistor has a collector as the n-type drain region, an emitter as the source region, and a base as the floating p-type well region.

9. The semiconductor device according to claim 5, wherein: The n-type buried layer is electrically connected to the power supply voltage.

10. The semiconductor device according to claim 9, wherein: The n-channel metal oxide semiconductor field effect transistor includes a source region electrically connected to the reference voltage Vss, and the semiconductor device further includes a lateral NPN bipolar junction transistor, wherein the lateral NPN bipolar junction transistor has a collector which is the n-type drain region, an emitter which is the source region, and a base which is the floating p-type well region.

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