Silicon optical chip compatible with 400G DR4 and 800G DR8 and optical engine
By designing silicon optical chips compatible with 400G DR4 and 800G DR8, different configurations are achieved by cutting reserved blank areas, which solves the high cost and long test time problems caused by independent design of traditional silicon optical chips, and achieves cost savings and time reduction.
Patent Information
- Application Number
- CN202422106644.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-28
- Publication Date
- 2025-05-27
- Estimated Expiration
- 2034-08-28
AI Technical Summary
Traditional DR8 and DR4 silicon optical chips are designed independently, resulting in high design and testing costs and long-term problems.
A silicon optical chip compatible with 400G DR4 and 800G DR8 is designed, with two in-optical waveguides and eight out-optical waveguides, and a blank area is reserved for cutting, which can be compatible with different application scenarios and achieve different configurations through cutting or not cutting.
It realizes only one tapping and testing, and is compatible with 400G DR4 and 800G DR8 optical engines, saving design and testing costs and shortening test time.
Smart Images
Figure CN222913930U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of silicon photonics chips, and particularly relates to a silicon photonics chip and an optical engine compatible with 400G DR4 and 800G DR8. Background Art
[0002] A traditional DR8 silicon photonics chip has two input waveguides and eight output waveguides. The optical path of one of the two input optical waveguides is divided into four paths and then coupled with four of the eight output waveguides, and the optical path of the other input optical waveguide is divided into four paths and then coupled with the remaining four output waveguides of the eight output waveguides, or it can be understood as a 1-to-4 scheme.
[0003] A DR4 silicon photonics chip has one input waveguide and four output waveguides. The optical path of the input optical waveguide is divided into four paths and then coupled with the four output waveguides, or it can be understood as a 1-to-4 scheme.
[0004] In the current solution, the DR8 silicon photonics chip and the DR4 silicon photonics chip are two independent chips, which are designed, fabricated, and tested separately. This not only incurs high costs but also takes a long time for testing. Content of the Utility Model
[0005] The technical problem to be solved by the utility model is to provide a silicon photonics chip and an optical engine compatible with 400G DR4 and 800G DR8 to overcome the deficiencies in the above-mentioned prior art.
[0006] The technical solution of the utility model to solve the above technical problem is as follows: A silicon photonics chip compatible with 400G DR4 and 800G DR8 includes: a chip body, on one side of the chip body, there are two input waveguides and eight output waveguides. The eight output waveguides are located between the two input waveguides, and the eight output waveguides are divided into two groups with four in each group and are distributed alternately. The area of the chip body between the two groups of output waveguides is a reserved blank area. The reserved blank area has a cutting area that divides the chip body into two parts. The optical path of the input waveguide on the same side of the reserved blank area is divided into four paths and then coupled with four output waveguides.
[0007] On the basis of the above technical solution, the utility model can be further improved as follows.
[0008] Further, the distance between two adjacent output waveguides in each group of output waveguides is 0.25 mm, and the width of the reserved blank area is 0.5 mm.
[0009] Further, the width of the cutting area is 0.1 mm to 0.2 mm.
[0010] Further, the width of the cutting area is 0.1 mm.
[0011] Based on the above technical solution, the present utility model further provides an optical engine, which includes the above silicon photonics chip compatible with 400G DR4 and 800G DR8.
[0012] The beneficial effects of the present utility model are as follows:
[0013] When the silicon photonics chip is applied to an 800G DR8 optical engine, there is no need to cut the silicon photonics chip. Two input optical waveguides are respectively coupled to two optical emission ends, and the eight output optical waveguides of the silicon photonics chip are coupled to an eight-channel fiber array. For the eight-channel fiber array used, only a predetermined spacing needs to be left in the middle.
[0014] When the silicon photonics chip is applied to a 400G DR4 optical engine, the silicon photonics chip is cut along the cutting area to be cut into two mirror-image DR4 silicon photonics chips. One input optical waveguide of each DR4 silicon photonics chip is coupled to one optical emission end, and the four output optical waveguides of each DR4 silicon photonics chip are coupled to a four-channel fiber array.
[0015] According to this solution, only one type of chip needs to be designed and taped out once, and it can be compatible with 400G DR4 and 800G DR8 optical engines, achieving the purpose of cost savings. At the same time, when the silicon photonics chip is applied to a 400G DR4 optical engine, the chip can be tested first. Specifically, it only needs to be tested once with an eight-channel fiber array. Compared with two traditional DR4 silicon photonics chips, it only needs to be tested once (two traditional DR4 silicon photonics chips should be tested twice). After passing the test, it is cut, saving test time compared with the prior art. Description of the Drawings
[0016] Figure 1 It is a structural diagram of the silicon photonics chip compatible with 400G DR4 and 800G DR8 in the present utility model;
[0017] Figure 2 It is a structural diagram of the silicon photonics chip compatible with 400G DR4 and 800G DR8 in the present utility model when applied to an 800G DR8 optical engine;
[0018] Figure 3 It is the first structural diagram of the silicon photonics chip compatible with 400G DR4 and 800G DR8 in the present utility model when applied to a 400G DR4 optical engine;
[0019] Figure 4 It is the second structural diagram of the silicon photonics chip compatible with 400G DR4 and 800G DR8 in the present utility model when applied to a 400G DR4 optical engine.
[0020] In the drawings, the list of components represented by each reference numeral is as follows:
[0021] 1. Chip body, 110. Reserved blank area, 120. Cutting area, 2. Input optical waveguide, 3. Output optical waveguide, 4. Optical emission end, 5. Eight-channel fiber optic array, 6. Four-channel fiber optic array. Detailed implementation
[0022] The principles and features of the present utility model will be described below in conjunction with the accompanying drawings. The examples given are only for explaining the present utility model and are not intended to limit the scope of the present utility model.
[0023] Example 1
[0024] As Figure 1 shown, a silicon photonics chip compatible with 400G DR4 and 800G DR8 includes: a chip body 1. There are two input optical waveguides 2 and eight output optical waveguides 3 on one side of the chip body 1. Among them, the eight output optical waveguides 3 are located between the two input optical waveguides 2, and the eight output optical waveguides 3 are divided into two groups with four in each group and are distributed alternately. The area of the chip body 1 between the two groups of output optical waveguides 3 is the reserved blank area 110. The reserved blank area 110 means that no electronic components are arranged in this area. In addition, the reserved blank area 110 has a cutting area 120 that divides the chip body 1 into two. The optical paths of the input optical waveguides 2 on the same side of the reserved blank area 110 are each divided into four paths and then coupled to four output optical waveguides 3.
[0025] When this silicon photonics chip is applied to an 800G DR8 optical engine, the silicon photonics chip does not need to be cut. The two input optical waveguides 2 are respectively coupled to two optical emission ends, and the eight output optical waveguides 3 of the silicon photonics chip are coupled to an eight-channel fiber optic array. For the eight-channel fiber optic array used, only a predetermined spacing needs to be left in the middle.
[0026] When this silicon photonics chip is applied to a 400G DR4 optical engine, the silicon photonics chip is cut along the cutting area 120 to be cut into two mirror-image DR4 silicon photonics chips. One input optical waveguide 2 of each DR4 silicon photonics chip is coupled to an optical emission end, and the four output optical waveguides 3 of each DR4 silicon photonics chip are coupled to a four-channel fiber optic array.
[0027] According to this solution, only one type of chip can be designed, and the wafers can be processed once, and it can be compatible with 400G DR4 and 800G DR8 optical engines, achieving the purpose of saving costs. At the same time, when this silicon photonics chip is applied to a 400G DR4 optical engine, the chip can be tested first. Specifically, it only needs to be tested once with an eight-channel fiber optic array. Compared with two traditional DR4 silicon photonics chips, it only needs to be tested once (two traditional DR4 silicon photonics chips should be tested twice). After passing the test, it is cut, saving test time compared with the prior art.
[0028] Example 2
[0029] As Figure 1 shown, this embodiment is a further improvement based on Embodiment 1, specifically as follows:
[0030] The spacing between adjacent two output optical waveguides 3 in each group of output optical waveguides 3 is 0.25 mm, and the width of the reserved blank area 110 is 0.5 mm. When this silicon photonic chip is applied to an 800G DR8 optical engine, only one channel in the middle of the eight-channel fiber array to be used needs to be empty.
[0031] Embodiment 3
[0032] As Figure 1 shown, this embodiment is a further improvement based on Embodiment 1 or 2, specifically as follows:
[0033] The width of the cutting area 120 is 0.1 mm to 0.2 mm, and in this embodiment, the width of the cutting area 120 is preferably 0.1 mm.
[0034] Embodiment 4
[0035] This embodiment is a further improvement based on Embodiment 1 or 2, specifically as follows:
[0036] An optical engine includes: a silicon photonic chip compatible with 400G DR4 and 800G DR8 as described in any one of Embodiments 1 to 3.
[0037] As Figure 2 shown, when this silicon photonic chip is applied to an 800G DR8 optical engine, the silicon photonic chip does not need to be cut. Two input optical waveguides 2 are respectively coupled to two optical emission ends 4, and the eight output optical waveguides 3 of the silicon photonic chip are coupled to an eight-channel fiber array 5. And only a predetermined spacing in the middle of the eight-channel fiber array 5 to be used needs to be empty.
[0038] As Figure 3 、 Figure 4 shown, when this silicon photonic chip is applied to a 400G DR4 optical engine, the silicon photonic chip is cut along the cutting area 120 to be cut into two mirrored DR4 silicon photonic chips. One input optical waveguide 2 of each DR4 silicon photonic chip is coupled to an optical emission end 4, and four output optical waveguides 3 of each DR4 silicon photonic chip are coupled to a four-channel fiber array 6.
[0039] Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention.
Claims
1. A silicon photonic chip compatible with 400G DR4 and 800G DR8, characterized in that: include: A chip body (1) is provided with two input light waveguides (2) and eight output light waveguides (3) on one side of the chip body (1); the eight output light waveguides (3) are located between the two input light waveguides (2), and the eight output light waveguides (3) are arranged alternately in two groups of four each; the area of the chip body (1) located between the two groups of output light waveguides (3) is a reserved blank area (110); the reserved blank area (110) has a cutting area (120) for dividing the chip body (1) into two; and the optical paths of the input light waveguides (2) located on the same side of the reserved blank area (110) are evenly divided into four paths and then coupled with the four output light waveguides (3).
2. The silicon photonic chip compatible with 400G DR4 and 800G DR8 according to claim 1, characterized in that: The spacing between two adjacent light output waveguides (3) in each group of light output waveguides (3) is 0.25 mm, and the width of the reserved blank area (110) is 0.5 mm.
3. A silicon photonic chip compatible with 400G DR4 and 800G DR8 according to claim 1 or 2, characterized in that: The width of the cutting area (120) is 0.1 mm to 0.2 mm.
4. The silicon photonic chip compatible with 400G DR4 and 800G DR8 according to claim 3, characterized in that: The width of the cutting area (120) is 0.1 mm.
5. A light engine, characterized in that: include: A silicon photonic chip compatible with 400G DR4 and 800G DR8 as claimed in any one of claims 1 to 4.