Solar cell, photovoltaic module and photovoltaic system

Abstract

The utility model is suitable for the technical field of photovoltaic cells, and provides a solar cell, a photovoltaic module and a photovoltaic system.The solar cell comprises a silicon substrate, a first doping layer and a second doping layer, the silicon substrate is provided with a first surface and a second surface which are oppositely arranged, the first doping layer is arranged on the first surface, the second doping layer is arranged on the second surface, and the first doping layer is arranged on the first surface. At least one of the first doping layer and the second doping layer extends along the side face of the silicon substrate and is in direct or indirect conductive contact with the other one of the first doping layer and the second doping layer to form a contact area. Therefore, the conversion efficiency of the solar cell is basically not lost, the hot spot risk is reduced, and the reliability and the power generation capacity of the solar cell are improved.

Description

Technical Field

[0001] The present application belongs to the field of photovoltaic cell technology, and in particular to solar cells, photovoltaic modules and photovoltaic systems. Background Art

[0002] Photovoltaic modules composed of multiple cells are usually installed in open areas with plenty of sunshine. In long-term use, it is inevitable that flying birds, dust, fallen leaves and other obstructions will fall on the photovoltaic modules. These obstructions will form shadows on the photovoltaic modules. In large photovoltaic module arrays, the row spacing is not suitable and shadows can be formed on each other. Due to the existence of local shadows, the current and voltage of some solar cell chips in the photovoltaic module have changed. Conventional solar cells have diode characteristics, and the obscured cells are reverse biased, which increases the product of the local current and voltage of the photovoltaic module, and its power consumption is extremely high, resulting in local temperature rise on these photovoltaic modules. Defects in some cell chips in the photovoltaic module may also cause the module to heat up locally during operation. This phenomenon is called the "hot spot effect". Therefore, photovoltaic modules with existing batteries have a high risk of hot spots in actual operation. After being packaged into photovoltaic modules, the hot spot effect may reduce the power of the module and bring safety issues such as local temperature rise. In related technologies, the risk of hot spots in photovoltaic modules is often avoided by setting bypass diodes, but this method will significantly reduce the power of the modules. Therefore, it is urgent to use other technical means to reduce the "hot spot effect" while maintaining the high power output of the modules. Utility Model Content

[0003] The embodiment of the present application provides a solar cell, aiming to solve the problem of how to reduce the "hot spot effect" while maintaining high power output of the component.

[0004] The embodiment of the present application is implemented as follows: a solar cell, comprising:

[0005] A silicon substrate having a first surface and a second surface disposed opposite to each other;

[0006] a first doped layer, the first doped layer being disposed on the first surface;

[0007] A second doping layer, wherein the second doping layer is disposed on the second surface, and the second doping layer has a polarity opposite to that of the first doping layer;

[0008] At least one of the first doping layer and the second doping layer extends along a side surface of the silicon substrate and is in conductive contact with the other of the first doping layer and the second doping layer to form a contact region.

[0009] Furthermore, the first doped layer has a first extension portion extending along the side of the silicon substrate, and the first extension portion is arranged on the side of the silicon substrate. The second doped layer has a second extension portion extending along the side of the silicon substrate, and the second extension portion is arranged on the side of the silicon substrate. The first extension portion and the second extension portion are in direct conductive contact on the side of the silicon substrate.

[0010] Furthermore, the first doped layer has a third extension portion extending along the side of the silicon substrate to the second surface, the third extension portion is arranged on the side of the silicon substrate and at least a portion of the second surface, and the third extension portion is in direct conductive contact with the second doped layer on the second surface.

[0011] Furthermore, the second doped layer has a fourth extension portion extending along the side of the silicon substrate to the first surface, the fourth extension portion is arranged on the side of the silicon substrate and at least a portion of the first surface, and the fourth extension portion and the first doped layer are in direct conductive contact on the first surface.

[0012] Furthermore, the solar cell also includes: a first passivation layer, the first passivation layer is arranged between the first doped layer and the silicon substrate, and the first doped layer is indirectly conductively contacted with the second doped layer through the first passivation layer; and / or a second passivation layer, the second passivation layer is arranged between the second doped layer and the silicon substrate, and the second doped layer is indirectly conductively contacted with the first doped layer through the second passivation layer.

[0013] Furthermore, one of the first passivation layer and the second passivation layer includes at least one of an amorphous silicon layer, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon carbonitride oxycarbon layer, a titanium oxide layer, a hafnium oxide layer and an aluminum oxide layer.

[0014] Furthermore, each of the first passivation layer and the second passivation layer has a thickness of 0.5 nm to 20 nm.

[0015] Furthermore, each of the first passivation layer and the second passivation layer has a thickness of 0.5 nm to 10 nm.

[0016] Furthermore, the first doped layer and the second doped layer are in direct conductive contact to form the contact region, and a ratio of a total area of ​​the contact region to an area of ​​the first surface or the second surface is in a range of 1E-8 to 0.03.

[0017] Furthermore, the first doped layer and the second doped layer are indirectly conductively contacted via the first passivation layer and / or the second passivation layer to form the contact region, and a ratio of the total area of ​​the contact region to the area of ​​the first surface or the second surface is in a range of 1E-8 to 0.03.

[0018] Furthermore, the first doped layer and the second doped layer form a conductive channel in the contact area, and the first doped layer and the second doped layer release current through the conductive channel, wherein under a reverse bias voltage of -12V or less than -12V, the current density of the solar cell is in the range of 0.1-5mA / cm 2 .

[0019] Furthermore, the first doped layer and the second doped layer form a conductive channel in the contact area, and the first doped layer and the second doped layer release current through the conductive channel, wherein under a reverse bias voltage of -12V or less than -12V, the current density of the solar cell is in the range of greater than 1.5mA / cm 2 Less than or equal to 5mA / cm 2 .

[0020] Furthermore, the contact area is located on at least one side of the first surface of the solar cell or the second surface of the solar cell or the side of the solar cell, or is located in a partial area of ​​at least one side of the first surface or the second surface of the solar cell or the side of the solar cell.

[0021] The embodiment of the present application also provides a photovoltaic module, including the above-mentioned solar cell.

[0022] An embodiment of the present application also provides a photovoltaic system, comprising the above-mentioned photovoltaic assembly.

[0023] The solar cell provided by the present application has a first doped layer disposed on the first surface of a silicon substrate, and a second doped layer disposed on the second surface of the silicon substrate. The first doped layer, the silicon substrate, and the second doped layer constitute a pn junction structure, thereby realizing the separation and collection of photogenerated carriers of the solar cell. In particular, at least one of the first doped layer and the second doped layer bypasses the side of the silicon substrate and contacts the second doped layer and the other of the first doped layer. When a reverse voltage is applied to both ends of the solar cell, a composite leakage current of an appropriate size can be generated. In this way, the risk of hot spots can be reduced while ensuring that the conversion efficiency of the solar cell is basically not lost, thereby improving the reliability and power generation capacity of the solar cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 The solar cell structure cross section provided in the embodiment of the present application is Figure 1 ;

[0025] Figure 2 The solar cell structure cross section provided in the embodiment of the present application is Figure 2 ;

[0026] Figure 3 The solar cell structure cross section provided in the embodiment of the present application is Figure 3 ;

[0027] Figure 4 The solar cell structure cross section provided in the embodiment of the present application is Figure 4 ;

[0028] Figure 5 The solar cell structure cross section provided in the embodiment of the present application is Figure 5 ;

[0029] Figure 6 The solar cell structure cross section provided in the embodiment of the present application is Figure 6 ;

[0030] Figure 7 The solar cell structure cross section provided in the embodiment of the present application is Figure 7 ;

[0031] Figure 8 The solar cell structure cross section provided in the embodiment of the present application is Figure 8 ;

[0032] Fig. 9 The solar cell structure cross section provided in the embodiment of the present application is Figure 9 ;

[0033] Fig.10 The solar cell structure cross section provided in the embodiment of the present application is Figure 10 ;

[0034] Fig.11 The solar cell structure cross section provided in the embodiment of the present application is Figure 10 one;

[0035] Fig.12 The solar cell structure cross section provided in the embodiment of the present application is Figure 10 two;

[0036] Fig.13 The solar cell structure cross section provided in the embodiment of the present application is Figure 10 three;

[0037] Fig.14 The solar cell structure cross section provided in the embodiment of the present application is Figure 10 Four;

[0038] Fig.15 The solar cell structure cross section provided in the embodiment of the present application is Figure 10 five;

[0039] Fig.16 The solar cell structure cross section provided in the embodiment of the present application is Figure 10 six;

[0040] Fig.17 The solar cell structure cross section provided in the embodiment of the present application is Figure 10 seven;

[0041] Fig.18 The solar cell structure cross section provided in the embodiment of the present application is Figure 10 eight;

[0042] Fig.19 The solar cell structure cross section provided in the embodiment of the present application is Figure 10 Nine;

[0043] Fig. 20 The solar cell structure cross section provided in the embodiment of the present application is Figure 2 ten;

[0044] Fig.21 The solar cell structure cross section provided in the embodiment of the present application is Figure 2 eleven;

[0045] Fig. 22 The solar cell structure cross section provided in the embodiment of the present application is Figure 2 twelve;

[0046] Fig.23 The solar cell structure cross section provided in the embodiment of the present application is Figure 2 Thirteen;

[0047] Fig.24 The solar cell structure cross section provided in the embodiment of the present application is Figure 2 fourteen;

[0048] Fig.25 The solar cell structure cross section provided in the embodiment of the present application is Figure 2 fifteen;

[0049] Fig.26 The solar cell structure cross section provided in the embodiment of the present application is Figure 2 sixteen;

[0050] Fig. 27 The solar cell structure cross section provided in the embodiment of the present application is Figure 2 XVII;

[0051] Fig.28 The solar cell structure cross section provided in the embodiment of the present application is Figure 2 eighteen;

[0052] Fig.29 The solar cell structure cross section provided in the embodiment of the present application is Figure 2 nineteen;

[0053] Fig.30 The solar cell structure cross section provided in the embodiment of the present application is Figure 3 ten;

[0054] Fig.31 The solar cell structure cross section provided in the embodiment of the present application is Figure 3 eleven;

[0055] Fig.32 The solar cell structure cross section provided in the embodiment of the present application is Figure 3 twelve.

[0056] 100. Solar cell, 111. First surface, 112. Second surface, 113. Side, 10. Silicon substrate, 20. First doped layer, 30. Second doped layer, 40. First passivation layer, 50. First extension portion, 60. Second extension portion, 70. Third extension portion, 80. Second passivation layer, 90. Fourth extension portion. DETAILED DESCRIPTION

[0057] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0058] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "plurality" means two or more, unless otherwise clearly and specifically defined.

[0059] The photovoltaic system in the embodiment of the present application may include the photovoltaic component in the embodiment of the present application, and the photovoltaic component in the embodiment of the present application may include a plurality of solar cells 100 in the embodiment of the present application.

[0060] In some embodiments, multiple solar cells 100 in a photovoltaic module can be connected in series in sequence to form a battery string. The battery strings can be connected in series, in parallel, or in a combination of series and parallel to achieve current bus output. For example, the connection between the solar cells 100 can be achieved by welding welding strips, and the connection between the battery strings can be achieved by bus bars.

[0061] In the solar cell 100 provided in the present application, a first doping layer 20 is disposed on the first surface of the silicon substrate 10, and a second doping layer 30 is disposed on the second surface of the silicon substrate 10. The first doping layer 20, the silicon substrate 10, and the second doping layer 30 constitute a pn junction structure, so as to realize the separation and collection process of photogenerated carriers of the solar cell 100. In particular, at least one of the first doping layer 20 and the second doping layer 30 contacts the second doping layer 30 and the other of the first doping layer 20 via the side of the silicon substrate 10, so as to realize the conductive connection between the first doping layer 20 and the second doping layer 30. When the solar cell 100 generates electricity normally, the contact area between the first doping layer 20 and the second doping layer 30 also performs photoelectric conversion to generate electricity, thereby improving the power generation of the solar cell 100. At the component end, when the solar cell 100 is shaded, the other solar cells connected in series with it provide reverse current to the shaded solar cell 100, and a composite leakage current of appropriate size can be generated between the first doping layer 20 and the second doping layer 30 of the solar cell 100, thereby reducing the voltage across the shaded solar cell 100 (the voltage is less than the sum of the voltages of other solar cells connected in series with the solar cell and not shaded), and the heat generation power of the solar cell 100 will be reduced, thereby reducing the high heat risk of the hot spot effect. Secondly, by deliberately introducing a conductive contact structure into the solar cell 100, it has a protective effect on the hot spot effect caused by defects in the silicon substrate 10 itself (that is, it can reduce the heat generated by the defects), and can reduce or even eliminate the control requirements for defects in the silicon substrate 10, while reducing the risk of hot spots caused by defects in the silicon substrate 10, the manufacturing capacity of the solar cell 100 is improved.

[0062] That is to say, by adopting the technical solution of the present application, in the present application, by reasonably designing the area of ​​the conductive contact structure and its position in the solar cell 100, the relationship between the photoelectric conversion efficiency of the solar cell 100 and the control of the hot spot risk can be balanced, and the hot spot risk can be reduced while ensuring that there is no significant loss in the conversion efficiency of the solar cell 100. At the same time, the defect control requirements of the solar cell 100 can be reduced or even eliminated, thereby improving the manufacturing and production capacity of the solar cell 100.

[0063] In addition, for a battery string composed of multiple solar cells 100, compared with the traditional method of connecting bypass diodes in reverse parallel at both ends of the battery string, under the solar cell structure design of the present application, it is equivalent to that each solar cell has a bypass circuit, so in some embodiments, in the photovoltaic module 200, it can reduce or omit the use of bypass diodes to reduce costs. In some embodiments, in the photovoltaic module 200, a bypass diode can also be set, which is not specifically limited here.

[0064] See also Figure 1 to Figure 32The solar cell 100 in the embodiment of the present application may include a silicon substrate 10 , a first doping layer 20 , a second doping layer 30 , a first passivation layer 40 and a second passivation layer 80 .

[0065] The silicon substrate 10 has a first surface and a second surface that are opposite to each other. The first doping layer 20 is disposed on the first surface, and the second doping layer 30 is disposed on the second surface. The second doping layer 30 has opposite polarity to the first doping layer 10 .

[0066] At least one of the first doping layer 20 and the second doping layer 30 extends along the side of the silicon substrate 10 and is in direct or indirect conductive contact with the other of the first doping layer 30 and the second doping layer 20 to form a contact region. Specifically, one of the first doping layer and the second doping layer may extend along the side of the silicon substrate, or the first doping layer and the second doping layer may extend along the side of the silicon substrate at the same time, thereby making conductive contact with each other.

[0067] It is particularly noted that the thickness of the first doping layer can be uniform, that is, the overall thickness of the first doping layer is consistent, and the thickness of the first doping layer can also be non-uniform, that is, the overall thickness of the first doping layer is inconsistent, the thickness of one part of the first doping layer is greater than the thickness of another part of the first doping layer, and the thickness of the second doping layer is the same as that of the first doping layer, which will not be repeated here and the present application does not impose any restrictions on this.

[0068] In some embodiments, the material of the silicon substrate 10 may be an elemental semiconductor material. Specifically, the elemental semiconductor material is composed of a single element, such as silicon or germanium. The elemental semiconductor material may be single crystal, polycrystalline, amorphous or microcrystalline, for example, silicon may be at least one of single crystal silicon, polycrystalline silicon, amorphous silicon or microcrystalline silicon.

[0069] In some embodiments, the silicon substrate 10 may be an N-type semiconductor substrate, a P-type semiconductor substrate or an intrinsic semiconductor substrate. The N-type semiconductor substrate is doped with an N-type doping element, which may be any one of the V-group elements such as phosphorus (P), bismuth (Bi), antimony (Sb) or arsenic (As). The P-type semiconductor substrate is doped with a P-type element, which may be any one of the III-group elements such as boron (B), aluminum (Al), gallium (Ga) or indium (In).

[0070] Preferably, in this embodiment, the silicon substrate 10 is a silicon substrate made of single crystal silicon. The ordered crystal structure helps to reduce the scattering and recombination probability of carriers during migration, so that the silicon substrate and the carriers generated by the first doping layer recombine less, thereby increasing the number and mobility of carriers.

[0071] In some embodiments, the silicon substrate 10 has a first surface 111 and a second surface 112 that are arranged opposite to each other. The first surface 111 may be the front surface, and the second surface 112 may be the back surface. The "front" and "back" in the front surface and the back surface are relative, that is, the "front" refers to the side facing the sunlight along the vertical direction, and the "back" refers to the side facing away from the sunlight along the vertical direction.

[0072] Specifically, in the embodiment of the present application, a first doping layer 20 is disposed on the first surface 111 of the silicon substrate 10, and a second doping layer 30 is disposed on the second surface 112 of the silicon substrate 10. The first doping layer 20 may be an N-type doping layer, and the second doping layer 30 may be a P-type doping layer. Of course, the first doping layer 20 may also be a P-type doping layer, and the second doping layer 30 may be an N-type doping layer, and the two have opposite polarities.

[0073] It should be noted that, in the present application, "one of the first doped layer and the second doped layer extends along the side of the silicon substrate and is in conductive contact with the other of the first doped layer and the second doped layer to form a contact area" means that there is no insulation between the two, and the two can be in direct conductive contact or indirect conductive contact through other passivation layers. For example, the two can be in indirect conductive contact through the first passivation layer 40 or the second passivation layer 80 mentioned below.

[0074] In some embodiments, the first doping layer 20 has a first extension portion 50 extending along the side surface 113 of the silicon substrate 10, and the first extension portion 50 is disposed on the side surface 113 of the silicon substrate 10. The second doping layer 30 has a second extension portion 60 extending along the side surface of the silicon substrate 10, and the second extension portion 60 is disposed on the side surface of the silicon substrate 10. The first extension portion 50 and the second extension portion 60 are in direct conductive contact on the side surface 113 of the silicon substrate 10.

[0075] In some embodiments, the first passivation layer 40 is disposed between the first doped layer 20 and the silicon substrate 10, the first doped layer 20 is indirectly conductively contacted with the second doped layer 30 through the first passivation layer 40, the second passivation layer 80 is disposed between the second doped layer 30 and the silicon substrate 10, and the second doped layer 30 is indirectly conductively contacted with the first doped layer 20 through the second passivation layer 80. The first passivation layer 40 and the second passivation layer 80 can prevent the recombination of photogenerated electrons and holes, reduce the energy loss in the photoelectric conversion process, and the passivation layer can form a good ohmic contact with the metal electrode, thereby improving the fill factor and short-circuit current of the battery, thereby further improving the photoelectric conversion efficiency.

[0076] The contact area between the first doped layer 20 and the second doped layer 30 is not limited in the present application, and can be the side surface 113 of the silicon substrate 10, the first surface 111 of the silicon substrate 10 and the second surface 112 of the silicon substrate 10 mentioned below, or any other position, or a combination of multiple contact areas, as long as the first doped layer 20 and the second doped layer 30 can be conductively contacted.

[0077] When the first doping layer 20 and the second doping layer 30 are in contact with each other at the side of the silicon substrate 10, the first doping layer 20 and the second doping layer 30 form a conductive contact at the side of the silicon substrate 10 in the following manner:

[0078] like Figure 1 As shown, the first doping layer 20 covers the first surface 111 of the silicon substrate 10, the first extension portion 50 of the first doping layer 20 extends along the side 113 of the silicon substrate 10, the second doping layer 30 covers the second surface 112 of the silicon substrate 10, the second extension portion 60 of the second doping layer 30 extends along the side 113 of the silicon substrate 10, the second extension portion 60 covers the outer side of the first extension portion 50, and the first extension portion 50 and the second extension portion 60 form direct conductive contact on the side 113 of the silicon substrate 10.

[0079] like Figure 2 As shown, the first doping layer 20 covers the first surface 111 of the silicon substrate 10, the first extension portion 50 of the first doping layer 20 extends along the side 113 of the silicon substrate 10, and the first passivation layer 40 is arranged between the first doping layer 20 and the silicon substrate 10. The second doping layer 30 covers the second surface 112 of the silicon substrate 10, the second extension portion 60 of the second doping layer 30 extends along the side 113 of the silicon substrate 10, and the second extension portion 60 covers the outer side of the first extension portion 50. The first extension portion 50 and the second extension portion 60 form a direct conductive contact on the side 113 of the silicon substrate 10.

[0080] like Figure 3 As shown, the first doping layer 20 covers the first surface 111 of the silicon substrate 10, the first extension portion 50 of the first doping layer 20 extends along the side 113 of the silicon substrate 10, the first passivation layer 40 is arranged between the first doping layer 20 and the silicon substrate 10, the second doping layer 30 covers the second surface 112 of the silicon substrate 10, the second extension portion 60 of the second doping layer 30 extends along the side 113 of the silicon substrate 10, the first passivation layer 40 is located between the first extension portion 50 and the second extension portion 60, the first extension portion 50 and the first passivation layer 40 cover the outside of the second extension portion 60, and the first extension portion 50 forms an indirect conductive contact on the side 113 of the silicon substrate 10 through the first passivation layer 40 and the second extension portion 60.

[0081] like Figure 4 As shown, the first doping layer 20 covers the first surface 111 of the silicon substrate 10, the first extension portion 50 of the first doping layer 20 extends along the side 113 of the silicon substrate 10, the second doping layer 30 covers the second surface 112 of the silicon substrate 10, the second extension portion 60 of the second doping layer 30 extends along the side 113 of the silicon substrate 10, a second passivation layer is arranged between the second doping layer and the silicon substrate, the second doping layer and the second passivation layer cover the outside of the first extension portion, the second passivation layer is located between the first extension portion and the second extension portion, and the second extension portion 60 forms an indirect conductive contact with the side 113 of the silicon substrate 10 through the second passivation layer 80 and the first extension portion 50.

[0082] like Figure 5 As shown, the first doping layer 20 covers the first surface 111 of the silicon substrate 10, the first extension portion 50 of the first doping layer 20 extends along the side 113 of the silicon substrate 10, the second doping layer 30 covers the second surface 112 of the silicon substrate 10, the second extension portion 60 of the second doping layer 30 extends along the side 113 of the silicon substrate 10, a first passivation layer is arranged between the first doping layer and the silicon substrate, a second passivation layer is arranged between the second doping layer and the silicon substrate, the second extension portion and the second passivation layer cover the outside of the first extension portion and the first passivation layer, and the second extension portion 60 forms an indirect conductive contact with the side 113 of the silicon substrate 10 through the second passivation layer 80 and the first extension portion 50.

[0083] like Figure 6 As shown, the first doping layer 20 covers the first surface 111 of the silicon substrate 10, the first extension portion 50 of the first doping layer 20 extends along the side 113 of the silicon substrate 10, the second doping layer 30 covers the second surface 112 of the silicon substrate 10, the second extension portion 60 of the second doping layer 30 extends along the side 113 of the silicon substrate 10, a first passivation layer is arranged between the first doping layer and the silicon substrate, a second passivation layer is arranged between the second doping layer and the silicon substrate, the first extension portion and the first passivation layer cover the outer sides of the second extension portion and the second passivation layer, and the first extension portion 50 forms an indirect conductive contact on the side 113 of the silicon substrate 10 through the first passivation layer 40 and the second extension portion 80.

[0084] like Figure 7As shown, the first doping layer 20 covers the first surface 111 of the silicon substrate 10, the first extension portion 50 of the first doping layer 20 extends along the side surface 113 of the silicon substrate 10, and the first extension portion partially covers the side surface of the silicon substrate. The second doping layer 30 covers the second surface 112 of the silicon substrate 10, the second extension portion 60 of the second doping layer 30 extends along the side surface 113 of the silicon substrate 10, and the second extension portion covers the outer side of the first extension portion. The first extension portion 50 and the second extension portion 60 form a direct conductive contact on the side surface 113 of the silicon substrate 10.

[0085] like Figure 8 As shown, the first doping layer 20 covers the first surface 111 of the silicon substrate 10, the first extension portion 50 of the first doping layer 20 extends along the side 113 of the silicon substrate 10, the second doping layer 30 covers the second surface 112 of the silicon substrate 10, the second extension portion 60 of the second doping layer 30 extends along the side 113 of the silicon substrate 10, the second extension portion partially covers the outside of the first extension portion, and the first extension portion 50 and the second extension portion 60 form direct conductive contact on the side 113 of the silicon substrate 10.

[0086] like Fig. 9 As shown, the first doping layer 20 covers the first surface 111 of the silicon substrate 10, the first extension portion 50 of the first doping layer 20 extends along the side surface 113 of the silicon substrate 10, the second doping layer 30 covers the second surface 112 of the silicon substrate 10, the second extension portion 60 of the second doping layer 30 extends along the side surface 113 of the silicon substrate 10, the second extension portion partially covers the side surface of the silicon substrate, the first extension portion covers the outer side of the second extension portion, and the first extension portion 50 and the second extension portion 60 form direct conductive contact on the side surface 113 of the silicon substrate 10.

[0087] A portion of the first doping layer 20 is disposed on the first surface 111 of the silicon substrate 10, and another portion of the first doping layer 20, the first extension portion 50, can be disposed on the side surface 113 of the silicon substrate 10. The first extension portion 50 can cover all the side surfaces of the silicon substrate 10, or the first extension portion 50 can cover part of the side surfaces of the silicon substrate 10. According to the actual situation, a portion of the second doping layer 30 is disposed on the second surface 112 of the silicon substrate 10, and another portion of the second doping layer 30, the second extension portion 60, can be disposed on the side surface 113 of the silicon substrate 10. The first extension portion 50 and the second extension portion 60 are in direct conductive contact on the side surface 113 of the silicon substrate 10, forming a bypass circuit of the solar cell, which can generate a composite leakage current of appropriate size and avoid the high heat risk of the hot spot effect. Avoid the safety hazard caused by the high heat accumulation of the hot spot effect.

[0088] When the first doped layer and the second doped layer are in contact at the first surface of the silicon substrate, the second doped layer 30 has a fourth extension portion 90 extending from the side surface 113 of the silicon substrate 10 to the first surface, the fourth extension portion 90 is disposed at the side surface 113 of the silicon substrate 10 and at least a portion of the first surface, and the fourth extension portion 90 and the first doped layer 20 are in direct conductive contact at the first surface 111. In some embodiments, as Fig.12 The first doping layer 20 and the second doping layer 30 are in direct conductive contact with the first surface 111 , and a first passivation layer is disposed between the first doping layer 20 and the silicon substrate 10 .

[0089] Specifically, the first doped layer and the second doped layer form a conductive contact region on the first surface of the silicon substrate as follows:

[0090] like Fig.10 As shown, the first doping layer 20 covers the first surface 111 of the silicon substrate 10, a portion of the second doping layer covers the second surface 112 of the silicon substrate, the fourth extension portion of the second doping layer 30 covers at least a portion of the first surface 111 of the silicon substrate, the fourth extension portion 90 covers the outside of the first doping layer 20, and the fourth extension portion 50 and the first doping layer 20 form a direct conductive contact on the first surface 111 of the silicon substrate 10.

[0091] like Fig.11 As shown, the first doping layer 20 covers the first surface 111 of the silicon substrate 10, a portion of the second doping layer covers the second surface 112 of the silicon substrate, the fourth extension portion of the second doping layer 30 covers at least a portion of the first surface 111 of the silicon substrate, a second passivation layer is arranged between the second doping layer and the silicon substrate, the fourth extension portion and the second passivation layer cover the outside of the first doping layer, and the fourth extension portion 50 forms an indirect conductive contact with the first surface 111 of the silicon substrate 10 through the second passivation layer and the first doping layer 20.

[0092] like Fig.12 As shown, the first doping layer 20 covers the first surface 111 of the silicon substrate 10, a portion of the second doping layer covers the second surface 112 of the silicon substrate, the fourth extension portion of the second doping layer 30 covers at least a portion of the first surface 111 of the silicon substrate, a first passivation layer is arranged between the first doping layer and the silicon substrate, the fourth extension portion covers the outer side of the first doping layer, and the fourth extension portion 50 and the first doping layer 20 form a direct conductive contact on the first surface 111 of the silicon substrate 10.

[0093] like Fig.13As shown, the first doping layer 20 covers the first surface 111 of the silicon substrate 10, a portion of the second doping layer covers the second surface 112 of the silicon substrate, the fourth extension portion of the second doping layer 30 covers at least a portion of the first surface 111 of the silicon substrate, a first passivation layer is arranged between the first doping layer and the silicon substrate, the first doping layer and the first passivation layer cover the outside of the fourth extension portion, and the first doping layer forms an indirect conductive contact with the first surface 111 of the silicon substrate 10 through the first passivation layer and the fourth extension portion.

[0094] like Fig.14 As shown, the first doping layer 20 covers the first surface 111 of the silicon substrate 10, a portion of the second doping layer covers the second surface 112 of the silicon substrate, the fourth extension portion of the second doping layer 30 covers at least a portion of the first surface 111 of the silicon substrate, a second passivation layer is arranged between the second doping layer 30 and the silicon substrate, the first doping layer covers the outer side of the fourth extension portion, and the first doping layer and the fourth extension portion form direct conductive contact on the first surface 111 of the silicon substrate 10.

[0095] like Fig.15 As shown, the first doping layer 20 covers the first surface 111 of the silicon substrate 10, a portion of the second doping layer covers the second surface 112 of the silicon substrate, the fourth extension portion of the second doping layer 30 covers at least a portion of the first surface 111 of the silicon substrate, a first passivation layer is arranged between the first doping layer and the silicon substrate, a second passivation layer is arranged between the second doping layer 30 and the silicon substrate, the first doping layer and the first passivation layer cover the outside of the fourth extension portion, and the first doping layer forms an indirect conductive contact with the first surface 111 of the silicon substrate 10 through the first passivation layer and the fourth extension portion.

[0096] like Fig.16 As shown, the first doping layer 20 covers the first surface 111 of the silicon substrate 10, a portion of the second doping layer covers the second surface 112 of the silicon substrate, the fourth extension portion of the second doping layer 30 covers at least a portion of the first surface 111 of the silicon substrate, a first passivation layer is arranged between the first doping layer and the silicon substrate, a second passivation layer is arranged between the second doping layer 30 and the silicon substrate, the fourth extension portion and the second passivation layer cover the outside of the first doping layer, and the second doping layer 30 forms an indirect conductive contact with the first surface 111 of the silicon substrate 10 through the second passivation layer and the first doping layer 20.

[0097] A portion of the second doping layer 30 is disposed on the second surface 112 of the silicon substrate 10, and another portion of the second doping layer 30 extends along the side surface 113 of the silicon substrate 10 until it covers a partial area of ​​the first surface 111 of the silicon substrate 10. In this way, the first doping layer 20 and the second doping layer 30 are in contact with the first surface 111, forming a bypass circuit and generating a composite leakage current of appropriate size, thereby avoiding the safety hazard caused by high heat accumulation due to the hot spot effect.

[0098] When the first doped layer and the second doped layer contact each other at the second surface of the silicon substrate, the first doped layer 20 has a third extension portion 70 extending along the side surface 113 of the silicon substrate 10 to the second surface 112, and the third extension portion 70 covers at least a portion of the side surface 113 and the second surface 112 of the silicon substrate 10, and the third extension portion 70 contacts the second doped layer 30 at the second surface 112.

[0099] Specifically, the first doped layer and the second doped layer form a conductive contact region on the second surface of the silicon substrate in the following manner:

[0100] like Fig.17 As shown, a portion of the first doped layer 20 covers the first surface 111 of the silicon substrate 10, and another portion of the first doped layer, the third extension portion 70, extends along the side surface 113 of the silicon substrate 10 to the second surface 112, and the third extension portion 70 covers at least a portion of the side surface 113 and the second surface 112 of the silicon substrate 10, and the second doped layer covers the outside of the third extension portion, and the third extension portion 70 forms a direct conductive contact with the second doped layer 30 on the second surface 112.

[0101] like Fig.18 As shown, a portion of the first doped layer 20 covers the first surface 111 of the silicon substrate 10, and another portion of the first doped layer, the third extension portion 70, extends along the side surface 113 of the silicon substrate 10 to the second surface 112, and the third extension portion 70 covers at least a portion of the side surface 113 and the second surface 112 of the silicon substrate 10. A second passivation layer is arranged between the second doped layer and the silicon substrate, and the second doped layer and the second passivation layer cover the outside of the third extension portion. The second doped layer 30 forms an indirect conductive contact through the second passivation layer and the third extension portion 70.

[0102] like Fig.19As shown, a portion of the first doped layer 20 covers the first surface 111 of the silicon substrate 10, and another portion of the first doped layer, the third extension portion 70, extends along the side surface 113 of the silicon substrate 10 to the second surface 112, and the third extension portion 70 covers at least a portion of the side surface 113 and the second surface 112 of the silicon substrate 10. A first passivation layer is arranged between the first doped layer and the silicon substrate, and the second doped layer covers the outer side of the third extension portion, and the second doped layer and the third extension portion 70 form a direct conductive contact on the second surface 112.

[0103] like Fig. 20 As shown, a portion of the first doped layer 20 covers the first surface 111 of the silicon substrate 10, and another portion of the first doped layer, the third extension portion 70, extends along the side surface 113 of the silicon substrate 10 to the second surface 112, and the third extension portion 70 covers at least a portion of the side surface 113 and the second surface 112 of the silicon substrate 10. A first passivation layer is arranged between the first doped layer and the silicon substrate, and a second passivation layer is arranged between the second doped layer and the silicon substrate. The second doped layer and the second passivation layer cover the outside of the third extension portion, and the second doped layer forms an indirect conductive contact with the third extension portion through the second passivation layer.

[0104] like Fig.21 As shown, a portion of the first doped layer 20 covers the first surface 111 of the silicon substrate 10, and another portion of the first doped layer, the third extension portion 70, extends along the side surface 113 of the silicon substrate 10 to the second surface 112, and the third extension portion 70 covers at least a portion of the side surface 113 and the second surface 112 of the silicon substrate 10, and the third extension portion covers the outside of the second doped layer, and the third extension portion 70 forms a direct conductive contact with the second doped layer 30 on the second surface 112.

[0105] like Fig. 22 As shown, a portion of the first doped layer 20 covers the first surface 111 of the silicon substrate 10, and another portion of the first doped layer, the third extension portion 70, extends along the side surface 113 of the silicon substrate 10 to the second surface 112, and the third extension portion 70 covers the side surface 113 of the silicon substrate 10 and at least a portion of the second surface 112, a first passivation layer is arranged between the first doped layer and the silicon substrate, the third extension portion and the first passivation layer cover the outer side of the second doped layer, and the third extension portion 70 forms an indirect conductive contact on the second surface 112 through the first passivation layer and the second doped layer 30.

[0106] like Fig.23As shown, a portion of the first doped layer 20 covers the first surface 111 of the silicon substrate 10, and another portion of the first doped layer, the third extension portion 70, extends along the side surface 113 of the silicon substrate 10 to the second surface 112, and the third extension portion 70 covers at least a portion of the side surface 113 and the second surface 112 of the silicon substrate 10. A second passivation layer is arranged between the second doped layer and the silicon substrate, and the third extension portion covers the outer side of the second doped layer, and the third extension portion 70 forms a direct conductive contact with the second doped layer 30 on the second surface 112.

[0107] like Fig.24 As shown, a portion of the first doping layer 20 covers the first surface 111 of the silicon substrate 10, and another portion of the first doping layer, the third extension portion 70, extends along the side surface 113 of the silicon substrate 10 to the second surface 112, and the third extension portion 70 covers the side surface 113 of the silicon substrate 10 and at least a portion of the second surface 112, a first passivation layer is arranged between the first doping layer and the silicon substrate, a second passivation layer is arranged between the second doping layer and the silicon substrate, the third extension portion and the first passivation layer cover the outside of the second doping layer, and the third extension portion 70 forms an indirect conductive contact on the second surface 112 through the first passivation layer and the second doping layer 30.

[0108] Further, when the first doping layer and the second doping layer form a conductive contact on the second surface of the silicon substrate, the second doping layer 30 is deposited on the edge of the silicon substrate 10 to form a protruding structure. Figure 17 to Figure 24 The first doped layer and the second doped layer are in direct conductive contact in the same manner as described above, and will not be described in detail here. Fig.25 and Fig.29 The first doped layer is in indirect conductive contact with the second doped layer through the passivation layer. Fig.26 , Fig. 27 , Fig.28 , Fig.30 , Fig.31 and Fig.32 .

[0109] A portion of the first doped layer 20 is disposed on the first surface 111 of the silicon substrate 10, and another portion of the first doped layer 20, the third extension portion 70, extends along the side of the silicon substrate 10 until it covers a partial area of ​​the second surface 112 of the silicon substrate. In this way, the first doped layer 20 and the second doped layer 30 are in contact with each other on the second surface, forming a bypass circuit and generating a composite leakage current of appropriate size, thereby avoiding the safety hazard caused by high heat accumulation due to the hot spot effect.

[0110] Such a structural design increases the carrier transport of the solar cell, because the current can flow not only through the first doped layer 20, the silicon substrate 10 and the second doped layer 30, but also through the contact area between the first doped layer 20 and the second doped layer 30. Secondly, the contact between the first doped layer 20 and the second doped layer 30 provides a shorter current path, reducing resistance and power consumption.

[0111] The first passivation layer 40 and the second passivation layer 80 respectively include at least one of an amorphous silicon layer, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon carbonitride oxycarbon layer, a titanium oxide layer, a hafnium oxide layer, and an aluminum oxide layer, which is not limited in the present application.

[0112] The thickness of the first passivation layer 40 and the second passivation layer 80 are 0.5nm to 20nm respectively. Thus, setting the thickness of the first passivation layer 40 and the second passivation layer 80 within the reasonable range of 0.5nm to 20nm can ensure the passivation effect of the composite surface while making the solar cell have a better carrier collection effect, and can avoid the first passivation layer and the second passivation layer 80 being too thin to cause poor passivation effect, and can also avoid the first passivation layer and the second passivation layer 80 being too thick to cause low tunneling efficiency.

[0113] Specifically, in such an embodiment, the thickness of the first passivation layer 40 and the second passivation layer 80 may be, for example, 0.5nm, 1nm, 1.5nm, 2nm, 2.5nm, 3nm, 3.5nm, 4nm, 4.5nm, 5nm, 5.5nm, 6nm, 7nm, 8nm, 9nm, 10nm, 15nm, 20nm or any value between 0.5nm and 20nm, and is not limited here.

[0114] Furthermore, the thickness of the first passivation layer 40 and the second passivation layer 80 are 0.5 nm to 10 nm respectively. Thus, setting the thickness of the first passivation layer 40 and the second passivation layer 80 within a reasonable range of 0.5 nm to 10 nm can ensure the passivation effect of the composite surface while making the solar cell have a better carrier collection effect.

[0115] Specifically, in such an embodiment, the thickness of the first passivation layer 40 and the second passivation layer 80 may be, for example, 0.5nm, 1nm, 1.5nm, 2nm, 2.5nm, 3nm, 3.5nm, 4nm, 4.5nm, 5nm, 5.5nm, 6nm, 7nm, 8nm, 9nm, 10nm or any value between 0.5nm and 10nm, and is not limited here.

[0116] The first doped layer 20 and the second doped layer 30 are in direct conductive contact to form a contact region (as shown in the dotted box in the figure), and the ratio of the total area of ​​the contact region to the area of ​​the first surface or the second surface is in the range of 1E-8 to 0.03. The first doped layer and the second doped layer are in indirect conductive contact through the first passivation layer to form a contact region (as shown in the dotted box in the figure), and the ratio of the total area of ​​the contact region to the area of ​​the first surface or the second surface is in the range of 1E-8 to 0.03. The first doped layer and the second doped layer are in indirect conductive contact through the second passivation layer to form a contact region, and the ratio of the total area of ​​the contact region to the area of ​​the first surface or the second surface is in the range of 1E-8 to 0.03.

[0117] Thus, setting the area ratio of the above-mentioned contact area within this reasonable range can avoid the total area ratio of the conductive contact area being too small, resulting in too high reverse bias, and can also avoid the area ratio of the conductive contact area being too large, which seriously affects the efficiency of the solar cell 100, that is, the efficiency of the solar cell 100 can be guaranteed while ensuring the reduction of the reverse conduction threshold. Reasonable contact area distribution can ensure that the current is evenly distributed inside the solar cell, avoid local overheating and current concentration, and further improve the performance and stability of the battery.

[0118] Specifically, in such an embodiment, the ratio of the area of ​​the contact region to the area of ​​the first surface or the second surface may be 1E-8, 0.01, 0.02, 0.03 or any other value between 1E-8 and 0.03, which is not specifically limited herein.

[0119] In some embodiments, the thickness of the first doping layer 20 may be 5 nm to 600 nm. In this way, it is possible to avoid the possibility that an excessively thin doping layer may lead to insufficient conductivity or reduced interface quality while ensuring the effect.

[0120] Specifically, the thickness of the first doping layer 20 may be 5 nm, 10 nm, 50 nm, 80 nm, 100 nm, 150 nm, 300 nm, 600 nm, or any value between 5 nm and 600 nm, which is not specifically limited herein.

[0121] Similarly, in such an embodiment, the thickness of the second doping layer 30 may also be 5 nm to 600 nm, which is not specifically limited herein.

[0122] To summarize, a first doped layer is disposed on the first surface of the silicon substrate, and a second doped layer is disposed on the second surface of the silicon substrate. The first doped layer, the silicon substrate, and the second doped layer constitute a pn junction structure, thereby realizing the separation and collection of photogenerated carriers of the solar cell. In particular, one of the first doped layer and the second doped layer bypasses the side of the silicon substrate and contacts the second doped layer and the other of the first doped layer, thereby realizing a bypass connection between the first doped layer and the second doped layer. When the solar cell generates electricity normally, the contact area between the first doped layer and the second doped layer also performs photoelectric conversion to generate electricity, thereby also improving the overall power generation efficiency of the solar cell. When the solar cell is blocked to produce a hot spot effect, a composite leakage current of appropriate size can be generated between the first doped layer 20 and the second doped layer 30, thereby avoiding the high thermal risk of the hot spot effect.

[0123] In some embodiments, the first doped layer and the second doped layer form a conductive channel in the contact region, and the first doped layer and the second doped layer release current through the conductive channel, wherein under a reverse bias voltage of -12V or less than -12V, the current density of the solar cell is in the range of 0.1 to 5 mA / cm 2 The reverse bias voltage of -12V or less than -12V is the standard test voltage. Within this current density range, the internal reaction of the solar cell is complete, and it has a higher energy density and power density.

[0124] Furthermore, the first doped layer and the second doped layer form a conductive channel in the contact area, and the first doped layer and the second doped layer release current through the conductive channel, wherein under a reverse bias voltage of -12V or less than -12V, the current density of the solar cell is in the range of greater than 1.5mA / cm 2 Less than or equal to 5mA / cm 2 The reverse bias voltage of -12V or less than -12V is the standard test voltage. Within this current density range, the internal reaction of the solar cell is complete, and it has a higher energy density and power density.

[0125] Specifically, the current density is defined as the current measured at a reverse bias voltage of -12 V or less than -12 V divided by the projected area of ​​the first surface or the second surface of the solar cell.

[0126] The solar cell includes a first electrode and a second electrode, wherein the first electrode is in electrical contact with the first doped layer, and the second electrode is in electrical contact with the second doped layer. In such an embodiment, the first electrode is in ohmic contact with the first doped layer 20 located on the first surface 111, and the second electrode is in ohmic contact with the second doped layer 30 located on the second surface 112 to achieve carrier extraction from the first doped layer and the second doped layer.

[0127] The contact region is located on at least one side of the first surface of the solar cell, the second surface of the solar cell, or the side of the solar cell, or is located on a partial region of at least one side of the first surface, the second surface of the solar cell, or the side of the solar cell.

[0128] In some embodiments, the contact area between the first doping layer 20 and the second doping layer 30 can be the entire edge of the solar cell 100 or a portion of the edge of the solar cell 100 , or a portion of the edge of the solar cell, or a combination of the above, which is not limited in the present application.

[0129] It is understandable that those skilled in the art can, under the guidance of the above embodiments, combine various implementation methods in the above embodiments to obtain technical solutions of multiple implementation methods.

[0130] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A solar cell, characterized in that: include: A silicon substrate having a first surface and a second surface disposed opposite to each other; a first doped layer, the first doped layer being disposed on the first surface; A second doping layer, wherein the second doping layer is disposed on the second surface, and the second doping layer has a polarity opposite to that of the first doping layer; Wherein, at least one of the first doping layer and the second doping layer extends along the side surface of the silicon substrate and is in conductive contact with the other of the first doping layer and the second doping layer to form a contact region.

2. The solar cell according to claim 1, characterized in that The first doped layer has a first extension portion extending along the side of the silicon substrate, and the first extension portion is arranged on the side of the silicon substrate. The second doped layer has a second extension portion extending along the side of the silicon substrate, and the second extension portion is arranged on the side of the silicon substrate. The first extension portion and the second extension portion are in direct conductive contact on the side of the silicon substrate.

3. The solar cell according to claim 1, characterized in that The first doped layer has a third extension portion extending along the side of the silicon substrate to the second surface. The third extension portion is arranged on the side of the silicon substrate and at least a portion of the second surface. The third extension portion is in direct conductive contact with the second doped layer on the second surface.

4. The solar cell according to claim 1, characterized in that The second doped layer has a fourth extension portion extending along the side of the silicon substrate to the first surface, the fourth extension portion is arranged on the side of the silicon substrate and at least a portion of the first surface, and the fourth extension portion and the first doped layer are in direct conductive contact on the first surface.

5. The solar cell according to claim 2, 3 or 4, characterized in that: The solar cell also includes: a first passivation layer, wherein the first passivation layer is arranged between the first doped layer and the silicon substrate, and the first doped layer is indirectly conductively contacted with the second doped layer through the first passivation layer; and / or a second passivation layer, wherein the second passivation layer is arranged between the second doped layer and the silicon substrate, and the second doped layer is indirectly conductively contacted with the first doped layer through the second passivation layer.

6. The solar cell according to claim 5, characterized in that One of the first passivation layer and the second passivation layer includes at least one of an amorphous silicon layer, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon carbonitride oxycarbon layer, a titanium oxide layer, a hafnium oxide layer, and an aluminum oxide layer.

7. The solar cell according to claim 5, characterized in that Each of the first passivation layer and the second passivation layer has a thickness of 0.5 nm to 20 nm.

8. The solar cell according to claim 7, characterized in that Each of the first passivation layer and the second passivation layer has a thickness of 0.5 nm to 10 nm.

9. The solar cell according to claim 1, characterized in that: The first doped layer and the second doped layer are in direct conductive contact to form the contact region, and a ratio of a total area of ​​the contact region to an area of ​​the first surface or the second surface is in a range of 1E-8 to 0.

03.

10. The solar cell according to claim 5, characterized in that: The first doped layer and the second doped layer are indirectly conductively contacted via the first passivation layer and / or the second passivation layer to form the contact region, and a ratio of a total area of ​​the contact region to an area of ​​the first surface or the second surface is in a range of 1E-8 to 0.

03.

11. The solar cell according to claim 1, characterized in that: The first doped layer and the second doped layer form a conductive channel in the contact area, and the first doped layer and the second doped layer release current through the conductive channel, wherein under a reverse bias voltage of -12V or less than -12V, the current density of the solar cell is greater than or equal to 0.1mA / cm 2 , and less than or equal to 5mA / cm 2 .

12. The solar cell according to claim 11, characterized in that The first doped layer and the second doped layer form a conductive channel in the contact area, and the first doped layer and the second doped layer release current through the conductive channel, wherein under a reverse bias voltage of -12V or less than -12V, the current density of the solar cell is in the range of greater than 1.5mA / cm 2 , and less than or equal to 5mA / cm 2 .

13. The solar cell according to claim 1, characterized in that: The contact region is located on at least one side of the first surface of the solar cell, the second surface of the solar cell, or the side of the solar cell, or is located on a partial region of at least one side of the first surface, the second surface of the solar cell, or the side of the solar cell.

14. A photovoltaic module, characterized in that: A solar cell comprising the solar cell according to any one of claims 1 to 13.

15. A photovoltaic system, characterized in that: Comprising the photovoltaic module described in claim 14.

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