N-type battery piece and battery assembly

Abstract

The utility model belongs to the technical field of batteries, and discloses an N-type battery piece and a battery assembly. The N-type battery piece comprises an N-type silicon substrate, and a tunneling layer, a doped crystalline silicon layer and a back antireflection functional layer which are sequentially arranged on the back surface of the N-type silicon substrate; the doped crystalline silicon layer at least comprises a first doped crystalline silicon layer, a second doped crystalline silicon layer and a third doped crystalline silicon layer which are sequentially arranged in the direction far away from the back surface of the N-type silicon substrate; the doping concentration of the first doped crystalline silicon layer is larger than that of the N-type silicon substrate. The doping concentration of the first doped crystalline silicon layer and the doping concentration of the third doped crystalline silicon layer are both larger than or smaller than the doping concentration of the second doped crystalline silicon layer. The N-type battery piece has the technical advantages of parasitic absorption reduction caused by low doping concentration, recombination reduction, low resistivity caused by high doping concentration and good passivation effect, and the overall performance of the N-type battery piece is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of batteries, in particular to an N-type battery chip and a battery module. Background Art

[0002] At present, the existing TOPCon batteries usually adopt a polysilicon doping layer with a thickness of more than 100 nm. On the back of the battery, silver paste is usually used to burn through the dielectric film to form an ohmic contact with the doped polysilicon. During the paste sintering process, metal silver grains may penetrate the doped polysilicon film layer, destroying the passivation effect of the interface oxide layer. In order to reduce the recombination current density in the metal contact area, the thickness of the doped polysilicon cannot be too thin, usually in the range of 100 nm - 150 nm. In order to ensure good field passivation effect and low ohmic contact, the doped polysilicon needs to have a sufficiently high doping concentration, usually greater than 1×10 20 cm -3 . However, the polysilicon film layer in the above passivation structure has a large film thickness and high doping concentration. Due to the free carrier absorption (FCA) of the doped polysilicon for long-wavelength light, it will cause the loss of the short-circuit current of the TOPCon battery. At the same time, the parasitic absorption of the doped polysilicon for the back-incident light will cause the reduction of the bifaciality of the battery. At present, mainly on the premise of ensuring that the metal electrode paste does not burn through the tunneling layer and the metal electrode forms a good ohmic contact with the polysilicon film layer, the thickness and doping concentration of the polysilicon film layer are reduced as much as possible to reduce the current loss; or only the above passivation structure is used in the metal electrode area of the battery, making it difficult to balance the light absorption and passivation effect of the battery. Summary of the Utility Model

[0003] The first object of the utility model is to provide an N-type battery chip, which takes into account the technical advantages of reduced parasitic absorption caused by low doping concentration, reduced recombination, low resistivity caused by high doping concentration, and good passivation effect, and is beneficial to improving the overall performance of the N-type battery chip.

[0004] The second object of the utility model is to provide a battery module, which has a lower resistivity and better overall performance.

[0005] To achieve the above object, the utility model adopts the following technical solutions:

[0006] The utility model discloses an N-type battery cell, which comprises an N-type silicon substrate, and a tunneling layer, a doped polycrystalline silicon layer and a back surface antireflection functional layer that are sequentially arranged on the back surface of the N-type silicon substrate. The doped polycrystalline silicon layer at least comprises a first doped polycrystalline silicon layer, a second doped polycrystalline silicon layer and a third doped polycrystalline silicon layer that are sequentially arranged in the back surface direction away from the N-type silicon substrate. The doping concentration of the first doped polycrystalline silicon layer is greater than that of the N-type silicon substrate. Wherein: the doping concentrations of the first doped polycrystalline silicon layer and the third doped polycrystalline silicon layer are both greater than that of the second doped polycrystalline silicon layer; or: the doping concentrations of the first doped polycrystalline silicon layer and the third doped polycrystalline silicon layer are both less than that of the second doped polycrystalline silicon layer.

[0007] In some embodiments, the first doped polycrystalline silicon layer, the second doped polycrystalline silicon layer and the third doped polycrystalline silicon layer are all microcrystalline silicon layers; or: the first doped polycrystalline silicon layer, the second doped polycrystalline silicon layer and the third doped polycrystalline silicon layer are all nanocrystalline silicon layers.

[0008] In some embodiments, the back surface antireflection functional layer comprises a silicon nitride layer or a TCO layer; and / or: the tunneling layer comprises at least one of a silicon oxide layer sheet, a silicon carbide layer sheet, a silicon carbon oxide layer sheet, a silicon nitride layer sheet and an aluminum oxide layer sheet.

[0009] In some embodiments, the N-type battery cell further comprises at least one polycrystalline silicon layer disposed between the tunneling layer and the doped polycrystalline silicon layer.

[0010] In some specific embodiments, the N-type battery cell further comprises a silicon oxide layer, and the silicon oxide layer is disposed between the doped polycrystalline silicon layer and the polycrystalline silicon layer, between two adjacent polycrystalline silicon layers or between two adjacent doped polycrystalline silicon layers.

[0011] In some embodiments, the doping concentrations of the first doped polycrystalline silicon layer and the third doped polycrystalline silicon layer are both greater than that of the second doped polycrystalline silicon layer.

[0012] In some embodiments, the doping concentrations of the first doped polycrystalline silicon layer and the third doped polycrystalline silicon layer are both less than that of the second doped polycrystalline silicon layer.

[0013] In some embodiments, the thicknesses of the first doped polycrystalline silicon layer, the second doped polycrystalline silicon layer and the third doped polycrystalline silicon layer are all 10 nm to 60 nm.

[0014] In some embodiments, the thickness of the tunneling layer is 1 nm to 2 nm.

[0015] The utility model also discloses a battery module, which comprises any one of the aforementioned N-type battery cells.

[0016] Advantages of the present utility model: Since the N-type cell disclosed in the present utility model forms a doped crystalline silicon layer on the back, the doped crystalline silicon layer at least includes a first doped crystalline silicon layer, a second doped crystalline silicon layer, and a third doped crystalline silicon layer with different concentrations. By using multiple doped crystalline silicon layers with different doping concentrations, the structural orderliness of the doped crystalline silicon layer results in a relatively high carrier mobility, which is also beneficial for the electrode to collect photo-generated electrons and hole pairs. Since the doping concentrations of the first doped crystalline silicon layer and the third doped crystalline silicon layer are both greater than or both less than the doping concentration of the second doped crystalline silicon layer. In this way, during the actual working process, the doping concentration of the first doped crystalline silicon layer will be higher than the doping concentration of the N-type silicon substrate by a certain number, making the Fermi level closer to the conduction band, which can ensure the potential barrier. Among the second doped crystalline silicon layer and the third doped crystalline silicon layer, the one with a higher doping concentration is beneficial for reducing the resistivity, and the one with a lower doping concentration is beneficial for effectively reducing parasitic absorption and recombination, thereby facilitating the N-type silicon substrate to absorb light.

[0017] Additional aspects and advantages of the present utility model will be given in part in the following description, become apparent in part from the following description, or be understood through the practice of the present utility model. Brief Description of the Drawings

[0018] Figure 1 is a schematic diagram of the back structure of the N-type cell of the present utility model;

[0019] Figure 2 is a schematic diagram of the complete structure of the N-type cell of the first structure of the present utility model;

[0020] Figure 3 is a schematic diagram of the complete structure of the N-type cell of the second structure of the present utility model;

[0021] Figure 4 is a schematic diagram of the complete structure of the N-type cell of the third structure of the present utility model.

[0022] Reference Signs:

[0023] 1. N-type silicon substrate; 2. Tunneling layer; 31. First doped crystalline silicon layer; 32. Second doped crystalline silicon layer; 33. Third doped crystalline silicon layer; 4. Back antireflection functional layer; 5. Polysilicon layer; 6. Silicon oxide layer; 7. Boron diffusion layer; 8. Passivation layer; 9. Front antireflection functional layer; 10. Electrode. Detailed Embodiments

[0024] The following further describes the present utility model in detail with reference to the drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the present utility model, rather than limiting the present utility model. Additionally, it should be noted that for the sake of description, only parts related to the present utility model are shown in the drawings, rather than all the structures.

[0025] In the description of the present utility model, unless otherwise clearly defined and limited, the terms "connected", "connected to", and "fixed" shall be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral body; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific circumstances.

[0026] In the present utility model, unless otherwise clearly defined and limited, the first feature being "above" or "below" the second feature may include the direct contact between the first and second features, or may include the situation where the first and second features are not in direct contact but in contact through other features therebetween. Moreover, the first feature being "above", "over", and "on" the second feature includes that the first feature is directly above and obliquely above the second feature, or merely indicates that the horizontal height of the first feature is higher than that of the second feature. The first feature being "below", "beneath", and "under" the second feature includes that the first feature is directly below and obliquely below the second feature, or merely indicates that the horizontal height of the first feature is lower than that of the second feature.

[0027] In the description of this embodiment, the orientation or positional relationships such as "above", "below", "right", etc. are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of description and simplifying the operation, rather than indicating or implying that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be understood as a limitation to the present utility model. In addition, the terms "first" and "second" are only used for distinction in description and have no special meaning.

[0028] The present utility model discloses an N-type battery cell. Refer to Figure 1 As shown, the N-type battery cell includes an N-type silicon substrate 1, and a tunneling layer 2, a doped crystalline silicon layer, and a back surface antireflection functional layer 4 that are sequentially arranged on the back surface of the N-type silicon substrate 1. The doped crystalline silicon layer at least includes a first doped crystalline silicon layer 31, a second doped crystalline silicon layer 32, and a third doped crystalline silicon layer 33 that are sequentially arranged in the direction away from the back surface of the N-type silicon substrate 1.

[0029] For the N-type battery cell of the present utility model, in some embodiments, the doping concentrations of the first doped crystalline silicon layer 31 and the third doped crystalline silicon layer 33 are both greater than the doping concentration of the second doped crystalline silicon layer 32. In other embodiments, the doping concentrations of the first doped crystalline silicon layer 31 and the third doped crystalline silicon layer 33 are both less than the doping concentration of the second doped crystalline silicon layer 32.

[0030] It can be understood that since the N-type cell of the present utility model forms a doped crystalline silicon layer on the back, the doped crystalline silicon layer at least includes a first doped crystalline silicon layer 31, a second doped crystalline silicon layer 32, and a third doped crystalline silicon layer 33. By using multiple doped crystalline silicon layers with different doping concentrations, the structural orderliness of the doped crystalline silicon layer results in a relatively high carrier mobility, which is also conducive to the collection of photo-generated electrons and hole pairs by the electrode 10. Since the doping concentrations of the first doped crystalline silicon layer 31 and the third doped crystalline silicon layer 33 are both greater than or both less than the doping concentration of the second doped crystalline silicon layer 32. In this way, during the actual working process, the doping concentration of the first doped crystalline silicon layer 31 will be higher than the doping concentration of the N-type silicon substrate by a certain number, making the Fermi level closer to the conduction band, which can ensure the potential barrier. Among the second doped crystalline silicon layer 32 and the third doped crystalline silicon layer 33, the one with a higher doping concentration is conducive to reducing the resistivity and improving the passivation effect, while the one with a lower doping concentration is conducive to effectively reducing parasitic absorption and recombination, thus being beneficial for the N-type silicon substrate 1 to absorb light.

[0031] It should be added that in the embodiments of the present utility model, the doped crystalline silicon layer can be one layer or multiple layers, and can be specifically selected according to actual needs.

[0032] In some embodiments, the first doped crystalline silicon layer 31, the second doped crystalline silicon layer 32, and the third doped crystalline silicon layer 33 are all microcrystalline silicon layers. It can be understood that the grains of the microcrystalline silicon layer are smaller, which is conducive to improving the hydrogen passivation effect of the N-type cell.

[0033] In some embodiments, the first doped crystalline silicon layer 31, the second doped crystalline silicon layer 32, and the third doped crystalline silicon layer 33 are all nanocrystalline silicon layers. It can be understood that compared with the microcrystalline silicon layer, the grains of the nanocrystalline silicon layer are smaller, which is more conducive to improving the hydrogen passivation effect of the crystalline silicon.

[0034] In some embodiments, the back antireflection functional layer 4 is a silicon nitride layer.

[0035] In some alternative embodiments, the back antireflection functional layer 4 is a TCO layer. It can be understood that by using the TCO layer as the back antireflection functional layer 4, based on the conductive characteristics of the TCO layer, a relatively low-temperature silver paste sintering technology can be realized at the screen end of the printing process, thereby avoiding the contact between the electrode 10 grid lines and the crystalline silicon, effectively reducing the contact resistance; and the relatively low-temperature sintering is conducive to suppressing the diffusion and escape of hydrogen and improving the hydrogen passivation of the crystalline silicon.

[0036] In some embodiments, the tunneling layer 2 includes a silicon oxide layer sheet.

[0037] In some alternative embodiments, the tunneling layer 2 includes at least one of a silicon carbide layer, a silicon oxycarbide layer, a silicon nitride layer, and an aluminum oxide layer. It can be understood that introducing carbon elements can make the thin film structure more dense and effectively inhibit film bursting; and during annealing, the introduction of carbon elements can effectively block the excessive diffusion of phosphorus into the silicon substrate.

[0038] In some embodiments, the N-type cell further includes at least one polysilicon layer 5 disposed between the tunneling layer 2 and the doped crystalline silicon layer. It can be understood that the polysilicon structure has a higher crystallization rate and smaller parasitic absorption. Adding the polysilicon layer 5 between the tunneling layer 2 and the doped crystalline silicon layer can be more conducive to reducing parasitic absorption, so that the N-type silicon substrate 1 receives more light, which is beneficial to improving the performance of the N-type cell.

[0039] Furthermore, the N-type cell further includes a silicon oxide layer 6, and the silicon oxide layer 6 is disposed between the doped crystalline silicon layer and the polysilicon layer 5, between adjacent two polysilicon layers 5, or between adjacent two doped crystalline silicon layers. Adding the silicon oxide layer 6 can inhibit the excessive diffusion of phosphorus during annealing, which is beneficial to improving the performance of the N-type cell.

[0040] It should be noted here that in the present utility model, when the polysilicon layer 5 is one layer, the silicon oxide layer 6 is also one layer, and the silicon oxide layer 6 is disposed between the doped crystalline silicon layer and the polysilicon layer 5. When the polysilicon layer 5 is two layers or more, the silicon oxide layer 6 is also two layers or more, and the silicon oxide layer 6 is disposed between the doped crystalline silicon layer and the polysilicon layer 5 and between adjacent two polysilicon layers 5. In certain embodiments, the doped crystalline silicon layer can also be multiple layers, and at this time the silicon oxide layer 6 is disposed between adjacent two doped crystalline silicon layers. The number of the silicon oxide layer 6, the number of the polysilicon layer 5, and the number of the doped crystalline silicon layers can be selected according to the actual design requirements of the N-type cell.

[0041] In some embodiments, the doping concentrations of the first doped crystalline silicon layer 31 and the third doped crystalline silicon layer 33 are both greater than the doping concentration of the second doped crystalline silicon layer 32, where: the doping concentration of the first doped crystalline silicon layer 31 is 1×20 20 cm -3 ~3×20 20 cm -3 ; the doping concentration of the second doped crystalline silicon layer 32 is 5×20 19 cm -3 ~1×20 20 cm -3 ; the doping concentration of the third doped crystalline silicon layer 33 is 5×20 20 cm -3 ~1×20 21 cm -3It can be understood that the doping concentration of the first doped crystalline silicon layer 31 is relatively high. The higher the doping concentration, the closer the Fermi level is to the conduction band, which can ensure the potential barrier. The doping concentration of the second doped crystalline silicon layer 32 is relatively low, which can effectively reduce parasitic absorption and recombination. The doping concentration of the third doped crystalline silicon layer 33 is high, which is beneficial to reducing the resistivity. And when combined with the back antireflection functional layer 4, the high doping concentration helps to reduce the contact resistance.

[0042] Preferably, the doping concentration of the first doped crystalline silicon layer 31 is lower than that of the third doped crystalline silicon layer 33. The advantage of this setting is to ensure the potential barrier while reducing the resistivity. The principle is that the doping concentration of the crystalline silicon close to the N-type silicon substrate 1 is higher than that of the N-type silicon substrate 1 by several orders of magnitude. The higher the doping concentration, the closer the Fermi level is to the conduction band, ensuring the energy level difference. The high doping concentration of the crystalline silicon far from the N-type silicon substrate 1 can improve the mobility, reduce the resistivity, and reduce the metal-semiconductor contact resistivity.

[0043] In some embodiments, the doping concentrations of the first doped crystalline silicon layer 31 and the third doped crystalline silicon layer 33 are both less than that of the second doped crystalline silicon layer 32: where: the doping concentration of the first doped crystalline silicon layer 31 is 1×10 20 cm -3 ~3×10 20 cm -3 ; the doping concentration of the second doped crystalline silicon layer 32 is 5×10 20 cm -3 ~1×10 21 cm -3 ; the doping concentration of the third doped crystalline silicon layer 33 is 3×10 20 cm -3 ~5×10 21 cm -3 It can be understood that although the first doped crystalline silicon layer 31 is lower than the second doped crystalline silicon layer 32, it is still higher than the N-type silicon substrate 1, making the Fermi level closer to the conduction band, which can ensure the potential barrier. The doping concentration of the second doped crystalline silicon layer 32 is relatively high, which can effectively reduce the resistivity. The doping concentration of the third doped crystalline silicon layer 33 is low, which can effectively reduce parasitic absorption and recombination.

[0044] Preferably, the doping concentration of the first doped crystalline silicon layer 31 is lower than that of the third doped crystalline silicon layer 33. The advantage of this setting is to ensure the potential barrier while reducing the resistivity. The principle is that the doping concentration of the crystalline silicon close to the N-type silicon substrate 1 is higher than that of the N-type silicon substrate 1 by several orders of magnitude. The higher the doping concentration, the closer the Fermi level is to the conduction band, ensuring the energy level difference. The high doping concentration of the crystalline silicon far from the N-type silicon substrate 1 can improve the mobility, reduce the resistivity, and reduce the metal-semiconductor contact resistivity.

[0045] In some embodiments, the thicknesses of the first doped crystalline silicon layer 31, the second doped crystalline silicon layer 32, and the third doped crystalline silicon layer 33 are all 10 nm - 60 nm. Specifically, they can be 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm. Of course, in other embodiments of the present utility model, the thicknesses of the first doped crystalline silicon layer 31, the second doped crystalline silicon layer 32, and the third doped crystalline silicon layer 33 can also be selected as other thicknesses according to actual needs.

[0046] In some embodiments, the thickness of the tunneling layer 2 is 1 nm - 2 nm. Specifically, it can be 1.1 nm, 1.2 nm, 1.3 nm, 1.4 nm, 1.5 nm, 1.6 nm, 1.7 nm, 1.8 nm, 1.9 nm, 2.0 nm. Of course, in other embodiments of the present utility model, the thickness of the tunneling layer 2 can also be selected as other thicknesses according to actual needs.

[0047] The specific structures of the N-type cell wafers of six embodiments of the present utility model will be described below.

[0048] Embodiment 1:

[0049] As Figure 2 shown, the N-type cell wafer of this embodiment includes an N-type silicon substrate 1, a tunneling layer 2, a doped crystalline silicon layer, a back surface antireflection functional layer 4, which are sequentially arranged on the back surface of the N-type silicon substrate 1, and a boron diffusion layer 7, a passivation layer 8, and a front surface antireflection functional layer 9, which are sequentially arranged on the front surface of the N-type silicon substrate 1. Electrodes 10 are provided on both the front and back surfaces of the N-type silicon substrate 1. The electrode 10 on the front surface penetrates through the front surface antireflection functional layer 9 and the passivation layer 8, and the electrode 10 on the back surface penetrates through the back surface antireflection functional layer 4. The doped crystalline silicon layer at least includes a first doped crystalline silicon layer 31, a second doped crystalline silicon layer 32, and a third doped crystalline silicon layer 33, which are sequentially arranged in the direction away from the back surface of the N-type silicon substrate 1. The doping concentrations of the first doped crystalline silicon layer 31 and the third doped crystalline silicon layer 33 are both greater than the doping concentration of the second doped crystalline silicon layer 32. Among them:

[0050] The first doped crystalline silicon layer 31, the second doped crystalline silicon layer 32, and the third doped crystalline silicon layer 33 are all microcrystalline silicon layers. The back surface antireflection functional layer 4 and the front surface antireflection functional layer 9 are silicon nitride layers, the tunneling layer 2 is a silicon oxide layer, and the passivation layer 8 is an aluminum oxide layer, a silicon oxide layer.

[0051] The N-type cell wafer of Embodiment 1 can not only ensure the thickness and doping concentration of the doped crystalline silicon, reduce the recombination current, but also ensure the potential barrier and reduce the optical parasitic absorption, and can better balance the light absorption and passivation effect of the N-type cell wafer.

[0052] It should be noted that, in the case of exactly the same structure, in the N-type solar cell of the first embodiment, the doping concentrations of the first doped crystalline silicon layer 31 and the third doped crystalline silicon layer 33 can also be both less than the doping concentration of the second doped crystalline silicon layer 32. The solar cells of the two structures have the same advantages.

[0053] Embodiment 2:

[0054] The N-type solar cell of this embodiment is basically similar in structure to the N-type solar cell of the first embodiment. The difference is that the first doped crystalline silicon layer 31, the second doped crystalline silicon layer 32, and the third doped crystalline silicon layer 33 are all nano-crystalline silicon layers.

[0055] The N-type solar cell of Embodiment 2 uses nano-crystalline silicon layers as the doped crystalline silicon layers on the basis of the first embodiment. The nano-crystalline silicon grains are smaller and the passivation effect is better.

[0056] It should be noted that, in the case of exactly the same structure, in the N-type solar cell of the second embodiment, the doping concentrations of the first doped crystalline silicon layer 31 and the third doped crystalline silicon layer 33 can also be both less than the doping concentration of the second doped crystalline silicon layer 32. The solar cells of the two structures have the same advantages.

[0057] Embodiment 3:

[0058] The N-type solar cell of this embodiment is basically similar in structure to the N-type solar cell of the first embodiment. The difference is that the tunneling layer 2 includes at least one of silicon carbide, silicon carbonitride, silicon nitride, and aluminum oxide.

[0059] The N-type solar cell of Embodiment 3 replaces the material of the tunneling layer 2 on the basis of the first embodiment. The introduction of carbon elements can make the thin film structure more dense, effectively inhibit film bursting, and during annealing, the introduction of carbon elements can effectively block the excessive diffusion of phosphorus into the silicon matrix.

[0060] It should be noted that, in the case of exactly the same structure, in the N-type solar cell of the third embodiment, the doping concentrations of the first doped crystalline silicon layer 31 and the third doped crystalline silicon layer 33 can also be both less than the doping concentration of the second doped crystalline silicon layer 32. The solar cells of the two structures have the same advantages.

[0061] Embodiment 4:

[0062] As Figure 3 shown, the N-type solar cell of this embodiment is basically similar in structure to the N-type solar cell of the first embodiment. The difference is that the N-type solar cell further includes a polysilicon layer 5 disposed between the tunneling layer 2 and the doped crystalline silicon layer.

[0063] The N-type solar cell of Embodiment 4 adds a polysilicon layer 5 on the basis of the first embodiment. The polysilicon structure has a higher crystallization rate and smaller parasitic absorption, which can make the light absorption function of the N-type solar cell better.

[0064] It should be added that, in the case of exactly the same structure, in the N-type solar cell of the fourth embodiment, the doping concentrations of the first doped crystalline silicon layer 31 and the third doped crystalline silicon layer 33 can also be both less than the doping concentration of the second doped crystalline silicon layer 32. The solar cells of the two structures have the same advantages.

[0065] Embodiment Five:

[0066] As Figure 4 shown, the N-type solar cell of this embodiment is basically similar in structure to the N-type solar cell of the fourth embodiment. The difference is that the N-type solar cell further includes a silicon oxide layer 6 disposed between the doped crystalline silicon layer and the polysilicon layer 5.

[0067] The N-type solar cell of Embodiment Five adds a silicon oxide layer 6 on the basis of the fourth embodiment. Adding the silicon oxide layer 6 can inhibit the excessive diffusion of phosphorus during annealing.

[0068] It should be added that, in the case of exactly the same structure, in the N-type solar cell of the fifth embodiment, the doping concentrations of the first doped crystalline silicon layer 31 and the third doped crystalline silicon layer 33 can also be both less than the doping concentration of the second doped crystalline silicon layer 32. The solar cells of the two structures have the same advantages.

[0069] Embodiment Six:

[0070] The N-type solar cell of this embodiment is basically similar in structure to the N-type solar cell of the first embodiment. The difference is that the back antireflection functional layer 4 and the front antireflection functional layer 9 are TCO layers. Based on the conductive characteristics of the TCO layer, a relatively low-temperature silver paste sintering technology can be used at the screen end of the printing process, thereby avoiding the contact between the electrode 10 grid lines and the crystalline silicon, effectively reducing the contact resistance; and the relatively low-temperature sintering is beneficial to inhibiting the diffusion escape and improving the passivation of the crystalline silicon.

[0071] It should be added that, in the case of exactly the same structure, in the N-type solar cell of the sixth embodiment, the doping concentrations of the first doped crystalline silicon layer 31 and the third doped crystalline silicon layer 33 can also be both less than the doping concentration of the second doped crystalline silicon layer 32. The solar cells of the two structures have the same advantages.

[0072] The present utility model also discloses a battery assembly, which includes any one of the N-type battery wafers described above. Since the battery assembly disclosed by the present utility model is composed of the N-type battery wafers described above, the battery assembly of the present utility model has advantages such as low parasitic absorption and low resistivity, has good overall performance, is beneficial to extending the service life, and enhances the market competitiveness of the product. The battery assembly disclosed by the present utility model may include only one N-type battery wafer, or may include multiple N-type battery wafers. When the battery assembly disclosed by the present utility model includes multiple N-type battery wafers, the structures of the multiple N-type battery wafers may be completely the same and be any one of the above-mentioned Embodiments 1 to 6, or the structures of the multiple N-type battery wafers may be different, and the structure of each N-type battery wafer may be selected from any one of Embodiments 1 to 6, as long as the actual needs can be met.

[0073] It should be supplemented and explained here that the battery assembly further includes a packaging structure for packaging the battery and a lead-out structure capable of leading out the N-type battery wafer. The specific forms of the packaging structure and the lead-out structure can be selected according to the prior art, and it is not necessary to describe the specific forms of the packaging structure and the lead-out structure here.

[0074] In the description of this specification, the descriptions referring to terms such as "some embodiments", "other embodiments", etc. mean that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present utility model. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0075] Obviously, the above-mentioned embodiments of the present utility model are merely examples given for clearly explaining the present utility model, and are not limitations on the implementation manners of the present utility model. For those of ordinary skill in the art, various obvious changes, re-adjustments and substitutions can be made without departing from the protection scope of the present utility model. It is not necessary and impossible to enumerate all the implementation manners here. Any modifications, equivalent substitutions and improvements made within the spirit and principle of the present utility model shall be included in the protection scope of the claims of the present utility model.

Claims

1. An N-type battery cell, characterized in that: The invention comprises an N-type silicon substrate (1), and a tunneling layer (2), a doped crystalline silicon layer, and a back-side anti-reflection functional layer (4) which are sequentially arranged on the back side of the N-type silicon substrate (1), wherein the doped crystalline silicon layer at least comprises a first doped crystalline silicon layer (31), a second doped crystalline silicon layer (32), and a third doped crystalline silicon layer (33) which are sequentially arranged in a back direction away from the N-type silicon substrate (1); the doping concentration of the first doped crystalline silicon layer (31) is greater than the doping concentration of the N-type silicon substrate (1); wherein: The doping concentrations of the first doped crystalline silicon layer (31) and the third doped crystalline silicon layer (33) are both greater than the doping concentration of the second doped crystalline silicon layer (32); or: The doping concentrations of the first doped crystalline silicon layer (31) and the third doped crystalline silicon layer (33) are both lower than the doping concentration of the second doped crystalline silicon layer (32).

2. The N-type battery cell according to claim 1, characterized in that: The first doped crystalline silicon layer (31), the second doped crystalline silicon layer (32) and the third doped crystalline silicon layer (33) are all microcrystalline silicon layers; or: The first doped crystalline silicon layer (31), the second doped crystalline silicon layer (32) and the third doped crystalline silicon layer (33) are all nanocrystalline silicon layers.

3. The N-type battery cell according to claim 1, characterized in that: The back anti-reflection functional layer (4) comprises a silicon nitride layer or a TCO layer; and / or: The tunneling layer (2) comprises at least one of a silicon oxide layer, a silicon carbide layer, a silicon oxycarbide layer, a silicon nitride layer and an aluminum oxide layer.

4. The N-type battery cell according to claim 1, characterized in that: The N-type cell further comprises at least one polysilicon layer (5) arranged between the tunneling layer (2) and the doped crystalline silicon layer.

5. The N-type battery cell according to claim 4, characterized in that: The N-type cell further comprises a silicon oxide layer (6), wherein the silicon oxide layer (6) is provided between the doped crystalline silicon layer and the polycrystalline silicon layer (5), between two adjacent polycrystalline silicon layers (5), or between two adjacent doped crystalline silicon layers.

6. The N-type battery cell according to claim 1, characterized in that: The thickness of the first doped crystalline silicon layer (31), the second doped crystalline silicon layer (32) and the third doped crystalline silicon layer (33) are all 10 nm to 60 nm.

7. The N-type battery cell according to claim 1, characterized in that: The thickness of the tunneling layer (2) is 1 nm to 2 nm.

8. A battery assembly, characterized in that: It comprises an N-type battery cell as described in any one of claims 1 to 7.

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