Power gallium nitride HEMT (High Electron Mobility Transistor) device with top heat dissipation surface-mounted packaging structure

Abstract

The utility model discloses a top heat dissipation surface-mounted packaging structure of a power gallium nitride HEMT device. The top heat dissipation surface-mounted packaging structure comprises a power gallium nitride HEMT chip, a slide holder, a grid electrode pin, a Kelvin source electrode pin, a source electrode pin and a drain electrode pin. Wherein the chip mounting area of the slide holder is connected with the power gallium nitride HEMT chip through solder or other modes, and is connected with a source electrode of the power gallium nitride HEMT chip through a metal bonding assembly. The source electrode pin is directly connected with the slide holder, and the Kelvin source electrode pin can be selectively connected with or separated from the slide holder. The grid electrode pin and the drain electrode pin are connected with the grid electrode and the drain electrode of the power gallium nitride HEMT chip through a metal bonding assembly. One surface, opposite to the chip mounting area, of the chip holder is exposed at the top of the packaging body to form a heat dissipation substrate, and each pin is formed towards one side, opposite to the heat dissipation substrate, of the chip holder and is used for welding and assembling a circuit board. Therefore, the power gallium nitride HEMT device can realize a top heat dissipation structure, and the heat dissipation efficiency and reliability are improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a power gallium nitride HEMT device with a top-cooled surface-mount package structure. Background Art

[0002] Traditional surface-mount packages mainly use bottom cooling for heat dissipation. Taking TOLL (Transistor Outline Leadless) package as an example, as Figure 1 shown, the bottom cooling method means that the metal heat dissipation substrate at the bottom of the package is welded to the surface copper layer of the circuit board, and then heat is conducted to the other side of the circuit board through thermal vias, and then connected to the heat sink to dissipate the heat into the environment. Using this heat dissipation method, the heat generated by the chip needs to be transferred through the heat dissipation substrate of the package body and the circuit board connected thereto, and the rest of the chip is wrapped in the plastic encapsulant with a low thermal conductivity and can only dissipate heat through limited air convection; therefore, the heat conduction efficiency depends to a large extent on the design of the circuit board, such as factors such as the size of the surface copper area of the circuit board, the number of copper layers, the copper thickness, whether to use thermal vias and the design parameters of thermal vias such as the aperture, the number of vias, and the copper thickness. The heat dissipation efficiency of the bottom cooling method is not only lower than that of the plug-in package, but also its electrical path and heat conduction path need to be realized on the circuit board connected to its bottom, so it is difficult to optimize the electrical performance and thermal performance of the system at the same time. In addition, since one side of the circuit board needs to be attached to the heat sink, and there are thermal vias connecting both sides designed on the circuit board, the space utilization rate of the circuit board is low, and the wiring flexibility inside the circuit board is greatly reduced.

[0003] To solve the above problems existing in the bottom cooling method and achieve a heat dissipation capacity close to or equivalent to that of the plug-in package device, the prior art has proposed a surface-mount package structure based on top cooling. This package structure is mainly applied to MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) devices or IGBT (Insulate-Gate Bipolar Transistor) devices with a vertical structure represented by silicon-based or silicon carbide-based. As Figure 2As shown, the drain (i.e., the drain region) of the electrical properties of the aforementioned two types of devices is located on the first side of the chip, and the source (i.e., the source region) and gate (i.e., the gate region) of the electrical properties are located on the second side of the chip. The first side and the second side are opposite to each other. Therefore, the first side can be directly electrically connected to the lead frame carrier stage through solder or other means. In a surface-mount package device with top heat dissipation, the side of the carrier stage opposite to the chip mounting area is exposed at the top of the package body, and the electrical function pins are led out to the side of the package body away from the heat dissipation substrate in the form of gull-wing pins or other shapes, so that the electrical function pins can be soldered to the circuit board. At the same time, to ensure the high-voltage insulation distance between the electrical function pins, the source pins and the gate pins can be placed on the first side of the package body, and the drain pins can be placed on the second side.

[0004] As Figure 3 shown, in a surface-mount package device with top heat dissipation, the heat generated by the chip can be directly dissipated into the environment through a heat sink connected to the heat dissipation substrate at the top of the device, thereby reducing the system thermal resistance. At the same time, all the electrical function pins of the device are soldered to a circuit board coplanar with the bottom of the package body, effectively decoupling the electrical path and the heat dissipation path, and increasing the wiring flexibility of the multi-layer circuit board, making more effective use of the space on both sides of the circuit board. In addition, since most of the heat is dissipated through the top of the device, the circuit board connected to the bottom of the device receives less heat. Therefore, the top heat dissipation method helps to reduce the operating temperature of adjacent devices, thereby improving the application reliability of the circuit system.

[0005] However, through research by the inventor, it is found that the existing top heat dissipation package structure cannot be applied to the packaging of power gallium nitride HEMT (High Electron Mobility Transistor) devices. Summary of the Invention

[0006] The purpose of this application is to solve the technical defect that the existing top heat dissipation package structure cannot be applied to the packaging of power gallium nitride HEMT devices.

[0007] In one embodiment, this application provides a power gallium nitride HEMT device with a top heat dissipation surface-mount package structure, including:

[0008] A power gallium nitride HEMT chip having a chip front and a chip back arranged opposite to each other, and the chip front has a source, a gate, and a drain;

[0009] The lead frame includes a carrier stage, a gate pin, at least one drain pin, and at least one source pin. The carrier stage is directly connected to each of the source pins. The source of the gallium nitride power HEMT chip is connected to the source pin through a first metal bonding component and is connected to the back of the chip. The gate pin is connected to the gate through a second metal bonding component, and the drain pin is connected to the drain through a third metal bonding component. Among them, the gate pin, the drain pin, and the source pin are all bent along a first direction, and the first direction is the direction from the carrier stage to the gallium nitride power HEMT chip.

[0010] In one embodiment, the lead frame further includes a Kelvin source pin, and there are two ways for the Kelvin source pin to be connected to the source.

[0011] In one embodiment, the Kelvin source pin is directly connected to the carrier stage.

[0012] In one embodiment, the Kelvin source pin is connected to the source through a fourth metal bonding component.

[0013] In one embodiment, the gallium nitride power HEMT chip has a first side and a second side arranged oppositely. Each of the drain pins is arranged on the first side, and each of the source pins, the gate pin, and the Kelvin source pin are all arranged on the second side.

[0014] In one embodiment, the shortest distance between the Kelvin source pin and the carrier stage in the first direction is greater than or equal to 0.6 millimeters.

[0015] In one embodiment, the shortest distance between the gate pin and the carrier stage in the first direction is greater than or equal to 0.6 millimeters.

[0016] In one embodiment, the shortest distance between the drain pin and the carrier stage in the first direction is greater than or equal to 0.6 millimeters.

[0017] In one embodiment, the gallium nitride power HEMT device with a top heat dissipation surface-mount package structure further includes a package body. The carrier stage, the gallium nitride power HEMT chip, the first metal bonding component, the second metal bonding component, the third metal bonding component, and parts of the gate pin, the drain pin, and the source pin are placed in the package body by means of plastic encapsulation molding. Parts of the gate pin, the drain pin, and the source pin all extend out of the package body. The side of the carrier stage opposite to the chip mounting area is exposed at the top of the package body to form a heat dissipation substrate. The chip mounting area refers to the area for mounting the gallium nitride power HEMT chip.

[0018] In one embodiment, the package is made of epoxy resin.

[0019] Compared with the prior art, the present application has the following advantages and technical effects:

[0020] The power gallium nitride HEMT device disclosed in the embodiment of the present application may include a power gallium nitride HEMT chip and a lead frame. The lead frame may include a carrier stage, a gate pin, a source pin, a Kelvin source pin, and a drain pin. Among them, the chip attachment area of the carrier stage is connected to the power gallium nitride HEMT chip by solder or other means, and the source of the power gallium nitride HEMT chip is directly bonded to the carrier stage of the lead frame through a metal bonding component. The source pin is directly connected to the carrier stage. The gate pin, the drain pin, and the carrier stage of the lead frame are separated, and the drain pin maintains a vertical potential difference with the carrier stage of the lead frame as the source end, so that there is enough creepage distance between the drain end and the source end. The Kelvin source pin can be optionally connected to or separated from the carrier stage of the lead frame. The gate pin and each drain pin are connected to the gate and drain of the power gallium nitride HEMT chip through a metal bonding component. The side of the lead frame carrier stage opposite to the chip attachment area is exposed at the top of the package to form a heat dissipation substrate; the electrical function pins are led out to the side of the package opposite to the heat dissipation substrate in the form of gull-wing pins or other shapes for soldering to a circuit board. In this way, the power gallium nitride HEMT device realizes a top heat dissipation structure, thereby improving the heat dissipation efficiency and reliability of the power gallium nitride HEMT device. At the same time, all electrical function pins are soldered to a circuit board coplanar with the bottom of the package, effectively decoupling the electrical path and the heat dissipation path, increasing the flexibility of multilayer circuit board wiring, and making more effective use of the space on both sides of the circuit board. And the pin dimensions and functional positions of this new package shape are exactly the same as those of the corresponding package shapes of the industry-standard silicon-based or silicon carbide-based MOSFET devices or IGBT devices, and are mutually compatible. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art.

[0022] Figure 1 FIG. 17 is a schematic diagram of the system heat dissipation method of a bottom heat dissipation surface-mounted package device in the prior art;

[0023] Figure 2 FIG. 21 is a schematic structural diagram of a silicon-based or silicon carbide-based MOSFET or IGBT surface-mounted package device with a top heat dissipation method in the prior art;

[0024] Figure 3 In the prior art, it is a schematic diagram of the system heat dissipation method using a top-cooled surface-mounted package device;

[0025] Figure 4 In one embodiment of the present application, it is one of the top-view schematic diagrams of the package structure of a power gallium nitride HEMT device;

[0026] Figure 5 In one embodiment of the present application, it is another top-view schematic diagram of the package structure of a power gallium nitride HEMT device;

[0027] Figure 6 In one embodiment of the present application, it is a side view of a power gallium nitride HEMT device;

[0028] Explanation of reference numerals:

[0029] 100 - Power gallium nitride HEMT chip, 200 - Carrier stage, 300 - Gate pin, 400 - Drain pin, 500 - Source pin, 600 - Kelvin source pin, 71 - Top circuit layer of the circuit board, 72 - Bottom circuit layer of the circuit board, 73 - Chip, 74 - Heat dissipation substrate, 75 - Plastic seal, 76 - Resistor or capacitor component, 77 - Circuit board, 78 - Internal circuit layer bypassing the thermal vias, 79 - Thermal via, 80 - Heat sink, 81 - Internal circuit layer. Detailed implementation manners

[0030] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. The described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present application.

[0031] As described in the background art, the existing top-cooled surface-mounted package structures for MOSFET devices or IGBT devices with a vertical structure represented by silicon-based or silicon carbide-based cannot be used for the package of power gallium nitride HEMT devices. After research by the inventor, it is found that the reason for this problem is that in the power gallium nitride HEMT chip, the source region, the gate region, and the drain region are located on the same surface of the chip, and the source region of the power gallium nitride HEMT device needs to be electrically connected to the carrier stage. Therefore, the existing lead frames and package structures cannot be directly used to obtain a power gallium nitride HEMT device with a top-cooled surface-mounted package structure.

[0032] To solve the above problems, the present application discloses a novel top - heat - dissipation surface - mount packaging structure that can be used for packaging power gallium nitride HEMT devices, which can improve the heat - dissipation efficiency of the power gallium nitride HEMT device system application, thereby reducing the switching loss of the power gallium nitride HEMT device system application and improving the stability and reliability of the system application.

[0033] In some embodiments, the power gallium nitride HEMT device (hereinafter simply referred to as the power gallium nitride HEMT device) of the top - heat - dissipation surface - mount packaging structure disclosed in the present application may include a power gallium nitride HEMT chip 100 and a lead frame. The lead frame may include a carrier stage 200, a gate pin 300, at least one drain pin 400, and at least one source pin 500. Among them, the number of drain pins 400 and source pins 500 can be determined according to the actual situation, and no specific limitation is made herein. In some examples, the number of drain pins 400 can be multiple, and the number of source pins 500 can be multiple.

[0034] Please see Figure 4 and Figure 5 , the power gallium nitride HEMT chip 100 has a chip front and a chip back, the chip front is opposite to the chip back, and the chip front has a source, a gate, and a drain.

[0035] The source of the power gallium nitride HEMT chip 100 is connected to the source pin 500 through a first metal bonding component and is connected to the chip back through solder or other means. Each source pin 500 of the lead frame is directly connected to the carrier stage 200. The carrier stage 200 can be attached to the chip back of the power gallium nitride HEMT chip 100 and is connected to the source of the power gallium nitride HEMT chip 100. It can be understood that the carrier stage 200 and the source of the power gallium nitride HEMT chip 100 can be connected in any manner, and no specific limitation is made herein. Exemplarily, the carrier stage 200 can be connected to the source of the power gallium nitride HEMT chip 100 through a metal bonding component, and the metal bonding component can be a metal lead.

[0036] The gate pin 300 can be connected to the gate of the power gallium nitride HEMT chip 100 through a second metal bonding component, and each drain pin 400 can be connected to the drain of the power gallium nitride HEMT chip 100 through a third metal bonding component. It can be understood that the "metal bonding component" involved herein can be an electrical connection component of any shape and any material, and no specific limitation is made herein, as long as the metal bonding component can achieve the electrical connection function. In one example, the metal bonding component can be a metal lead.

[0037] Such as Figure 6As shown, the first direction F1 in this text refers to the direction from the carrier stage 200 towards the gallium nitride on power (GaN-on-Power) HEMT chip 100. The gate pins 300, each drain pin 400, and each source pin 500 can be bent along the first direction F1, and the side of the carrier stage 200 opposite to the chip mounting area is exposed at the top of the package. When the gallium nitride on power HEMT device is soldered to the circuit board, the carrier stage 200, the gallium nitride on power HEMT chip 100, and the circuit board are stacked in sequence, and the carrier stage 200 acting as a heat dissipation substrate is arranged on the side far from the circuit board, thereby realizing top heat dissipation.

[0038] The top heat dissipation surface mount package structure used in this application is different from the existing similar package structures. The differences are at least: the carrier stage 200 in this application is connected to the source of the device instead of the drain, and the drain pins 400 in this application can maintain a certain vertical displacement difference from the carrier stage 200. The top heat dissipation surface mount package structure disclosed in this application is more suitable for planar gallium nitride on power HEMT devices, can improve the heat dissipation efficiency of the gallium nitride on power HEMT devices, utilize the excellent characteristics of fast switching speed and high switching frequency of the gallium nitride on power HEMT devices more effectively and stably, and can improve the efficiency and power density of the power system, which is beneficial to realizing automated assembly, enhancing the flexibility of the circuit board wiring design, and realizing effective decoupling of the electrical path and the heat dissipation path.

[0039] In one embodiment, as Figure 4 and Figure 5 shown, to effectively improve the switching stability and reliability of the gallium nitride on power HEMT device, the lead frame structure of this application has a Kelvin source pin 600, and there are two ways for the Kelvin source pin 600 to be connected to the source of the gallium nitride on power HEMT chip 100.

[0040] In one example, as Figure 4 shown, the Kelvin source pin 600 can be connected to the source of the gallium nitride on power HEMT chip 100 through a fourth metal bonding component, and the realization of its electrical function is through the metal bonding component to connect from the source above the gallium nitride on power HEMT chip 100 to the bonding area of the Kelvin source pin 600. That is, the Kelvin source can be connected to the source of the gallium nitride on power HEMT chip 100 through the metal bonding component. Among them, for the specific description of the metal bonding component, reference can be made to the relevant description of the metal bonding component in the above text, and it will not be elaborated here.

[0041] In one embodiment, as Figure 5As shown, the Kelvin source pin 600 can be directly connected to the carrier stage 200 to electrically connect to the source of the gallium nitride power HEMT chip 100 through the carrier stage 200. That is, the source pin 500 of the lead frame and the Kelvin source pin 600 can be directly connected to the carrier stage 200, and the source of the gallium nitride power HEMT chip 100 can be connected to the corresponding area of the carrier stage 200 through a metal bonding component to achieve electrical connection. In this way, the electrical parameters of the gallium nitride power HEMT device are further optimized. On the other hand, the switching speed of the gallium nitride power HEMT device can be increased, thereby optimizing the switching efficiency.

[0042] In one embodiment, as Figure 4 and Figure 5 shown, the gallium nitride power HEMT chip 100 has a first side and a second side that are oppositely arranged. Each drain pin 400 is arranged on the first side, and each source pin 500, gate pin 300, and Kelvin source pin 600 are all arranged on the second side. Further, the gate pin 300, the Kelvin source pin, and each source pin 500 can be sequentially arranged along the edge of the carrier stage 200. In this way, the pin function positions of the gallium nitride power HEMT device are consistent with those of general silicon-based or silicon carbide-based MOSFET devices or IGBT devices, and can be mutually compatible during circuit design.

[0043] In one example, the number of drain pins 400 can be 7, and the number of source pins 500 can be 5. In this way, the gallium nitride power HEMT device can be completely consistent with general silicon-based or silicon carbide-based MOSFET devices or IGBT devices in terms of the number of pins, pin size, and pin function positions, further improving device compatibility.

[0044] In one embodiment, the gate pin 300 of the gallium nitride power HEMT device is separated from the carrier stage 200, that is, the gate pin 300 is not in direct contact with the carrier stage 200. The shortest distance between the gate pin 300 and the carrier stage 200 in the first direction F1 is greater than or equal to 0.6 mm to improve the isolation effect.

[0045] In one embodiment, the drain pin 400 of the gallium nitride power HEMT device is separated from the carrier stage 200, that is, the drain pin 400 is not in direct contact with the carrier stage 200 and maintains a vertical difference from the carrier stage 200 as the source end, so that there is enough creepage distance between the drain end and the source end. In one example, the shortest distance between each drain pin 400 and the carrier stage 200 in the first direction F1 is greater than or equal to 0.6 mm to improve the isolation effect.

[0046] In one embodiment, the Kelvin source pin 600 of the power gallium nitride HEMT device and the carrier stage 200 are separately arranged, that is, the Kelvin source pin 600 is not in direct contact with the carrier stage 200 and maintains a vertical potential difference with the carrier stage 200 serving as the source terminal. In one example, the shortest distance between the Kelvin source pin 600 and the carrier stage 200 in the first direction F1 is greater than or equal to 0.6 mm. In one embodiment, the power gallium nitride HEMT device may further include a package body. The carrier stage 200, the power gallium nitride HEMT chip 100, the first metal bonding component, the second metal bonding component, the third metal bonding component, and parts of the gate pin 300, parts of the drain pin 400, and parts of the source pin 500 (including the Kelvin source pin 600) are placed in the package body by means of plastic encapsulation molding. Parts of the gate pin 300, parts of each drain pin 400, and parts of each source pin 500 (including the Kelvin source pin 600) extend out of the package body. That is, the orthographic projection of each pin (including the gate pin 300, the drain pin 400, the source pin 500, and the Kelvin source pin 600) in the first direction F1 has an overlapping area and a non-overlapping area with the orthographic projection of the package body in the first direction F1. Through the external lead of the pins, welding is performed with the circuit board. In one example, the gate pin 300, the drain pin 400, the source pin 500, and the Kelvin source pin 600 can be gull-wing pins to improve the board-level reliability.

[0047] The side of the carrier stage 200 opposite to the chip mounting area is exposed at the top of the package body to form a heat dissipation substrate. Herein, the chip mounting area refers to the area on the carrier stage 200 for mounting the power gallium nitride HEMT chip 100. It can be understood that the power gallium nitride HEMT chip 100 can be mounted in any area of the carrier stage 200, and this is not specifically limited herein.

[0048] It can be understood that the package body can be made of any material and can be of any shape, and its shape and preparation material can be determined according to the actual situation. In one example, the package body can be made of epoxy resin.

[0049] In one embodiment, the power gallium nitride HEMT chip 100 may be depletion type and may be made based on a dual-chip stacked package. That is, the power gallium nitride HEMT chip 100 may include a power gallium nitride HEMT chip 100 and a silicon-based MOSFET chip 700 arranged in a stacked core. The power gallium nitride HEMT chip 100 is located at the bottom layer, and the silicon-based MOSFET chip 700 is located at the top layer. By adopting a cascode stacked package structure, using this power gallium nitride HEMT device can simplify the control circuit structure and improve the circuit reliability. Finally, it should also be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article or device including the said element. In this article, "a", "an", "the", "this" and "its" may also include the plural form, unless the context clearly indicates otherwise. A plurality means at least two cases, such as 2, 3, 5 or 8, etc. "And / or" includes any and all combinations of the related listed items.

[0050] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The various embodiments can be combined as needed, and the same or similar parts can be referred to each other.

[0051] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be obvious to those skilled in the art. The general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to these embodiments shown herein, but will be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A power gallium nitride HEMT device with a top heat dissipation surface mount packaging structure, characterized in that: include: A power gallium nitride HEMT chip, comprising a chip front side and a chip back side arranged opposite to each other, wherein the chip front side has a source electrode, a gate electrode and a drain electrode; A lead frame comprises a wafer carrier, a gate pin, at least one drain pin and at least one source pin, wherein the wafer carrier is directly connected to each of the source pins, the source of the power gallium nitride HEMT chip is connected to the source pin through a first metal bonding component and is connected to the back side of the chip; the gate pin is connected to the gate through a second metal bonding component, and the drain pin is connected to the drain through a third metal bonding component; wherein the gate pin, the drain pin and the source pin are all bent along a first direction, and the first direction is the direction in which the wafer carrier points to the power gallium nitride HEMT chip.

2. The power gallium nitride HEMT device of the top heat dissipation surface mount packaging structure according to claim 1, characterized in that: The lead frame further includes a Kelvin source pin, and there are two ways of connecting the Kelvin source pin to the source.

3. The power gallium nitride HEMT device of the top heat dissipation surface mount packaging structure according to claim 2, characterized in that: The Kelvin source pin is directly connected to the wafer carrier.

4. The power gallium nitride HEMT device of the top heat dissipation surface mount packaging structure according to claim 2, characterized in that: The Kelvin source pin is connected to the source through a fourth metal bonding component.

5. The power gallium nitride HEMT device of the top heat dissipation surface mount package structure according to any one of claims 2 to 4, characterized in that: The power gallium nitride HEMT chip has a first side and a second side that are arranged opposite to each other, each of the drain pins is arranged on the first side, and each of the source pins, the gate pin and the Kelvin source pin are arranged on the second side.

6. The power gallium nitride HEMT device of the top heat dissipation surface mount packaging structure according to claim 4, characterized in that: The shortest distance between the Kelvin source pin and the wafer stage in the first direction is greater than or equal to 0.6 mm.

7. The power gallium nitride HEMT device with a top heat dissipation surface mount packaging structure according to claim 1, characterized in that: The shortest distance between the gate pin and the wafer stage in the first direction is greater than or equal to 0.6 mm.

8. The power gallium nitride HEMT device with a top heat dissipation surface mount packaging structure according to claim 1, characterized in that: The shortest distance between the drain pin and the wafer stage in the first direction is greater than or equal to 0.6 mm.

9. The power gallium nitride HEMT device of the top heat dissipation surface mount package structure according to any one of claims 2 to 4, characterized in that: The power gallium nitride HEMT device of the top heat dissipation surface mount package structure further includes a package body, wherein the wafer carrier, the power gallium nitride HEMT chip, the first metal bonding component, the second metal bonding component, the third metal bonding component, and a portion of the gate pin, a portion of the drain pin, and a portion of the source pin are placed in the package body by means of plastic packaging; a portion of the gate pin, a portion of the drain pin, a portion of the source pin, and a portion of the Kelvin source pin all extend out of the package body; a side of the wafer carrier opposite to the mounting area is exposed at the top of the package body to form a heat dissipation substrate; the mounting area refers to an area for mounting the power gallium nitride HEMT chip.

10. The power gallium nitride HEMT device of the top heat dissipation surface mount packaging structure according to claim 9, characterized in that: The packaging body is made of epoxy resin.

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