Packaging structure of power chip

Abstract

The utility model discloses a power chip packaging structure, which comprises a substrate, a laminated structure body, a lead and a packaging layer, and is characterized in that the laminated structure body is arranged at one side of the substrate along a first direction, the laminated structure body comprises a heat dissipation layer, a switching layer and a bare chip which are laminated, the heat dissipation layer is arranged at one side of the bare chip facing the substrate, and the switching layer is arranged at the other side of the bare chip facing the substrate; the bare chip, the heat dissipation layer and the substrate are fixed through the switching layer, the lead is connected with the bare chip and the substrate, and the packaging layer is used for packaging the stacked structure body, the lead and part of the substrate. Wherein the heat conductivity of the heat dissipation layer in the second direction is larger than that of the transfer layer in the second direction, and the second direction intersects with the first direction. According to the packaging structure of the power chip in the embodiment of the invention, the heat dissipation efficiency of the power chip can be remarkably improved, and the junction temperature and the thermal resistance of the power chip are improved.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and particularly relates to a packaging structure for a power chip. Background Art

[0002] With the evolution of advanced wafer manufacturing process nodes and the development of advanced chip packaging technologies, the power density of chips has increased significantly, resulting in a significant increase in the heat flux density of chips, posing higher requirements for chip thermal management technologies.

[0003] Among them, within a power chip, the heat flux density of the bare chip is relatively large, and the heat - generating area is relatively small. It is impossible to directly dissipate heat only by using an external heat sink, which is extremely likely to cause heat accumulation inside the power chip, thereby deteriorating the chip junction temperature and thermal resistance. Therefore, a solution to improve the thermal performance of power chips is urgently needed. Summary of the Utility Model

[0004] The embodiments of this application provide a packaging structure for a power chip, which can improve the heat dissipation efficiency of the power chip and improve the junction temperature and thermal resistance of the power chip.

[0005] On the one hand, the embodiments of this application provide a packaging structure for a power chip, including: a substrate; a stacked structure body disposed on one side of the substrate along a first direction, the stacked structure body including a heat - dissipation layer, an interposer layer, and a bare chip stacked, the heat - dissipation layer being disposed on the side of the bare chip facing the substrate, and the bare chip, the heat - dissipation layer, and the substrate being fixed through the interposer layer; a wire connecting the bare chip and the substrate; and a packaging layer packaging the stacked structure body, the wire, and a part of the substrate; wherein, the thermal conductivity of the heat - dissipation layer along a second direction is greater than the thermal conductivity of the interposer layer along the second direction, and the second direction intersects with the first direction.

[0006] According to one aspect of this application, the heat - dissipation layer is one of a diamond heat sink and a diamond composite heat sink.

[0007] According to one aspect of this application, the interposer layer is one of silver paste and solder paste.

[0008] According to one aspect of this application, within the stacked structure body, the interposer layers on both sides of the heat - dissipation layer are electrically connected.

[0009] According to one aspect of this application, the heat - dissipation layer includes a plurality of through - holes penetrating along the first direction, and the interposer layer on one side of the heat - dissipation layer extends into the through - holes and is electrically connected to the interposer layer on the other side.

[0010] According to one aspect of the present application, the power chip includes a plurality of bare chips, and at least part of the bare chips are correspondingly provided with the heat dissipation layer on one side facing the substrate.

[0011] According to one aspect of the present application, the power chip includes a plurality of the stacked structures, and the plurality of the stacked structures are arranged on the substrate at intervals.

[0012] According to one aspect of the present application, the heat dissipation layer is provided in its entirety on the substrate, the stacked structure includes a plurality of the bare chips, and the plurality of the bare chips are arranged on the heat dissipation layer at intervals.

[0013] According to one aspect of the present application, the stacked structure includes a plurality of bare chips stacked, and along the first direction, the heat dissipation layer is provided between at least two adjacent bare chips and / or between the bare chip and the substrate.

[0014] According to one aspect of the present application, two adjacent bare chips are arranged in a staggered overlapping manner, and the heat dissipation layer between the two adjacent bare chips covers the overlapping area.

[0015] The packaging structure of the power chip provided by the embodiment of the present application includes a substrate, a stacked structure, a wire, and a packaging layer. The substrate and the stacked structure are connected by the wire and are packaged by the packaging layer. In the stacked structure, by providing the heat dissipation layer on the side of the bare chip facing the substrate and making the thermal conductivity of the heat dissipation layer along the second direction greater than the thermal conductivity of the transfer layer along the second direction, it can be ensured that during the operation of the power chip, the heat generated by the bare chip can be laterally conducted along the second direction through the heat dissipation layer with an extremely low thermal resistance, so that the heat concentrated in a partial area of the bare chip is dispersed by the heat dissipation layer and quickly conducted to the substrate to dissipate to the outside, thereby fully improving the heat dissipation efficiency of the power chip and enhancing the reliability of the power chip. Description of the Drawings

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required to be used in the embodiments of the present application. Obviously, the following described drawings are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0017] Figure 1 is a schematic cross-sectional view of the packaging structure of the power chip provided by some embodiments of the present application;

[0018] Figure 2 is a schematic cross-sectional view of the packaging structure of the power chip provided by other embodiments of the present application;

[0019] Figure 3 It is a flowchart of a method for manufacturing a power chip provided by some embodiments of the present application;

[0020] Figure 4 It is a schematic diagram of step S10 in the manufacturing method provided by some embodiments of the present application;

[0021] Figure 5 It is a schematic diagram of step S20 in the manufacturing method provided by some embodiments of the present application;

[0022] Figure 6 It is a schematic diagram of step S30 in the manufacturing method provided by some embodiments of the present application;

[0023] Figure 7 It is a schematic diagram of step S40 in the manufacturing method provided by some embodiments of the present application;

[0024] Figure 8 It is a schematic diagram of step S50 in the manufacturing method provided by some embodiments of the present application;

[0025] Figure 9 It is a schematic diagram of step S60 in the manufacturing method provided by some embodiments of the present application;

[0026] Figure 10 It is a schematic diagram of step S70 in the manufacturing method provided by some embodiments of the present application.

[0027] In the drawings:

[0028] 1 - Substrate; 2 - Stacked structure; 21 - Heat dissipation layer; 22 - Interposer layer; 23 - Bare chip; 3 - Conductive wire; 4 - Encapsulation layer;

[0029] X - Second direction; Z - First direction. Detailed implementation manners

[0030] The features and exemplary embodiments of various aspects of the present application will be described in detail below. To make the objectives, technical solutions and advantages of the present application more clear and understandable, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application and are not configured to limit the present application. For those skilled in the art, the present application can be implemented without some of these specific details. The following description of the embodiments is only intended to provide a better understanding of the present application by showing examples of the present application.

[0031] It should be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variant thereof are intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the said element.

[0032] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "above" or "over" another layer or another region, it may mean directly above the other layer or another region, or there may be other layers or regions between it and the other layer or another region. And if the component is flipped, this layer or this region will be "below" or "beneath" the other layer or another region.

[0033] Without departing from the spirit or scope of the present application, various modifications and variations can be made to the present application, which will be apparent to those skilled in the art. Therefore, the present application is intended to cover modifications and variations of the present application that fall within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in the present application can be combined with each other without conflict.

[0034] For a better understanding of the present utility model, the following will be described in detail with reference to Figures 1 to 10 the packaging structure of the power chip according to the embodiments of the present application.

[0035] Please refer to Figure 1 , the embodiments of the present application provide a packaging structure of a power chip, including a substrate 1, a stacked structure body 2, a wire 3 and a packaging layer 4. The stacked structure body 2 is arranged on one side of the substrate 1 along the first direction Z. The stacked structure body 2 includes a heat dissipation layer 21, an interposer layer 22 and a bare chip 23 which are stacked. The heat dissipation layer 21 is arranged on the side of the bare chip 23 facing the substrate 1. The bare chip 23, the heat dissipation layer 21 and the substrate 1 are fixed to each other through the interposer layer 22. The wire 3 connects the bare chip 23 and the substrate 1. The packaging layer 4 is used to package the stacked structure body 2, the wire 3 and a part of the substrate 1. Wherein, the thermal conductivity of the heat dissipation layer 21 along the second direction X is greater than the thermal conductivity of the interposer layer 22 along the second direction X, and the second direction X intersects with the first direction Z.

[0036] In the packaging structure of the power chip in the embodiments of the present application, the substrate 1 and the stacked structure 2 are connected by a wire 3 and are packaged by a packaging layer 4. Inside the stacked structure 2, by providing a heat dissipation layer 21 on the side of the bare chip 23 facing the substrate 1, and making the thermal conductivity of the heat dissipation layer 21 along the second direction X greater than the thermal conductivity of the interposer layer 22 along the second direction X, it can be ensured that during the operation of the power chip, the heat generated by the bare chip 23 can be laterally conducted along the second direction X with an extremely low thermal resistance through the heat dissipation layer 21, so that the heat concentrated in a partial area of the bare chip 23 is dispersed through the heat dissipation layer 21 and quickly conducted to the substrate 1 to dissipate to the outside, thereby fully improving the heat dissipation efficiency of the power chip and enhancing the reliability of the power chip.

[0037] Wherein, the first direction Z is the thickness direction of the stacked structure 2, and the second direction X is the lateral direction.

[0038] It can be understood that, compared with the method of directly connecting the bare chip 23 to the substrate 1 through the interposer layer 22, in the embodiments of the present application, by providing a heat dissipation layer 21 on the side of the bare chip 23 facing the substrate 1 and making the thermal conductivity of the heat dissipation layer 21 along the lateral direction greater than the thermal conductivity of the interposer layer 22 along the lateral direction, the heat of the bare chip 23 can be more effectively laterally conducted, and then the heat can be efficiently transferred to the external heat sink through the substrate 1, improving the junction temperature and thermal resistance of the power chip under the same external heat sink configuration.

[0039] The following describes each part structure of the power chip.

[0040] The substrate 1 can be a packaging substrate or a lead frame. The substrate 1 is used to provide support, heat dissipation, and protection functions, and at the same time provide an electrical connection between the power chip and the circuit board. Passive and active devices can be buried in the substrate 1 to achieve certain system functions.

[0041] The stacked structure 2 includes an interposer layer 22, a heat dissipation layer 21, and a bare chip 23 that are stacked on the substrate 1.

[0042] The bare chip 23 is a wafer die. Die refers to the die before packaging, which is a small piece cut from a silicon wafer by laser. Each die is an independent functional chip and will ultimately be packaged as a unit.

[0043] The heat dissipation layer 21 is used to be arranged under the bare chip 23. It can also withstand a part of the heat. And for the problem of large heat flux density of the bare chip 23, it can laterally propagate the heat concentrated at the bottom of the bare chip 23 with an extremely low thermal resistance, disperse it on the heat dissipation layer 21 and then transfer it to the substrate 1 for heat dissipation, effectively avoiding heat accumulation, fully improving the heat dissipation efficiency of the substrate 1, so that the junction temperature and thermal resistance of the chip are significantly improved under the same external heat sink configuration.

[0044] The interconnection layer 22 is used to be disposed between the substrate 1 and the heat dissipation layer 21, as well as between the heat dissipation layer 21 and the bare chip 23, so as to realize the connection and fixation between the stacked structure 2 and the substrate 1, as well as within the stacked structure 2 itself, and reduce the risk of connection failure caused by deformation of the substrate 1, the heat dissipation layer 21 or the bare chip 23.

[0045] The wire 3 is a bonding wire, such as a gold wire, a copper wire or an aluminum wire, and realizes the electrical interconnection between the bare chip 23 and the outside by interconnecting the input / output pads of the bare chip 23 with the substrate 1.

[0046] The encapsulation layer 4 is filled with an insulating resin, specifically an epoxy thermosetting resin, and is used to encapsulate the vulnerable parts such as the stacked structure 2, the wire 3 and a part of the substrate 1, etc., so as to prevent the influence and damage of the external environment.

[0047] Wherein, after encapsulation, the substrate 1 has a heat dissipation surface and pins that are exposed outside the encapsulation layer 4, i.e., not encapsulated, for heat and electrical connection. The heat conducted to the substrate 1 can be quickly dissipated through the heat dissipation surface, and the heat is conducted to the outside for heat dissipation, so that the chip can quickly conduct heat during operation, with good heat dissipation effect and high reliability.

[0048] It can be understood that the thermal conductivity of the heat dissipation layer 21 is greater than that of the interconnection layer 22. Here, the thermal conductivity can be reflected by the thermal conductivity coefficient of the material. The higher the thermal conductivity coefficient of the material, the stronger the thermal conductivity. The heat dissipation layer 21 and the interconnection layer 22 can be made of different materials, so that the thermal conductivity of the heat dissipation layer 21 in the transverse direction is greater than the heat conduction ability of the interconnection layer 22 in the transverse direction.

[0049] Wherein, the unit of the thermal conductivity coefficient is watt per meter kelvin, and can also be written as W / (m·k).

[0050] In some alternative embodiments, the heat dissipation layer 21 is one of a diamond heat sink and a diamond composite heat sink.

[0051] The diamond heat sink is generally cut from a 4-inch diamond wafer prepared by chemical vapor deposition. The crystal structure of diamond determines its high thermal conductivity. The thermal conductivity coefficient of diamond is as high as 1200W / (m·k) - 2000W / (m·k), and it has good heat conduction performance. The diamond composite heat sink refers to a heat sink made of a composite material of diamond and metal, and by doping a metal material, such as copper.

[0052] In addition, by setting the heat dissipation layer 21 as a diamond composite heat sink, it can have a certain electrical conductivity. Whether the heat dissipation layer 21 is specifically set as a diamond heat sink or a diamond composite heat sink can be adjusted according to the electrical conductivity requirements of the heat dissipation layer 21, and it only needs to meet the thermal conductivity of the heat dissipation layer 21 in the transverse direction.

[0053] Optionally, the size of the heat dissipation layer 21 in the first direction Z is greater than 100 um, that is, the thermal conductivity of the heat dissipation layer 21 is greater than 800 W / (m·k), and a thickness of about 100 um can meet the heat dissipation requirements. Further, the size of the heat dissipation layer 21 in the first direction Z can be less than 1000 um to reduce the thickness of the stacked structure 2 and reduce the size of the power chip.

[0054] In some alternative embodiments, the interconnection layer 22 is one of silver paste and solder paste.

[0055] By setting the interconnection layer 22 as silver paste, the connection and fixation between the stacked structure 2 and the substrate 1 and within the stacked structure 2 itself can be achieved after curing. Moreover, silver paste has certain thermal and electrical conductivity capabilities, and can transfer heat along the first direction Z through the interconnection layer 22 to improve the heat dissipation efficiency of the power chip. Of course, the interconnection layer 22 can also be set as solder paste, or other interconnection materials, as long as the connection and fixation requirements between the stacked structure 2 and the substrate 1 and between the layers of the stacked structure 2 itself can be achieved.

[0056] Please refer to Figure 2 , in some cases, the stacked structure 2 needs to be set as a conductive structure. For some heat dissipation layers 21, the heat dissipation layer 21 is not conductive. Therefore, in order to realize the functions of the stacked structure 2, in some alternative embodiments, within the stacked structure 2, the interconnection layers 22 on both sides of the heat dissipation layer 21 are electrically connected.

[0057] Among them, the interconnection layers 22 on both sides of the heat dissipation layer 21 being electrically connected can be achieved by setting a conductive structure on the periphery of the heat dissipation layer 21 to realize the electrical connection of the interconnection layer 22, or by setting a conductive structure within the heat dissipation layer 21 to realize the electrical connection of the interconnection layer 22.

[0058] In some alternative embodiments, the heat dissipation layer 21 includes a plurality of through holes penetrating along the first direction Z, and the interconnection layer 22 on one side of the heat dissipation layer 21 extends into the through holes and is electrically connected to the interconnection layer 22 on the other side.

[0059] By setting a plurality of through holes on the heat dissipation layer 21, without the need to set other conductive structures, the through holes can be directly used to make the interconnection layers 22 on both sides of the heat dissipation layer 21 contact each other to realize the electrical connection of the interconnection layer 22. The structure is simple, which is more convenient for the preparation of power chips and reduces costs.

[0060] Optionally, the positions, sizes, and numbers of the through holes on the heat dissipation layer 21 can all be adjusted according to the conductive requirements of the power chip, and the present application does not make specific limitations thereon.

[0061] For the power chip, it includes a single-die structure and a multi-die structure.

[0062] The single-die structure means that there is only one bare chip 23 in the power chip, and the bare chip 23 is connected to the substrate 1 through the heat dissipation layer 21 and is packaged.

[0063] When the power chip is a multi-die structure, in some alternative embodiments, the power chip includes multiple bare chips 23, and at least part of the bare chips 23 are correspondingly provided with heat dissipation layers 21 on one side facing the substrate 1. By providing the heat dissipation layer 21 under at least part of the bare chips 23, the heat of the multiple bare chips 23 can be quickly transferred to the substrate 1 through the heat dissipation layer 21, improving the heat dissipation effect of the power chip.

[0064] Specifically, when the power chip is a multi-die structure, it includes two arrangement forms: a planar structure and a stacked structure. The planar structure means that multiple bare chips 23 are arranged in the same layer, and the stacked structure means that multiple bare chips 23 are stacked together along the first direction Z.

[0065] For the planar structure, in some alternative embodiments, the power chip includes multiple stacked structures 2, and the multiple stacked structures 2 are arranged at intervals on the substrate 1. Alternatively, the heat dissipation layer 21 is provided as a whole layer on one side of the substrate 1, and the stacked structure 2 includes multiple bare chips 23, and the multiple bare chips 23 are arranged at intervals on the heat dissipation layer 21.

[0066] When multiple bare chips 23 need to be independently grounded, multiple stacked structures 2 can be provided, and the stacked structures 2 are independently arranged at intervals. Each stacked structure 2 includes a bare chip 23 and a heat dissipation layer 21, and the heat of each bare chip 23 can be dissipated through the corresponding heat dissipation layer 21 to meet the heat dissipation requirements of high-power density chips.

[0067] When multiple bare chips 23 can share the same grounding body, the multiple bare chips 23 can share the same heat dissipation layer 21, and the heat of each bare chip 23 can be transferred to the heat dissipation layer 21 and diffusely transfer heat through the heat dissipation layer 21 to simplify the structure of the power chip and improve the reliability of the power chip.

[0068] For the stacked structure, in some alternative embodiments, the stacked structure 2 includes multiple stacked bare chips 23, and along the first direction Z, a heat dissipation layer 21 is provided between at least two adjacent bare chips 23 and / or between the bare chip 23 and the substrate 1.

[0069] Among them, a heat dissipation layer 21 is provided between at least two adjacent bare chips 23 and / or between the bare chip 23 and the substrate 1 means that the heat dissipation layer 21 can be provided only between the lowermost bare chip 23 and the substrate 1, or multiple heat dissipation layers 21 can be provided. Among the multiple heat dissipation layers 21, some are provided between two adjacent bare chips 23, and some are provided between the bare chip 23 and the substrate 1.

[0070] In some optional embodiments, two adjacent bare chips 23 are arranged in a staggered overlapping manner, and the heat dissipation layer 21 between two adjacent bare chips 23 covers the overlapping area.

[0071] When multiple bare chips 23 are vertically stacked, by arranging the bare chips 23 in a staggered overlapping manner, it is convenient for each bare chip 23 to lead out a wire 3 to be connected to the substrate 1. On this basis, when the heat dissipation layer 21 is arranged between two adjacent bare chips 23, the heat dissipation layer 21 between two adjacent bare chips 23 can cover the overlapping area to increase the area of the heat dissipation layer 21, so that the concentrated heat is dispersed in the heat dissipation layer 21, effectively avoiding heat accumulation and meeting the heat dissipation requirements of high-power density bare chips 23.

[0072] Please refer to Figures 3 to 10 , taking the single-die structure of an embodiment of the present application as an example, the preparation method of the power chip is described as follows, which includes the following steps:

[0073] S10. Provide a substrate 1;

[0074] S20. Pattern and coat silver paste on the substrate 1;

[0075] S30. Bond the diamond heat sink to the silver paste and dry and cure it;

[0076] S40. Coat silver paste above the diamond heat sink;

[0077] S50. Bond the bare chip 23 to the diamond heat sink through silver paste to form a stacked structure 2;

[0078] S60. Connect the pads of the bare chip 23 to the pins of the substrate 1 through the wire 3;

[0079] S70. Package the stacked structure 2, the wire 3 and a part of the substrate 1.

[0080] Please refer to Figure 4 , in S10, the substrate 1 can be set as a commonly used package substrate or lead frame in power chip packaging.

[0081] Please refer to Figure 5 , in S20, the screen can be contacted with the substrate 1, and the silver paste is printed onto the surface of the substrate 1 through a squeegee to form an interposer layer 22.

[0082] Please refer to Figure 6 , in S30, the diamond heat sink can be bonded to the silver paste in the form of surface mounting, or can be bonded to the silver paste in the form of being picked up by a chuck, so as to form a heat dissipation layer 21. The diamond heat sink can be a structure packaged in a tape form or a structure scribed in a wafer form.

[0083] Please refer to Figure 7, in S40, silver paste is applied on the diamond heat sink by means of nozzle dispensing to form an interconnection layer 22 on the heat dissipation layer 21.

[0084] Please refer to Figure 8 , in S50, the scribed and ground bare chip 23 is picked up by a chuck and bonded to the silver paste on the diamond heat sink under a certain pressure.

[0085] Please refer to Figure 9 , in S60, the pads of the bare chip 23 are connected to the pins of the substrate 1 through the wire 3 for interconnection, realizing the electrical interconnection between the bare chip 23 and the outside.

[0086] Please refer to Figure 10 , in S70, an epoxy thermosetting resin can be used to encapsulate the vulnerable parts such as the stacked structure 2, the wire 3 and part of the substrate 1 to form an encapsulation layer 4 to prevent the influence and damage of the external environment.

[0087] It can be understood that the above preparation method has low cost, simple operation, is compatible with the packaging power of existing power chips, only needs to add one more chip mounting process, is applicable to various packaging types, and has broad application prospects.

[0088] The heat dissipation effect of the power chip in the above application embodiment is compared and analyzed by simulation. As shown in Table 1, where Scheme 1 is the packaging structure of the existing power chip, that is, the bare chip 23 is directly bonded to the substrate 1 through silver paste, and Scheme 2 is the packaging structure of the power chip in the application embodiment of the present application. By setting the heat dissipation layer 21 under the bare chip 23, the junction temperature can be reduced by 11.2% and the thermal resistance can be reduced by 33%, and the effect is remarkable.

[0089] Moreover, by analyzing the interfacial heat flux distribution nephogram in the simulation results, it is found that in Scheme 2 proposed in this patent, by introducing the heat dissipation layer 21, the lateral conduction of the temperature at the bottom of the bare chip 23 can be significantly enhanced, so that the concentrated chip temperature is dispersed on the heat dissipation layer 21, and then conducted to the external heat sink through the substrate 1, effectively avoiding heat accumulation and meeting the heat dissipation requirements of high power density chips.

[0090] Table 1: Simulation comparison of heat dissipation effect

[0091] Solution Thermal power (W) Case point temperature (°C) Junction temperature (°C) Temperature difference (°C) Thermal resistance (°C / W) Solution 1 3.3W 110.93 134.69 23.76 7.2 Solution 2 3.3W 103.62 119.54 15.92 4.8

[0092] The above are only specific implementation manners of the present application. Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the systems, modules and units described above can refer to the corresponding processes in the foregoing method embodiments, and will not be elaborated herein. It should be understood that the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of various equivalent modifications or substitutions, and these modifications or substitutions should be covered within the protection scope of the present application.

[0093] It should also be noted that the exemplary embodiments mentioned in the present application describe some methods or systems based on a series of steps or devices. However, the present application is not limited to the order of the above steps, that is, the steps can be executed in the order mentioned in the embodiments, or different from the order in the embodiments, or several steps can be executed simultaneously.

Claims

1. A packaging structure of a power chip, characterized in that: include: substrate; A stacked structure is arranged on one side of the substrate along the first direction, the stacked structure comprises a heat dissipation layer, a transfer layer and a bare chip which are stacked, the heat dissipation layer is arranged on a side of the bare chip facing the substrate, and the bare chip, the heat dissipation layer and the substrate are fixed to each other through the transfer layer; A wire connecting the bare chip and the substrate; A packaging layer, packaging the stacked structure, the wires and a portion of the substrate; The thermal conductivity of the heat dissipation layer along the second direction is greater than the thermal conductivity of the transfer layer along the second direction, and the second direction intersects with the first direction.

2. The packaging structure of the power chip according to claim 1, characterized in that: The heat dissipation layer is one of a diamond heat sink and a diamond composite heat sink.

3. The packaging structure of the power chip according to claim 1, characterized in that: The transfer layer is one of silver paste and solder paste.

4. The packaging structure of the power chip according to claim 1, characterized in that: In the stacked structure, the transfer layers located on both sides of the heat dissipation layer are conductively connected.

5. The packaging structure of the power chip according to claim 4, characterized in that: The heat dissipation layer includes a plurality of through holes penetrating along the first direction, and the transfer layer located on one side of the heat dissipation layer extends into the through holes and is conductively connected with the transfer layer located on the other side.

6. The packaging structure of a power chip according to any one of claims 1 to 5, characterized in that: The power chip includes a plurality of bare chips, and the heat dissipation layer is correspondingly arranged on a side of at least some of the bare chips facing the substrate.

7. The packaging structure of the power chip according to claim 6, characterized in that: The power chip includes a plurality of the stacked structures, and the plurality of the stacked structures are arranged on the substrate at intervals.

8. The packaging structure of the power chip according to claim 6, characterized in that: The heat dissipation layer is entirely disposed on the substrate, and the stacked structure includes a plurality of bare chips, which are disposed on the heat dissipation layer at intervals.

9. The packaging structure of the power chip according to claim 6, characterized in that: The stacked structure includes a plurality of bare chips stacked in layers, and along the first direction, the heat dissipation layer is disposed between at least two adjacent bare chips and / or between the bare chip and the substrate.

10. The packaging structure of the power chip according to claim 9, characterized in that: Two adjacent bare chips are arranged in a staggered overlapping manner, and the heat dissipation layer between the two adjacent bare chips covers the overlapping area.

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