Test structure for detecting open circuit of transistor channel
By designing multiple test units with different number of channels and using resistance measurement, the problem of monitoring transistor channel process is solved, and the accurate positioning of the channel breaking position is achieved.
Patent Information
- Application Number
- CN202421960499.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-14
- Publication Date
- 2025-05-30
- Estimated Expiration
- 2034-08-14
AI Technical Summary
In ultra-deep submicron semiconductor manufacturing, the process of monitoring a single transistor channel becomes very difficult, especially because the channel opening is difficult to accurately locate.
A test structure is provided, including at least two test units of different channels, each of which consists of one or more transistors, and determines whether there is a channel damage and circuit breaker through resistance measurement.
Through a number of test units composed of different channels and electrical parameter testing methods, effective monitoring of a single channel process is achieved, and the channel break position can be accurately positioned.
Smart Images
Figure CN222927498U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of semiconductor manufacturing, and particularly relates to a test structure for detecting transistor channel open circuit. Background Art
[0002] With the development of microelectronics technology, integrated circuits have now entered the era of ultra-deep submicron, which makes the feature size of electronic devices smaller and smaller, and the chip scale larger and larger. Circuits with tens of millions or even more than one billion gates can be integrated on a single chip. As the size of semiconductor devices decreases day by day, molecular epitaxy technology has become one of the most critical processes in semiconductor manufacturing at the 28nm and below nodes.
[0003] EPI grows the required size of EPI on silicon through selective growth. The size of EPI has a significant impact on the performance of semiconductor devices, including situations such as transistor channel open circuit caused during the process. Since semiconductor devices have multiple channels, when one of the channels is damaged and open, current can still pass through, and the entire device does not show an open circuit situation. Therefore, it becomes very difficult to monitor the process of a single channel.
[0004] Therefore, there is a need to provide a new test structure for monitoring the growth of transistor channels and accurately locating the position of channel open circuit. Summary of the Utility Model
[0005] The utility model provides a test structure for detecting transistor channel open circuit to monitor the growth of channels in a transistor in order to solve all or part of the above-mentioned prior art problems.
[0006] To achieve the above object, the present utility model provides a test structure for detecting transistor channel open circuit, which includes at least two test units with different numbers of channels; each test unit includes one or more transistors; each transistor includes a channel structure and a gate structure, the gate structure straddles the channel structure, and the channel structure includes one or more spaced channels; when the test unit includes one transistor, it is led out from both ends of the channel structure on one side of the gate structure in the transistor; when the test unit includes multiple transistors, the multiple transistors are connected in series and led out from both ends of the channel structures on the same side of the gate structure in the first and last transistors; the test units with different numbers of channels refer to the different numbers of channels set in the channel structures of the transistors in the test units; the channel structures of the transistors in the same test unit are set with the same number of channels. By providing multiple test units composed of transistors with different numbers of channels and measuring their resistance values using the two-terminal method, according to the resistance value relationship of the measured test units, it can be used to determine whether there is a situation of channel damage and open circuit, providing a feasible solution for monitoring the process of a single channel using electrical parameter testing methods.
[0007] In some of these embodiments, the test unit includes multiple transistors, and the multiple transistors are arranged in a transistor array of multiple rows and multiple columns; the transistors in the same row are connected in series through corresponding channels and are alternately connected in series across layers on both sides of the transistor array to form a serpentine test link; wherein, the cross-layer series connection includes connecting the corresponding channels on the same side of the gate structure in two transistors in series through a metal wire connecting the active region, a via, and a first metal wire. Arranging the multiple transistors in the test unit in an array and connecting them in a serpentine series can connect as many transistors in series as possible in the available area, saving area, and effectively improving the sensitivity of the test structure and the accuracy of the test results.
[0008] In some of these embodiments, when the test unit includes one transistor, the test unit is led out across layers from both ends of the channel structure on one side of the gate structure in the transistor; when the test unit includes multiple transistors, the multiple transistors are connected in series and led out across layers from both ends of the channel structures on the same side of the gate structure in the first and last transistors; wherein, the cross-layer leading out includes leading out the channel structure through a metal wire connecting the active region, a via, and a first metal wire for testing. Using the first metal wire as a test pin to lead out the test structure without preparing additional leading-out structures can simplify the test structure.
[0009] In some of these embodiments, the channel structure in the transistor includes N spaced-apart channels; the test structure includes test units with N different numbers of channels, that is, the test structure includes: a test unit with 1 channel, …, a test unit with i channels, …, a test unit with N channels, where i ∈ [1, N] and N ≥ 2.
[0010] In some of these embodiments, in the test structure, each test unit includes the same number of transistors. This further simplifies the test structure and can simplify the manufacturing process and facilitate the series connection of multiple transistors.
[0011] In some of these embodiments, the test structure includes at least one first test unit, at least one second test unit, and at least one third test unit; the first test unit refers to a test unit in which the channel structure of the transistor has one channel; the second test unit refers to a test unit in which the channel structure of the transistor has two channels; the third test unit refers to a test unit in which the channel structure of the transistor has three channels. By using three test units respectively composed of transistors with 1, 2, and 3 channels, it is possible to determine whether there is a channel damage and open circuit in a three-channel semiconductor device based on the resistance test results.
[0012] In some of these embodiments, when the number of transistors is one, the transistors in the three test units are arranged in the same row in ascending order of the number of channels; when the number of transistors is multiple, the transistors in the same test unit are connected in series, and each transistor in different test units corresponds one by one and is arranged in the same column in ascending order of the number of channels. Corresponding the transistors in different test units one by one and arranging them in the same column in the order of the number of channels can simplify the manufacturing process and make it more convenient to concentrate multiple test units to save area.
[0013] Compared with the prior art, the main beneficial effects of the present utility model are: providing a test structure for transistor channel open circuit, and based on the test results of this structure, it can be used to determine whether there is a channel damage and open circuit situation to achieve the monitoring of a single channel. Description of the Drawings
[0014] In order to more clearly illustrate the technical solutions in the specific embodiments of the present utility model, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following described drawings are only some embodiments of the present utility model. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.
[0015] Figure 1Schematic diagram of the test unit for Embodiment 1.
[0016] Figure 2 Top view schematic diagram of the test structure for Embodiment 2.
[0017] Figure 3 Top view schematic diagram of the test structure for Embodiment 3.
[0018] Figure 4 Schematic diagram of the current path during measurement of the test structure for Embodiment 3.
[0019] Figure 5 Test result diagram of the test structure for Embodiment 3. Figure 5 A is the result when the channel in the test structure is normal, Figure 5 B is the result when there is channel damage in the test structure. Detailed implementation manners
[0020] Regarding the foregoing and other technical contents, features and effects of the present utility model, they will be clearly presented in the following detailed description of the preferred embodiments with reference to the drawings. The directional terms mentioned in the following embodiments, such as: up, down, left, right, front or back, etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are for illustration and not for limiting the present utility model.
[0021] The test structure involved in the present utility model includes at least two test units. Among them, according to different test conditions and test purposes, the test structure can be composed of at least two test units, or can be combined by more test units; the compositions of the test units can be the same or different. The following uses three embodiments in conjunction with the drawings to separately illustrate the test structure.
[0022] Embodiment 1:
[0023] Figure 1 Schematic diagram of the test unit in the test structure for Embodiment 1.
[0024] In this embodiment, the test structure includes two test units; each test unit includes a transistor, the transistor includes a channel structure and a gate structure, the gate structure straddles the channel structure, the channel structure includes one or more spaced channels, and the number of channels in the two test units is different: a test unit with one channel and a test unit with two channels. As Figure 1 shown, it is a test unit with two channels in the test structure, that is, a transistor with two channels. It should be noted that in this application, the transistor is Figure 1 the structure shown, but in other embodiments, transistors with advanced processes can also be used, that is, transistors with other architectures under continuous miniaturization of applicable processes.
[0025] Specifically, in this embodiment, each transistor includes two parts: a channel structure and a gate structure; at least one channel is included in the channel structure of each transistor. When multiple channels are provided in the channel structure of the transistor, the multiple channels are spaced apart from each other. In this embodiment, two test units can be arranged from left to right, that is, two transistors are arranged on the same substrate and arranged in the same row in the order of the number of channels provided in the transistors; the difference between the transistors in these two test units lies in the number of channels inside them, and the number of channels from left to right is 2 and 1 in sequence.
[0026] In other embodiments, it is only required that the number of channels in the above two transistors is 2 and 1 respectively, and the arrangement order of these two transistors is not required.
[0027] To simplify the preparation process of the test structure and for the convenience of subsequent testing, metal wires (metal wires in the metal layer M0A) connecting the active regions, vias (vias in the via layer V0), and first metal wires (metal wires in the metal layer M1) are also provided to realize the cross-layer connection of the channel structures in the test units. In this embodiment, in each test unit, 2 metal wires connecting the active regions are provided, and are respectively arranged at both ends of the channel structure on the side of the gate structure in the transistor and are respectively connected thereto. For example, it can be found that channel structures extend out on both sides of the gate structure. At this time, either side of the channel structure can be selected for connection, that is, the same ends of the multiple channels on the selected side are simultaneously connected to a metal wire connecting the active region, and the other ends of the multiple channels on the selected side are simultaneously connected to another metal wire connecting the active region.
[0028] In each test unit, a via and a first metal wire are also provided at the same time. Through this via, the connection between the metal wire connecting the active region and the first metal wire can be realized, so as to connect the channel structure in the test unit across layers and use it for testing. In this application, all the metal wires connecting the active regions are located in the same M0A metal layer, and all the first metal wires are located in the same M1 metal layer. To simplify the structure and facilitate preparation, test pins for connecting out the test units are formed on the first metal wires, that is, a part of the first metal wire is used as the test pin.
[0029] In this embodiment, the resistance of the two transistors with different numbers of channels in the two test units is measured respectively by the two-terminal method, and the resistance value Rs-2 channels of the transistor with 2 channels and the resistance value Rs-1 channel of the transistor with 1 channel can be obtained respectively. However, in other embodiments, the four-terminal Kelvin four-terminal method can also be used to measure the resistance, and the number of test pins is set accordingly. This patent does not make specific limitations.
[0030] According to the correspondence relationship between two resistance values, it can be determined whether there is a channel open circuit. The determination method is as follows: when all channels are normal, for each additional channel in the transistor, the current-carrying capacity increases, and the resistance of the device decreases. That is, in the normal state, for two transistors with different channel numbers, if the two measured resistance values Rs-1 channel and Rs-2 channel are measured, they should decrease linearly. Usually, if the measured resistance values are not linear and the deviation exceeds the preset deviation threshold, it can be suspected that there is an open circuit in the channels of the transistor (an open circuit in a certain channel will cause the resistance to increase).
[0031] In this embodiment, there are two test units. In other embodiments, the test structure may also include three test units with different channel numbers, or even more test units with different channel numbers. Here, the test units with different channel numbers refer to the test units in which the channel structures of the transistors have different channel numbers set.
[0032] In other embodiments, the channel structure in the transistor includes N phase-spaced channels, where N is a positive integer and N≥2; the test structure includes at least N test units with different channel numbers. The N test units with different channel numbers are respectively a test unit with 1 channel,..., a test unit with i channels,..., a test unit with N channels, where i∈[1,N] and N≥2.
[0033] Embodiment 2:
[0034] To increase the sensitivity of the test structure and the accuracy of the test results, the number of transistors in each test unit can be increased and all the transistors in the test unit can be connected in series for testing. Figure 2 FIG. is a top view schematic diagram of the test structure of Embodiment 2. To simplify the drawing, the three-dimensional test structure is presented from the perspective of a top view. For easy understanding, it can be combined with Figure 1 the test structure in for understanding.
[0035] As Figure 2 shown, the test structure in this embodiment includes three test units; each test unit includes 9 transistors connected in series, and the number of channels set in the transistors in the same test unit is the same. The basic structure of the transistors in the test unit can be the same as that in Embodiment 1, or it can be a transistor of an advanced process, that is, a transistor of other architectures under the continuous miniaturization of the applicable process, which will not be elaborated here. In other embodiments, the number of transistors connected in series in the test unit can be other numbers, which can be flexibly determined according to the test purpose and the test area.
[0036] As Figure 2As shown, the Fin structure in the figure is used to represent the channel structure in a transistor, and the transistors of adjacent test units are separated by a gate structure (i.e., the Poly structure shown in the figure). It should be noted that the attached Figure 2 is only a schematic illustration of the test structure for convenience of representation, and does not mean the actual structure of the transistor.
[0037] For each test unit, 9 transistors connected in series are arranged in the up-down direction in the figure, and three test units are arranged adjacent to each other in the left-right direction in the figure. In this application, the extending direction of the channel in the transistor is along the left-right direction in the figure, and the extending direction of the gate structure is along the up-down direction in the figure; the arrangement of transistors in the up-down direction is called row setting, and the arrangement in the left-right direction is called column setting.
[0038] In this embodiment, in each test unit, the transistors are arranged in rows and connected in series through corresponding channels, and each transistor in the same test unit has the same number of channels; three test units are arranged in columns, that is, each transistor in the three test units is arranged in columns in one-to-one correspondence. For the three test units arranged in columns, the number of channels of the transistors in the test units from left to right is 1, 2, and 3 in sequence. After the 9 transistors in each test unit are connected in series, a test link is formed, that is, test link chain1 formed by connecting 9 transistors with 1 channel in series, test link chain2 formed by connecting 9 transistors with 2 channels in series, and test link chain3 formed by connecting 9 transistors with 3 channels in series.
[0039] In the same test unit, the series connection method of two adjacent transistors with the same number of channels arranged in the same row is: all the channels on the same side of the gate structure of the two are respectively connected together. It should be noted that in the actual manufacturing process of the transistor, the corresponding channels in two adjacent transistors up and down in the same test unit can be grown epitaxially together without additional means to achieve their connection.
[0040] In this embodiment, metal wires, vias, and first metal wires connecting the active regions are also provided to realize the cross-layer connection of both ends of the channel structure on one side of the gate structure in the test unit. In this embodiment, in each test unit, 2 metal wires connecting the active regions are provided, which are respectively arranged on both sides of the two transistors at the head and tail ends of the series-connected transistors and are respectively connected to both ends of the channel structures on the same side of the gate structure of the head and tail transistors, that is, the metal wire connecting the active region on the upper side connects one end of the channel structure on one side of the gate structure of the transistor at the head end, and the metal wire connecting the active region on the lower side connects one end of the channel structure on the same side of the gate structure of the transistor at the tail end.
[0041] In each test unit, a through hole and a first metal wire are also provided. Through the through hole, the connection between the metal wire connecting the active region and the first metal wire can be realized, so that the channel structure in the test unit can be connected out across layers and used for testing. In this application, all the metal wires connecting the active region are located in the same M0A metal layer, and all the first metal wires are located in the same M1 metal layer. To simplify the structure and facilitate preparation, a test pin for connecting out the test unit is formed on the first metal wire, that is, a part of the first metal wire is used as the test pin.
[0042] The resistance of the three test units in the test structure is measured respectively by the two-terminal method, and 3 resistance values can be obtained. According to the corresponding relationship between the 3 resistance values, it can be judged whether there is a channel open circuit.
[0043] In this embodiment, there are three test units. In other embodiments, the test structure includes at least two test units with different channel numbers. The test units with different channel numbers here refer to the test units with different channel numbers set in the channel structure of the transistors in the test unit.
[0044] In this embodiment, the transistors in the three test units are arranged adjacent to each other in the same column. In other embodiments, different test units can be arranged separately.
[0045] Embodiment Three:
[0046] In order to further improve the sensitivity of the test structure, more transistors need to be connected in series in each test unit. If the transistors in the test unit are arranged in one direction, it will waste the test area. For this reason, the transistors in each test unit can be arranged in the form of a transistor array with multiple rows and multiple columns, that is, they are repeatedly arranged in the up-down direction and the left-right direction, and a complete structure is formed by the serpentine series connection method, so that more transistors can be connected in series as much as possible in the available area.
[0047] Figure 3 FIG. is a top view schematic diagram of the test structure of Embodiment Three.
[0048] As Figure 3 shown, the test structure in this embodiment also includes three test units. Each test unit includes 45 transistors connected in series. The specific structure of the transistors in the test unit can refer to Embodiment One and Embodiment Two, and will not be elaborated here.
[0049] Referring to Figure 2 and Figure 3 it can be seen that Figure 3 the present embodiment shown is in Figure 2It is formed on the basis of the second embodiment. The number of transistors in each test unit is increased to 45, with 9 transistors arranged in the same row and a total of 5 rows, that is, arranged in the form of a 9-row and 5-column transistor array; the transistors arranged in the same row are connected in series through the corresponding channels, and the transistors in adjacent rows are alternately connected in series across layers on both sides of the transistor array, connecting a total of 45 transistors in series into a serpentine test link; and three different test units are arranged in the same column, that is, each transistor in the three test units is arranged in the same column one by one. For the three test units arranged in the same column, the number of channels of the transistors in the test units from left to right is 1, 2, and 3 respectively.
[0050] In this embodiment, the test unit composed of transistors with one channel is denoted as the first test unit, the test unit composed of transistors with two channels is denoted as the second test unit, and the test unit composed of transistors with three channels is denoted as the third test unit. All the transistors in the first test unit are connected in series in a serpentine shape to form a serpentine test link snakechain1, all the transistors in the second test unit are connected in series in a serpentine shape to form a serpentine test link snakechain2, and all the transistors in the third test unit are connected in series in a serpentine shape to form a serpentine test link snakechain3.
[0051] The method of connecting the test links in a serpentine shape is as follows: Taking the formation of the serpentine test link snakechain1 as an example, first connect the 9 transistors arranged in the same row in series to form a test link chain1 (the connection method here refers to the second embodiment), then there are 5 test links chain1, and the 5 test links chain1 from left to right can be named the first test link chain1, the second test link chain1, the third test link chain1, the fourth test link chain1, and the fifth test link chain1. As Figure 3As shown in the figure, first, the first test link chain1 and the second test link chain1 are connected in series across layers. That is, by connecting the metal wires, vias, and the first metal wire in the active region, the corresponding channels on the same side of the gate structure in the two transistors at the lower ends of the two test links are connected in series. Specifically, a metal wire connecting the active region is provided at each of the lower ends of the first test link chain1 and the second test link chain1, and the channel structures on the same side of the gate structure in the transistors at the lower ends of these two test links chain1 (for example, in this embodiment, the channels connected are those on the left side of the gate structure) are respectively connected to the corresponding metal wires connecting the active region; then, the two metal wires connecting the active region are connected to the first metal wire by using vias, thereby realizing the series connection across layers of the first test link chain1 and the second test link chain1; the series connection across layers is alternately performed on both sides of the transistor array by using the same method. That is, at the other end (i.e., the upper end) of the second test link chain1, the second test link chain1 and the third test link chain1 are connected in series, so that the 5 test links chain1 are connected in series in a snake shape, and finally, a snake-shaped test link snakechain1 is formed. Similarly, a snake-shaped test link snakechain2 and a snake-shaped test link snakechain3 are formed respectively in the above manner. At the head and tail ends of the formed snake-shaped test link snakechain1, snake-shaped test link snakechain2, and snake-shaped test link snakechain3, a metal wire connecting the active region is also provided respectively, and the channel structures on the same side of the gate structure in the transistors at the head and tail ends are respectively led out through the metal wire connecting the active region, vias, and the first metal wire for testing, and the test pins are formed on the led-out first metal wire.
[0052] The resistance of the snake-shaped test link snakechain1, snake-shaped test link snakechain2, and snake-shaped test link snakechain3 in the test structure is measured respectively by the two-terminal method, and 3 resistance values can be obtained. According to the corresponding relationship between the 3 resistance values, it can be judged whether there is a channel open circuit. Figure 4 It is a schematic diagram of the current path during the measurement of the test structure in Embodiment 3. The arrow direction in the figure indicates the direction of current flow. As Figure 4 shown, 45 transistors (9 in each row, a total of 5 rows) are connected in series in each snakechain structure in the figure.
[0053] In this embodiment, there are three test units. In other embodiments, the test structure includes at least two test units with different channel numbers. Here, the test units with different channel numbers refer to the test units with different numbers of channel structures set in the transistors.
[0054] In this embodiment, the transistors in the three test units are arranged adjacent to each other in the same column. In other embodiments, different test units can be separately arranged.
[0055] Figure 5 It is the test result diagram of the test structure of Embodiment 3. Figure 5 A is the result when the channel in the test structure is normal. As Figure 5 shown in A, the Rs resistance values measured by the normal 3 EPI chains are linear. Among them, the resistance value of Channel 1 is the resistance value of the serpentine test link snakechain1, the resistance value of Channel 2 is the resistance value of the serpentine test link snakechain2, and the resistance value of Channel 3 is the resistance value of the serpentine test link snakechain3. As the number of channels in the transistor gradually increases from 1 to 3, the total resistance value of the corresponding serpentine test link snakechain continuously decreases, and the resistance values of the three show a linear relationship, indicating that no channel in the test structure is damaged and open-circuited.
[0056] As Figure 5 shown in B, the resistance values of the serpentine test link snakechain1, the serpentine test link snakechain2, and the serpentine test link snakechain3 are not in a linear relationship, indicating that there may be a damaged and open-circuited channel. According to the corresponding relationship of the three groups of resistance values, it can be found that the resistance value of the serpentine test link snakechain3 is only about 10% smaller than the resistance value of the serpentine test link snakechain2, indicating that one channel in the transistor with 3 channels may be damaged and open-circuited.
Claims
1. A test structure for detecting a transistor channel disconnection, characterized in that: comprising at least two test cells having different numbers of channels; The test unit includes one or more transistors; the transistor includes a channel structure and a gate structure, the gate structure spans the channel structure, and the channel structure includes one or more spaced channels; When the test unit includes one transistor, the two ends of the channel structure located on one side of the gate structure of the transistor are connected; when the test unit includes multiple transistors, the multiple transistors are connected in series and then connected through the two ends of the channel structure located on the same side of the gate structure of the first and last transistors; The test units with different numbers of channels refer to the test units in which the channel structures of the transistors are arranged with different numbers of channels; the channel structures of the transistors in the same test unit are arranged with the same number of channels.
2. A test structure for detecting a transistor channel disconnection according to claim 1, characterized in that: The test unit includes a plurality of transistors, and the plurality of transistors are arranged in a transistor array of multiple rows and columns; The transistors in the same row are connected in series through corresponding channels, and are alternately connected in series across layers on both sides of the transistor array, so that the multiple transistors are connected in series into a serpentine test link; The cross-layer series connection includes connecting corresponding channels located on the same side of the gate structure in two transistors in series by connecting the metal wires, through holes and the first metal wires in the active area.
3. A test structure for detecting a transistor channel disconnection according to claim 1, characterized in that: When the test unit includes one transistor, the test unit is connected across layers through two ends of a channel structure located on one side of a gate structure in the transistor; when the test unit includes multiple transistors, the multiple transistors are connected in series and connected across layers through two ends of a channel structure located on the same side of a gate structure in the first and last transistors; The cross-layer connection includes connecting the channel structure for testing by connecting the metal wires, through holes and the first metal wires in the active area.
4. A test structure for detecting a transistor channel disconnection according to claim 1, characterized in that: The channel structure in the transistor includes N spaced channels; The test structure includes N test units with different numbers of channels, that is, the test structure includes: a test unit with 1 channel, ..., a test unit with i channel, ..., a test unit with N channel, i∈[1,N], N≥2.
5. A test structure for detecting a transistor channel disconnection according to claim 4, characterized in that: In the test structure, each test unit includes the same number of transistors.
6. A test structure for detecting a transistor channel disconnection according to claim 5, characterized in that: comprising at least one first test unit, at least one second test unit and at least one third test unit; The first test unit refers to a test unit in which the channel structure of the transistor in the test unit is provided with one channel; The second test unit refers to a test unit in which the channel structure of the transistor in the test unit is provided with two channels; The third test unit refers to a test unit in which the channel structure of the transistor in the test unit is provided with three channels.
7. A test structure for detecting a transistor channel disconnection according to claim 6, characterized in that: When the number of the transistor is one, the transistors in the three test units are arranged in the same column from small to large according to the number of the channels; when the number of the transistors is multiple, the transistors in the same test unit are connected in series, and each transistor in different test units corresponds to each other one by one and are arranged in the same column from small to large according to the number of the channels.