Silicon carbide MOSFET half-bridge driving protection circuit

Abstract

The utility model provides a silicon carbide MOSFET half-bridge driving protection circuit comprising a first driving circuit and a second driving circuit, the first driving circuit and the second driving circuit are connected with a voltage conversion circuit module and a bridge arm interlocking logic module, the first driving circuit is also connected with a first isolation power supply module, a first driving resistor Rg and a silicon carbide MOSFET Q1, and the second driving circuit is also connected with a second isolation power supply module. The second driving circuit is also connected with a second isolation power supply module, a second driving resistor Rg and a silicon carbide MOSFET Q2; the bridge arm interlocking logic module is also connected with a voltage conversion circuit module; according to the utility model, two silicon carbide MOSFETs of an upper bridge arm and a lower bridge arm can be driven at the same time, a power supply and a signal are isolated at the same time, and the robustness of a system is enhanced; in addition, the circuit integrates the functions of bridge arm interlocking, under-voltage locking, desaturation protection, active Miller clamping protection and the like, and the silicon carbide MOSFET is protected from being damaged by accidents to a great extent.

Description

Technical Field

[0001] The utility model belongs to the technical field of power electronic drive, and particularly relates to a silicon carbide MOSFET half-bridge drive protection circuit. Background Art

[0002] As one of the representative products of the third-generation semiconductors, silicon carbide MOSFETs can effectively meet the requirements of high efficiency, miniaturization and light weight of power electronic systems with their excellent performance of high voltage resistance, high temperature resistance, low loss, strong current-carrying capacity and small on-resistance, and are widely used in new energy vehicles, photovoltaic power generation, rail transit, smart grid and other fields. At present, the main products of silicon carbide MOSFETs are concentrated in 650V, 1200V and 1700V, which have very great advantages compared with traditional MOSFETs.

[0003] However, silicon carbide MOSFETs have relatively high requirements for the drive circuit. On the one hand, it is reflected in the drive voltage and drive speed. Generally, the drive voltage range of silicon-based devices is -20V to 20V, the turn-on voltage is 2 - 5V, the drive high and low levels of silicon-based IGBT power devices are 15V / -5V, and the drive high and low levels of silicon-based MOSFETs are 15V / -0V or 15V / -15V. While the drive voltage range of silicon carbide MOSFETs is -6V to 22V. Although its turn-on threshold is only about 2.7V and decreases with the increase of temperature, it can be fully turned on only when the drive reaches 18V to 20V. Therefore, the drive circuits of conventional silicon-based power devices cannot directly drive silicon carbide MOSFETs; in addition, the switching frequency of silicon carbide MOSFETs is relatively high, and the circuit requires sufficient drive speed and drive ability.

[0004] On the other hand, it is required that the drive circuit can detect the abnormal working conditions of silicon carbide MOSFETs and protect them in time. Due to its relatively low turn-on threshold and fast switching speed, silicon carbide MOSFETs have a large dv / dt, which is prone to crosstalk and cause mis-turn-on, further resulting in the direct connection of the upper and lower bridge arms. Therefore, active Miller clamp protection is required to suppress the influence of crosstalk on the circuit. In addition, the drive circuit also requires functions such as bridge arm interlock protection, desaturation protection, undervoltage lockout, etc.

[0005] Based on the above situation, it leads to the relatively large design difficulty, incomplete protection functions and high cost of the silicon carbide MOSFET drive circuit. Summary of the Utility Model

[0006] In order to solve the above technical problems, the utility model provides a silicon carbide MOSFET half-bridge drive protection circuit.

[0007] The utility model is achieved through the following technical solutions.

[0008] A silicon carbide MOSFET half-bridge drive protection circuit provided by the present utility model includes a first drive circuit and a second drive circuit. Both the first drive circuit and the second drive circuit are connected to a voltage conversion circuit module and a bridge arm interlock logic module. The first drive circuit is further connected to a first isolated power supply module, a first drive resistor Rg, and a silicon carbide MOSFET Q1. The second drive circuit is further connected to a second isolated power supply module, a second drive resistor Rg, and a silicon carbide MOSFET Q2. The first isolated power supply module, the second isolated power supply module, and the voltage conversion circuit module are also all connected to a power supply. The bridge arm interlock logic module is further connected to the voltage conversion circuit module and a pulse signal terminal.

[0009] The voltage conversion circuit module includes an LDO linear voltage regulator U3. The IN pin of the LDO linear voltage regulator U3 is connected to one end of a capacitor C15 and the power supply. The Out pin is connected to one end of a capacitor C16. The GND pin is connected to the other ends of the capacitor C15 and the capacitor C16 and then connected to the power supply ground GND.

[0010] The bridge arm interlock logic module includes an AND gate chip U4, an exclusive OR gate chip U5A, and an exclusive OR gate chip U5B.

[0011] The 1st pin of the AND gate chip U4 is connected to one ends of a resistor R1 and a resistor R2. The 2nd pin is connected to one ends of a resistor R3 and a resistor R4. The 4th pin is connected to the 2nd pin of the exclusive OR gate chip U5A and the 1st pin of the exclusive OR gate chip U5B. The 1st pin of the exclusive OR gate chip U5A is connected to the other end of the resistor R2 and one end of a capacitor C17. The 2nd pin of the exclusive OR gate chip U5B is connected to the other end of the resistor R3 and one end of a capacitor C18. One ends of the resistor R1 and the resistor R4 are also respectively connected to a PWM1 signal and a PWM2 signal. The other ends of the resistor R1 and the resistor R4, the 5th pin of the AND gate chip U4, the 5th pin of the exclusive OR gate chip U5A, and the 5th pin of the exclusive OR gate chip U5B are all connected to the Out pin of the LDO linear voltage regulator U3. The other ends of the capacitor C17 and the capacitor C18, the 3rd pin of the AND gate chip U4, the 3rd pin of the exclusive OR gate chip U5A, and the 3rd pin of the exclusive OR gate chip U5B are all connected to the power supply ground GND.

[0012] The first isolated power supply module includes a dedicated driver power supply U1; the Vin pin of the dedicated driver power supply U1 is connected to one ends of capacitors C2 and C3, the positive electrode of electrolytic capacitor C1, and the +15V power supply, and the GND pin is connected to the other ends of capacitors C2 and C3 and the negative electrode of electrolytic capacitor C1 and then connected to the power supply ground GND, the +Vo pin is connected to one ends of capacitors C4 and C5, the -Vo pin is connected to one ends of capacitors C6 and C7, and the 0V pin is connected to the other ends of capacitors C4, C5, C6 and C7 and then connected to the power supply ground PGND_H.

[0013] The second isolated power supply module includes a dedicated driver power supply U2; the Vin pin of the dedicated driver power supply U2 is connected to one ends of capacitors C9 and C10, the positive electrode of electrolytic capacitor C8, and the +15V power supply, and the GND pin is connected to the other ends of capacitors C9 and C10 and the negative electrode of electrolytic capacitor C8 and then connected to the power supply ground GND, the +Vo pin is connected to one ends of capacitors C11 and C12, the -Vo pin is connected to one ends of capacitors C13 and C14, and the 0V pin is connected to the other ends of capacitors C11, C12, C13 and C14 and then connected to the power supply ground PGND_L.

[0014] The first drive circuit includes an isolated drive chip U7, a transient suppression diode D5, high-voltage diodes D1, D2, a voltage regulator diode D3, a diode D4, and capacitors C32, C33;

[0015] The GND1 pin of the isolation drive chip U7 is connected to one end of the capacitor C20 and the power supply ground GND. The IN+ pin is connected to the other end of the capacitor C20 and one end of the resistor R10. The RDY pin is connected to one end of the capacitor C23 and the resistor R9. The FAL_ pin is connected to one end of the capacitor C22 and the resistor R8. The RST pin and the VCC1 pin are both connected to the other ends of the resistor R8 and the resistor R9, one end of the parallel connection of the capacitor C30 and the capacitor C31, and the Out pin of the LDO linear voltage regulator U3. The TEST pin is connected to the other ends of the capacitor C22 and the capacitor C23 and then connected to the power supply ground GND. The VEE2 pin is connected to the -Vo pin of the driver dedicated power supply U1. The CLAMP pin is connected to one end of the resistor R11. The VCC2 pin is connected to the +Vo pin of the driver dedicated power supply U1. The ASC pin is connected to one end of the resistor R17. The GND2 pin is connected to the power ground PGND_H. The other end of the resistor R11 is connected to the power ground PGND_H through the transient suppression diode D5, the resistor R16 and the capacitor C21. The other end of the resistor R11 is also connected to the anode of the diode D4 and the gate of the silicon carbide MOSFET Q1. The cathode of the diode D4 is connected to the +Vo pin of the driver dedicated power supply U1. The other end of the resistor R17 is connected to the power ground PGND_H. The cathode of the zener diode D3 is connected to one end of the capacitor C19 and the resistor R5 and the DESAT pin of the isolation drive chip U7. The other end of the resistor R5 is connected to the anode of the high-voltage diode D1. The cathode of the high-voltage diode D1 is connected to the anode of the high-voltage diode D2. The cathode of the high-voltage diode D2 is connected to the drain of the silicon carbide MOSFET Q1. The anode of the zener diode D3 and the other end of the capacitor C19 are connected to the power ground PGND_H. The other end of the resistor R10 is connected to the 4th pin of the NOR gate chip U5A. One end of the parallel connection of the capacitor C32 and the capacitor C33 is connected to the cathode of the diode D4. The other end is connected to one end of the parallel connection of the capacitor C34 and the capacitor C35 and the power ground PGND_H. The other end of the parallel connection of the capacitor C34 and the capacitor C35 is connected to the VEE2 pin of the isolation drive chip U7.

[0016] The second drive circuit includes an isolation drive chip U8, a transient suppression diode D10, high-voltage diodes D6, D7, a zener diode D8, a diode D9, capacitors C36, C29;

[0017] The GND1 pin of the isolation drive chip U8 is connected to one end of the capacitor C25 and the power supply ground GND. The IN+ pin is connected to the other end of the capacitor C25 and one end of the resistor R19. The RDY pin is connected to one end of the capacitor C28 and the resistor R7. The FAL_ pin is connected to one end of the capacitor C27 and the resistor R6. The RST pin and the VCC1 pin are both connected to the other ends of the resistor R7 and the resistor R6, one end of the parallel connection of the capacitor C30 and the capacitor C31, and the Out pin of the LDO linear voltage regulator U3. The TEST pin is connected to the other ends of the capacitor C27 and the capacitor C28 and then connected to the power supply ground GND. The VEE2 pin is connected to the -Vo pin of the driver dedicated power supply U2. The CLAMP pin is connected to one end of the resistor R20. The VCC2 pin is connected to the +Vo pin of the driver dedicated power supply U2. The ASC pin is connected to one end of the resistor R26. The GND2 pin is connected to the power ground PGND_L. The other end of the resistor R20 is connected to the power ground PGND_L through the transient suppression diode D10, the resistor R25 and the capacitor C26. The other end of the resistor R20 is also connected to the anode of the diode D9 and the gate of the silicon carbide MOSFET Q2. The cathode of the diode D9 is connected to the +Vo pin of the driver dedicated power supply U2. The other end of the resistor R26 is connected to the power ground PGND_L. The cathode of the zener diode D8 is connected to one end of the capacitor C24, the resistor R18 and the DESAT pin of the isolation drive chip U8. The other end of the resistor R18 is connected to the anode of the high-voltage diode D6. The cathode of the high-voltage diode D6 is connected to the anode of the high-voltage diode D7. The cathode of the high-voltage diode D7 is connected to the drain of the silicon carbide MOSFET Q2 and the source of the silicon carbide MOSFET Q1 (whether there is a connection relationship needs to be confirmed with the inventor). The anode of the zener diode D8 and the other end of the capacitor C24 are connected to the power ground PGND_L. The other end of the resistor R19 is connected to the 4th pin of the NOR gate chip U5B. One end of the parallel connection of the capacitor C36 and the capacitor C29 is connected to the cathode of the diode D9. The other end is connected to one end of the parallel connection of the capacitor C37 and the capacitor C38 and the power ground PGND_L. The other end of the parallel connection of the capacitor C37 and the capacitor C38 is connected to the VEE2 pin of the isolation drive chip U8.

[0018] The first drive resistor Rg includes resistors R12, R13, R14, and R15. One end of the parallel connection of the resistor R12 and the resistor R13 is connected to the OUTL pin of the isolation drive chip U7, and the other end is connected to the gate of the silicon carbide MOSFET Q1. One end of the parallel connection of the resistor R14 and the resistor R15 is connected to the OUTH pin of the isolation drive chip U7, and the other end is connected to the gate of the silicon carbide MOSFET Q1.

[0019] The second driving resistor Rg includes resistors R21, R22, R23, and R24; one end of the parallel connection of resistor R21 and resistor R22 is connected to the OUTL pin of the isolated driving chip U8, and the other end is connected to the gate of the silicon carbide MOSFET Q2; one end of the parallel connection of resistor R23 and resistor R24 is connected to the OUTH pin of the isolated driving chip U8, and the other end is connected to the gate of the silicon carbide MOSFET Q2.

[0020] The beneficial effects of the present utility model are as follows: A silicon carbide MOSFET half-bridge driving and protecting circuit of the present utility model can drive two silicon carbide MOSFETs on the upper and lower bridge arms simultaneously, and isolate the power supply and signals at the same time, enhancing the robustness of the system; in addition, the circuit integrates functions such as arm interlock, undervoltage lockout, desaturation protection, and active Miller clamping protection, greatly protecting the silicon carbide MOSFET from damage caused by accidents. Description of the Drawings

[0021] Figure 1 is a schematic structural principle diagram of the present utility model;

[0022] Figure 2 is a circuit schematic diagram of the voltage conversion circuit module of the present utility model;

[0023] Figure 3 is a circuit schematic diagram of the arm interlock logic module of the present utility model;

[0024] Figure 4 is a circuit schematic diagram of the first isolated power supply module and the second isolated power supply module of the present utility model;

[0025] Figure 5 is a circuit schematic diagram of the first driving circuit, the second driving circuit, the first driving resistor, and the second driving resistor of the present utility model. Detailed Embodiment

[0026] The technical solution of the present utility model will be further described below, but the scope of protection claimed is not limited thereto.

[0027] As Figure 1The figure shows a schematic diagram of the structural principle of the present utility model; a silicon carbide MOSFET half-bridge drive protection circuit, including a first drive circuit and a second drive circuit. Both the first drive circuit and the second drive circuit are connected to a voltage conversion circuit module and a bridge arm interlock logic module. The first drive circuit is also connected to a first isolated power supply module, a first drive resistor Rg, and a silicon carbide MOSFET Q1. The second drive circuit is also connected to a second isolated power supply module, a second drive resistor Rg, and a silicon carbide MOSFET Q2. The first isolated power supply module, the second isolated power supply module, and the voltage conversion circuit module are also all connected to a power supply. The bridge arm interlock logic module is also connected to the voltage conversion circuit module and a pulse signal terminal.

[0028] As Figure 2 The figure shows a circuit schematic diagram of the voltage conversion circuit module of the present utility model; the voltage conversion circuit module includes an LDO linear voltage regulator U3. The IN pin of the LDO linear voltage regulator U3 is connected to one end of a capacitor C15 and a power supply. The Out pin is connected to one end of a capacitor C16. The GND pin is connected to the other ends of the capacitor C15 and the capacitor C16 and then connected to the power supply ground GND.

[0029] Specifically, the model of the LDO linear voltage regulator U3 is CJ7805, and its maximum output current is 1A. It can convert a 15V voltage into a 5V voltage to supply power to the primary sides of the isolated drive chip U7 of the first drive circuit and the isolated drive chip U8 of the second drive circuit.

[0030] As Figure 3 The figure shows a circuit schematic diagram of the bridge arm interlock logic module of the present utility model; the bridge arm interlock logic module includes an AND gate chip U4, an exclusive OR gate chip U5A, and an exclusive OR gate chip U5B.

[0031] The 1st pin of the AND gate chip U4 is connected to one ends of a resistor R1 and a resistor R2. The 2nd pin is connected to one ends of a resistor R3 and a resistor R4. The 4th pin is connected to the 2nd pin of the exclusive OR gate chip U5A and the 1st pin of the exclusive OR gate chip U5B. The 1st pin of the exclusive OR gate chip U5A is connected to the other end of the resistor R2 and one end of a capacitor C17. The 2nd pin of the exclusive OR gate chip U5B is connected to the other end of the resistor R3 and one end of a capacitor C18. One ends of the resistor R1 and the resistor R4 are also respectively connected to a PWM1 signal and a PWM2 signal. The other ends of the resistor R1 and the resistor R4, the 5th pin of the AND gate chip U4, the 5th pin of the exclusive OR gate chip U5A, and the 5th pin of the exclusive OR gate chip U5B are all connected to the Out pin of the LDO linear voltage regulator U3. The other ends of the capacitor C17 and the capacitor C18, the 3rd pin of the AND gate chip U4, the 3rd pin of the exclusive OR gate chip U5A, and the 3rd pin of the exclusive OR gate chip U5B are all connected to the power supply ground GND.

[0032] Specifically, the model number of the gate chip U4 is SN74LVC1G32DCKR, and the model numbers of the exclusive-OR gate chips U5A and U5B are NL27WZ86USG;

[0033] Specifically, the gate chip U4, the exclusive-OR gate chip U5A, and the exclusive-OR gate chip U5B are mainly used to form a bridge arm interlock logic module, which can avoid the situation that the PWM1 signal and the PWM2 signal are both at high level due to misoperation or algorithm error, resulting in the simultaneous conduction of the upper and lower bridge arms of the silicon carbide MOSFET and causing the half-bridge to be short-circuited and burned out; where PWM1 and PWM2 are pulse signals, and IN1 and IN2 are the input signals of the isolation drive chip U7 of the first drive circuit and the isolation drive chip U8 of the second drive circuit respectively, and its truth table is shown in Table 1;

[0034] Table 1

[0035]

[0036]

[0037] It can be seen from the truth table that when the PWM1 signal is at high level and the PWM2 signal is at high level, IN1 and IN2 are at low level, effectively avoiding the bridge arm direct connection situation caused by misoperation or algorithm error;

[0038] Specifically, the resistors R1 and R4 are pull-up resistors; the resistors R2 and R3 respectively form low-pass filters with the capacitors C17 and C18 to filter out high-frequency signals in the circuit.

[0039] As Figure 4 shown is the circuit schematic diagram of the first isolation power supply module and the second isolation power supply module of the present invention; the first isolation power supply module includes a dedicated driver power supply U1; the Vin pin of the dedicated driver power supply U1 is connected to one end of the capacitors C2 and C3, the positive electrode of the electrolytic capacitor C1, and the +15V power supply, and the GND pin is connected to the other ends of the capacitors C2 and C3, the negative electrode of the electrolytic capacitor C1 and then connected to the power supply ground GND, the +Vo pin is connected to one end of the capacitors C4 and C5, the -Vo pin is connected to one end of the capacitors C6 and C7, and the 0V pin is connected to the other ends of the capacitors C4, C5, C6, and C7 and then connected to the power supply ground PGND_H;

[0040] The second isolated power supply module includes a dedicated driver power supply U2; the Vin pin of the dedicated driver power supply U2 is connected to one ends of capacitors C9 and C10, the positive electrode of electrolytic capacitor C8, and the +15V power supply. The GND pin is connected to the other ends of capacitors C9 and C10 and the negative electrode of electrolytic capacitor C8, and then connected to the power supply ground GND. The +Vo pin is connected to one ends of capacitors C11 and C12. The -Vo pin is connected to one ends of capacitors C13 and C14. The 0V pin is connected to the other ends of capacitors C11, C12, C13, and C14 and then connected to the power ground PGND_L;

[0041] Specifically, the models of both the dedicated driver power supply U1 and the dedicated driver power supply U2 are QA01C-18, with an output power of 2W and an input voltage of 15V. Through internal isolation, the voltage is converted into VCC (+18V) and VEE (-3.3V) to supply power to the secondary sides of the isolated drive chip U7 of the first drive circuit and the isolated drive chip U8 of the second drive circuit, so as to achieve the ability to drive the silicon carbide MOSFET;

[0042] Specifically, electrolytic capacitors C1 and C8 are used as energy storage capacitors, and capacitors C2, C3, C4, C5, C6, C7, C9, C10, C11, C12, C13, C14, C15, and C16 are used as bypass capacitors to filter out the high-frequency components in the circuit and improve the power purity. The capacitors should be as close as possible to the chip pins to improve power stability, reduce noise, optimize circuit performance, and reduce EMI.

[0043] As Figure 5 shown is the circuit schematic diagram of the first drive circuit, the second drive circuit, the first drive resistor, and the second drive resistor of the present utility model; the first drive circuit includes an isolated drive chip U7, a transient suppression diode D5, high-voltage diodes D1, D2, a voltage regulator diode D3, a diode D4, and capacitors C32, C33;

[0044] The GND1 pin of the isolation drive chip U7 is connected to one end of the capacitor C20 and the power supply ground GND. The IN+ pin is connected to the other end of the capacitor C20 and one end of the resistor R10. The RDY pin is connected to one end of the capacitor C23 and the resistor R9. The FAL_ pin is connected to one end of the capacitor C22 and the resistor R8. The RST pin and the VCC1 pin are both connected to the other ends of the resistor R8 and the resistor R9, one end of the parallel connection of the capacitor C30 and the capacitor C31, and the Out pin of the LDO linear voltage regulator U3. The TEST pin is connected to the other ends of the capacitor C22 and the capacitor C23 and then connected to the power supply ground GND. The VEE2 pin is connected to the -Vo pin of the driver dedicated power supply U1. The CLAMP pin is connected to one end of the resistor R11. The VCC2 pin is connected to the +Vo pin of the driver dedicated power supply U1. The ASC pin is connected to one end of the resistor R17. The GND2 pin is connected to the power ground PGND_H. The other end of the resistor R11 is connected to the power ground PGND_H through the transient suppression diode D5, the resistor R16 and the capacitor C21. The other end of the resistor R11 is also connected to the anode of the diode D4 and the gate of the silicon carbide MOSFET Q1. The cathode of the diode D4 is connected to the +Vo pin of the driver dedicated power supply U1. The other end of the resistor R17 is connected to the power ground PGND_H. The cathode of the zener diode D3 is connected to one end of the capacitor C19 and the resistor R5 and the DESAT pin of the isolation drive chip U7. The other end of the resistor R5 is connected to the anode of the high-voltage diode D1. The cathode of the high-voltage diode D1 is connected to the anode of the high-voltage diode D2. The cathode of the high-voltage diode D2 is connected to the drain of the silicon carbide MOSFET Q1. The anode of the zener diode D3 and the other end of the capacitor C19 are connected to the power ground PGND_H. The other end of the resistor R10 is connected to the 4th pin of the NOR gate chip U5A. One end of the parallel connection of the capacitor C32 and the capacitor C33 is connected to the cathode of the diode D4. The other end is connected to one end of the parallel connection of the capacitor C34 and the capacitor C35 and the power ground PGND_H. The other end of the parallel connection of the capacitor C34 and the capacitor C35 is connected to the VEE2 pin of the isolation drive chip U7.

[0045] The second drive circuit includes an isolation drive chip U8, a transient suppression diode D10, high-voltage diodes D6, D7, a zener diode D8, a diode D9, capacitors D36, D29;

[0046] The GND1 pin of the isolation drive chip U8 is connected to one end of the capacitor C25 and the power supply ground GND. The IN+ pin is connected to the other end of the capacitor C25 and one end of the resistor R19. The RDY pin is connected to one end of the capacitor C28 and the resistor R7. The FAL_ pin is connected to one end of the capacitor C27 and the resistor R6. The RST pin and the VCC1 pin are both connected to the other ends of the resistor R7 and the resistor R6, one end of the parallel connection of the capacitor C30 and the capacitor C31, and the Out pin of the LDO linear voltage regulator U3. The TEST pin is connected to the other ends of the capacitor C27 and the capacitor C28 and then connected to the power supply ground GND. The VEE2 pin is connected to the -Vo pin of the driver dedicated power supply U2. The CLAMP pin is connected to one end of the resistor R20. The VCC2 pin is connected to the +Vo pin of the driver dedicated power supply U2. The ASC pin is connected to one end of the resistor R26. The GND2 pin is connected to the power ground PGND_L. The other end of the resistor R20 is connected to the power ground PGND_L through the transient suppression diode D10, the resistor R25, and the capacitor C26. The other end of the resistor R20 is also connected to the anode of the diode D9 and the gate of the silicon carbide MOSFET Q2. The cathode of the diode D9 is connected to the +Vo pin of the driver dedicated power supply U2. The other end of the resistor R26 is connected to the power ground PGND_L. The cathode of the zener diode D8 is connected to one end of the capacitor C24, the resistor R18, and the DESAT pin of the isolation drive chip U8. The other end of the resistor R18 is connected to the anode of the high-voltage diode D6. The cathode of the high-voltage diode D6 is connected to the anode of the high-voltage diode D7. The cathode of the high-voltage diode D7 is connected to the drain of the silicon carbide MOSFET Q2 and the source of the silicon carbide MOSFET Q1. The anode of the zener diode D8 and the other end of the capacitor C24 are connected to the power ground PGND_L. The other end of the resistor R19 is connected to the 4th pin of the NOR gate chip U5B. One end of the parallel connection of the capacitor C36 and the capacitor C29 is connected to the cathode of the diode D9. The other end is connected to one end of the parallel connection of the capacitor C37 and the capacitor C38 and the power ground PGND_L. The other end of the parallel connection of the capacitor C37 and the capacitor C38 is connected to the VEE2 pin of the isolation drive chip U8.

[0047] Specifically, the model numbers of the isolation drive chip U7 included in the first drive circuit and the isolation drive chip U8 included in the second drive circuit are both NSI6611. The PWM1 and PWM2 signals are respectively input into the isolation drive chip U7 and the isolation drive chip U8 after passing through the bridge arm interlock logic module. While isolating the primary and secondary sides, the isolation drive chip U7 and the isolation drive chip U8 perform level conversion on the signal voltage and have signal driving capabilities, with a maximum sink current and source current ≥ 10A; the rise time and fall time of the signals output by the isolation drive chip U7 and the isolation drive chip U8 are only 50ns under a 10nF load, meeting the switching frequency speed requirements of the silicon carbide MOSFET, and they integrate functions such as undervoltage lockout, desaturation protection, and active Miller clamp protection. In addition, their common-mode immunity ≥ 150kV / us, enhancing the system robustness.

[0048] Specifically, the signals POWER+ and POWER- are the DC bus voltage, and the AC signal is the half-bridge AC output.

[0049] Specifically, the resistors R6 and R7, and R8 and R9 are pull-up resistors, respectively providing high-level outputs for the open-drain outputs of the internal MOS transistors of the isolation drive chip U8 and the isolation drive chip U7;

[0050] Specifically, the resistor R10 and the capacitor C20, and the resistor R19 and the capacitor C25 form low-pass filters to filter out high-frequency signals in the circuit;

[0051] Specifically, the resistors R17 and R16 are current-limiting resistors;

[0052] Specifically, the resistors R11 and R20 respectively constitute active Miller clamp detection circuits, and generally have a value of 0Ω;

[0053] Specifically, the desaturation detection circuit is composed of the zener diode D3, the capacitor C19, the resistor R5, the high-voltage diode D1, and the high-voltage diode D2, and the desaturation detection circuit is composed of the zener diode D8, the capacitor C24, the resistor R18, the high-voltage diode D6, and the high-voltage diode D7, preventing the silicon carbide MOSFET from being damaged due to overcurrent;

[0054] More specifically, the model numbers of the zener diodes D3 and D8 are BZT52C12; the model numbers of the high-voltage diodes D1, D2, D6, and D7 are GS3MB;

[0055] Specifically, the protection circuit for the gate drive signal is composed of the transient voltage suppression diode D5, the ordinary diode D4, the pull-down resistor R16, and the capacitor C21, and the protection circuit for the gate drive signal is composed of the transient voltage suppression diode D10, the ordinary diode D9, the pull-down resistor R25, and the capacitor C26, suppressing signal crosstalk while enhancing system reliability;

[0056] More specifically, the transient voltage suppression diodes D5 and D10 are of the model SMAJ20CA;

[0057] Capacitors C30 and C31 are filter capacitors for the 5V power supply of the drive chip, filtering out the high-frequency components in the circuit;

[0058] Capacitors C32, C33, C34, C35, C36, C29, C37 and C38 are drive energy storage capacitors, which are required to have low parasitic parameters and large capacitance values.

[0059] The first drive resistor Rg includes resistors R12, R13, R14, and R15; one end of the parallel connection of resistor R12 and resistor R13 is connected to the OUTL pin of the isolated drive chip U7, and the other end is connected to the gate of the silicon carbide MOSFET Q1; one end of the parallel connection of resistor R14 and resistor R15 is connected to the OUTH pin of the isolated drive chip U7, and the other end is connected to the gate of the silicon carbide MOSFET Q1;

[0060] The second drive resistor Rg includes resistors R21, R22, R23, and R24; one end of the parallel connection of resistor R21 and resistor R22 is connected to the OUTL pin of the isolated drive chip U8, and the other end is connected to the gate of the silicon carbide MOSFET Q2; one end of the parallel connection of resistor R23 and resistor R24 is connected to the OUTH pin of the isolated drive chip U8, and the other end is connected to the gate of the silicon carbide MOSFET Q2;

[0061] Specifically, resistors R12, R13, R14, R15, R21, R22, R23 and R24 are drive power resistors, which are required to have a power greater than 2W, and generally the package is 1206 or 2512.

[0062] Specifically, the drive signal IN1 and the drive signal IN2 respectively pass through the first drive resistor Rg and the second drive resistor Rg to respectively control the on and off of the silicon carbide MOSFET Q1 and the silicon carbide MOSFET Q2. By respectively changing the resistance values of the first drive resistor Rg and the second drive resistor Rg, the switching speeds of the silicon carbide MOSFET Q1 and the silicon carbide MOSFET Q2 can be changed; if the switching speed is too fast, the risk of mis-conduction will increase, and if the switching speed is too slow, the power consumption will increase. Therefore, it is necessary to balance the effects of the two.

[0063] The beneficial effects of the present utility model are as follows: A silicon carbide MOSFET half-bridge drive and protection circuit of the present utility model can drive two silicon carbide MOSFETs of the upper and lower bridge arms simultaneously, and isolate the power supply and signals at the same time, enhancing the robustness of the system; in addition, this circuit integrates functions such as bridge arm interlock, undervoltage lockout, desaturation protection, and active Miller clamp protection, greatly protecting the silicon carbide MOSFET from damage caused in unexpected situations.

Claims

1. A silicon carbide MOSFET half-bridge drive protection circuit, characterized in that: It includes a first drive circuit and a second drive circuit, wherein the first drive circuit and the second drive circuit are both connected to the voltage conversion circuit module and the bridge arm interlocking logic module, the first drive circuit is also connected to the first isolated power supply module, the first drive resistor Rg and the silicon carbide MOSFET Q1, and the second drive circuit is also connected to the second isolated power supply module, the second drive resistor Rg and the silicon carbide MOSFET Q2; the first isolated power supply module, the second isolated power supply module and the voltage conversion circuit module are also connected to the power supply; the bridge arm interlocking logic module is also connected to the voltage conversion circuit module and the pulse signal terminal.

2. A silicon carbide MOSFET half-bridge drive protection circuit as claimed in claim 1, characterized in that: The voltage conversion circuit module includes an LDO linear regulator U3, an IN pin of the LDO linear regulator U3 is connected to one end of a capacitor C15 and a power supply, an Out pin is connected to one end of a capacitor C16, and a GND pin is connected to the other ends of the capacitors C15 and C16 and then to a power supply ground GND.

3. A silicon carbide MOSFET half-bridge drive protection circuit as claimed in claim 1, characterized in that: The bridge arm interlocking logic module includes an AND gate chip U4, an XOR gate chip U5A and an XOR gate chip U5B; Pin 1 of the AND gate chip U4 is connected to one end of the resistor R1 and the resistor R2, pin 2 is connected to one end of the resistor R3 and the resistor R4, and pin 4 is connected to pin 2 of the XOR gate chip U5A and pin 1 of the XOR gate chip U5B; pin 1 of the XOR gate chip U5A is connected to the other end of the resistor R2 and one end of the capacitor C17; pin 2 of the XOR gate chip U5B is connected to the other end of the resistor R3 and one end of the capacitor C18; one end of the resistor R1 is connected to the resistor R One end of 4 is also connected to PWM1 signal and PWM2 signal respectively; the other end of resistor R1 and resistor R4, pin 5 of AND gate chip U4, pin 5 of XOR gate chip U5A, and pin 5 of XOR gate chip U5B are all connected to the Out pin of LDO linear regulator U3, and the other end of capacitor C17 and capacitor C18, pin 3 of AND gate chip U4, pin 3 of XOR gate chip U5A, and pin 3 of XOR gate chip U5B are all connected to the power supply ground GND.

4. A silicon carbide MOSFET half-bridge drive protection circuit as claimed in claim 1, characterized in that: The first isolated power supply module includes a driver-specific power supply U1; the Vin pin of the driver-specific power supply U1 is connected to one end of capacitor C2 and capacitor C3, the positive electrode of electrolytic capacitor C1, and a +15V power supply, the GND pin is connected to the other end of capacitor C2 and capacitor C3, the negative electrode of electrolytic capacitor C1, and then connected to the power supply ground GND, the +Vo pin is connected to one end of capacitor C4 and capacitor C5, the -Vo pin is connected to one end of capacitor C6 and capacitor C7, and the 0V pin is connected to the other end of capacitor C4, capacitor C5, capacitor C6 and capacitor C7 and then connected to the power ground PGND_H.

5. A silicon carbide MOSFET half-bridge drive protection circuit as claimed in claim 1, characterized in that: The second isolated power supply module includes a driver-specific power supply U2; the Vin pin of the driver-specific power supply U2 is connected to one end of capacitor C9 and capacitor C10, the positive electrode of electrolytic capacitor C8, and a +15V power supply, the GND pin is connected to the other end of capacitor C9 and capacitor C10, the negative electrode of electrolytic capacitor C8, and then connected to the power supply ground GND, the +Vo pin is connected to one end of capacitor C11 and capacitor C12, the -Vo pin is connected to one end of capacitor C13 and capacitor C14, and the 0V pin is connected to the other end of capacitor C11, capacitor C12, capacitor C13, and capacitor C14, and then connected to the power ground PGND_L.

6. A silicon carbide MOSFET half-bridge drive protection circuit as claimed in claim 1, characterized in that: The first driving circuit includes an isolation driving chip U7, a transient suppression diode D5, high-voltage diodes D1 and D2, a voltage regulator D3, a diode D4, and capacitors C32 and C33; The GND1 pin of the isolation driver chip U7 is connected to one end of the capacitor C20 and the power supply ground GND, the IN+ pin is connected to the other end of the capacitor C20 and one end of the resistor R10, the RDY pin is connected to one end of the capacitor C23 and the resistor R9, the FAL_ pin is connected to one end of the capacitor C22 and the resistor R8, the RST pin and the VCC1 pin are connected to the other end of the resistor R8 and the resistor R9, the end of the capacitor C30 and the capacitor C31 connected in parallel, and the Out pin of the LDO linear regulator U3, and the TEST pin is connected to the capacitor C22 and the capacitor C23. The other end is connected to the power supply ground GND, the VEE2 pin is connected to the -Vo pin of the driver dedicated power supply U1, the CLAMP pin is connected to one end of the resistor R11, the VCC2 pin is connected to the +Vo pin of the driver dedicated power supply U1, the ASC pin is connected to one end of the resistor R17, and the GND2 pin is connected to the power ground PGND_H; the other end of the resistor R11 is connected to the power ground PGND_H through the transient suppression diode D5, the resistor R16 and the capacitor C21, and the other end of the resistor R11 is also connected to the anode of the diode D4 and the silicon carbide MOSFET The gate of Q1 is connected, the cathode of diode D4 is connected to the +Vo pin of the driver dedicated power supply U1, and the other end of resistor R17 is connected to the power ground PGND_H; the cathode of the voltage regulator D3 is connected to the capacitor C19 and one end of the resistor R5, and the DESAT pin of the isolation driver chip U7, the other end of the resistor R5 is connected to the anode of the high-voltage diode D1, the cathode of the high-voltage diode D1 is connected to the anode of the high-voltage diode D2, the cathode of the high-voltage diode D2 is connected to the drain of the silicon carbide MOSFET Q1, the anode of the voltage regulator D3 and the other end of the capacitor C19 are connected to the power ground PGND_H; the other end of the resistor R10 is connected to pin 4 of the NOR gate chip U5A; one end of the capacitor C32 and the capacitor C33 connected in parallel is connected to the cathode of the diode D4, and the other end is connected to one end of the capacitor C34 and the capacitor C35 connected in parallel, and the power ground PGND_H, and the other end of the capacitor C34 and the capacitor C35 connected in parallel is connected to the VEE2 pin of the isolation driver chip U7.

7. A silicon carbide MOSFET half-bridge drive protection circuit as claimed in claim 1, characterized in that: The second driving circuit includes an isolation driving chip U8, a transient suppression diode D10, high-voltage diodes D6 and D7, a voltage regulator tube D8, a diode D9, and capacitors C36 and C29; The GND1 pin of the isolation driver chip U8 is connected to one end of the capacitor C25 and the power supply ground GND, the IN+ pin is connected to the other end of the capacitor C25 and one end of the resistor R19, the RDY pin is connected to one end of the capacitor C28 and the resistor R7, the FAL_ pin is connected to one end of the capacitor C27 and the resistor R6, the RST pin and the VCC1 pin are connected to the other end of the resistor R7 and the resistor R6, the end of the capacitor C30 and the capacitor C31 connected in parallel, and the Out pin of the LDO linear regulator U3, and the TEST pin is connected to the capacitor C27 and the capacitor C28. The other end is connected to the power supply ground GND, the VEE2 pin is connected to the -Vo pin of the driver dedicated power supply U2, the CLAMP pin is connected to one end of the resistor R20, the VCC2 pin is connected to the +Vo pin of the driver dedicated power supply U2, the ASC pin is connected to one end of the resistor R26, and the GND2 pin is connected to the power ground PGND_L; the other end of the resistor R20 is connected to the power ground PGND_L through the transient suppression diode D10, the resistor R25 and the capacitor C26, and the other end of the resistor R20 is also connected to the anode of the diode D9 and the silicon carbide MOSFET The gate of Q2 is connected, the cathode of diode D9 is connected to the +Vo pin of the driver dedicated power supply U2, and the other end of resistor R26 is connected to the power ground PGND_L; the cathode of the voltage regulator D8 is connected to the capacitor C24 and one end of the resistor R18, and the DESAT pin of the isolation driver chip U8, the other end of the resistor R18 is connected to the anode of the high-voltage diode D6, the cathode of the high-voltage diode D6 is connected to the anode of the high-voltage diode D7, the cathode of the high-voltage diode D7 is connected to the drain of the silicon carbide MOSFET Q2 and the silicon carbide MOSFET The source of Q1 is connected, the anode of the voltage regulator D8 and the other end of the capacitor C24 are connected to the power ground PGND_L; the other end of the resistor R19 is connected to pin 4 of the NOR gate chip U5B; one end of the capacitor C36 and the capacitor C29 connected in parallel is connected to the cathode of the diode D9, and the other end is connected to one end of the capacitor C37 and the capacitor C38 connected in parallel, and the power ground PGND_L, and the other end of the capacitor C37 and the capacitor C38 connected in parallel is connected to the VEE2 pin of the isolation driver chip U8.

8. A silicon carbide MOSFET half-bridge drive protection circuit as claimed in claim 1, characterized in that: The first driving resistor Rg includes resistors R12, R13, R14, and R15; one end of the resistor R12 and the resistor R13 connected in parallel is connected to the OUTL pin of the isolation driving chip U7, and the other end is connected to the gate of the silicon carbide MOSFET Q1; one end of the resistor R14 and the resistor R15 connected in parallel is connected to the OUTH pin of the isolation driving chip U7, and the other end is connected to the gate of the silicon carbide MOSFET Q1.

9. A silicon carbide MOSFET half-bridge drive protection circuit as claimed in claim 1, characterized in that: The second driving resistor Rg includes resistors R21, R22, R23, and R24; one end of the resistor R21 and the resistor R22 connected in parallel is connected to the OUTL pin of the isolation driving chip U8, and the other end is connected to the gate of the silicon carbide MOSFET Q2; one end of the resistor R23 and the resistor R24 ​​connected in parallel is connected to the OUTH pin of the isolation driving chip U8, and the other end is connected to the gate of the silicon carbide MOSFET Q2.

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