Semiconductor device structure

Abstract

A semiconductor device structure includes a channel region, a first source / drain feature, a gate dielectric layer, and a gate electrode layer. The channel region includes a first channel layer having a first width and a second channel layer disposed below the first channel layer, the second channel layer having a second width greater than the first width. The first source / drain feature has sidewalls in contact with the first channel layer and the second channel layer. A gate dielectric layer is disposed around a plurality of exposed surfaces of each of the first channel layer and the second channel layer. The gate electrode layer is disposed on the gate dielectric layer.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a semiconductor device. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs in which each generation has smaller and more complex circuits than the previous one. In the course of the development of ICs, the functional density (i.e., the number of interconnected devices per wafer area) generally increases, while the geometric size (i.e., the smallest element (or line) that can be created using a manufacturing process) decreases. This process of scaling down generally brings benefits by increasing production efficiency and reducing related costs. This scaling down poses new challenges. For example, transistors using nanowire channels have been proposed to achieve increased device density, greater carrier mobility, and greater drive current in a device. As the device size decreases, continuous improvement in the processing and manufacturing of ICs is required. Summary of the Utility Model

[0003] An object of embodiments of the present disclosure is to provide a semiconductor device structure including a channel region, a first source / drain feature, a gate dielectric layer, and a gate electrode layer. The channel region includes a first channel layer formed of a first material and a second channel layer formed of the first material. The first channel layer has a first width, and the second channel layer is disposed below the first channel layer and has a second width greater than the first width. The first source / drain feature has sidewalls in contact with the first channel layer and the second channel layer. The gate dielectric layer is disposed to surround a plurality of exposed surfaces of each of the first channel layer and the second channel layer. The gate electrode layer is disposed on the gate dielectric layer.

[0004] Another object of embodiments of the present disclosure is to provide a semiconductor device structure including a substrate, a channel region, and a source / drain region. The channel region is longitudinally located on the substrate and includes a bottom first semiconductor layer and a top first semiconductor layer spaced apart from each other, with the top first semiconductor layer above the bottom first semiconductor layer. The source / drain region is located on the substrate and is adjacent to and in contact with the channel region. The bottom first semiconductor layer has a width greater than the width of the top first semiconductor layer.

[0005] An object of an embodiment of the present disclosure is to provide another semiconductor device structure including a substrate, a nanosheet channel region, and source / drain epitaxial features. The nanosheet channel region includes a bottom first semiconductor layer, an intermediate first semiconductor layer, and a top first semiconductor layer that are spaced apart from each other and longitudinally located on the substrate from bottom to top. The source / drain epitaxial features are located on the substrate and are adjacent to and in contact with the nanosheet channel region. The source / drain epitaxial features have a cross-sectional profile that gradually narrows towards the substrate, such that the width of the bottom first semiconductor layer is greater than the width of the intermediate first semiconductor layer, and the width of the intermediate first semiconductor layer is greater than the width of the top first semiconductor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of various features may be arbitrarily increased or decreased.

[0007] Figures 1 to 4 、 Figures 5A to 5C 、 Figures 8A to 8C and Figures 9A to 9C are cross-sectional views of various stages of manufacturing a semiconductor device structure according to some embodiments;

[0008] Figure 6 are various exemplary pulse schemes for an etching process according to some embodiments;

[0009] Figure 7A is an exemplary pulse scheme for an etching process according to some embodiments;

[0010] Figure 7B is an example of ion movement through a pulse scheme according to some embodiments;

[0011] Figure 10 is according to some embodiments of Figure 9C a cross-sectional view of the semiconductor device structure shown and a perspective view of a portion of the semiconductor device structure;

[0012] Figures 11A to 11C are respectively as Figures 9A to 9C an enlarged cross-sectional view of a portion of the semiconductor device structure shown;

[0013] Figure 12 is as Figure 9A an enlarged cross-sectional view of a portion of the semiconductor device structure shown.

[0014] SYMBOL DESCRIPTION

[0015] 100: Semiconductor device structure

[0016] 102: Substrate

[0017] 103: Shallow Trench Isolation

[0018] 104: Semiconductor Layer Stack

[0019] 106: First Semiconductor Layer

[0020] 108: Second Semiconductor Layer

[0021] 110: Etch Stop Layer

[0022] 112: Sacrificial Gate Layer / Sacrificial Gate Structure

[0023] 114,116: Spacer Layer / Gate Spacer

[0024] 144: Inner Spacer / Dielectric Spacer

[0025] 146: Source / Drain (S / D) Epitaxial Feature / Epitaxial Feature

[0026] 146a: First Epitaxial Layer

[0027] 146b: Second Epitaxial Layer

[0028] 162: Contact Etch Stop Layer (CESL)

[0029] 164: Interlayer Dielectric (ILD) Layer

[0030] 170: Void

[0031] 180: Gate Dielectric Layer

[0032] 182: Gate Electrode Layer

[0033] 190: Replacement Gate Structure

[0034] A,B: Ions

[0035] A 1 ,A 1 ',A 2 ,A 2 ',A 3 ,A 3 ',B 1 ,B 1 ',B 2 ,B 2 ',B 3 ,B 3 ',C 1 ,C 1 ',C 2 ,C 2 ',C 3 ,C 3 ': Width

[0036] Bias: Bias power

[0037] Bias1: First bias power

[0038] Bias2: Second bias power

[0039] E1, E2, E3: Length

[0040] H1, H2, H3: Height

[0041] I - I': Line

[0042] R1, R2, R3: Channel resistance

[0043] Source: Source power

[0044] T0: Time point

[0045] X, Y, Z: Direction

[0046] θ 1 , θ 2 : Ion angle Detailed implementation manners

[0047] The following disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific examples of components and arrangements described below are used to simplify the present disclosure. Of course, these are only examples and not intended to limit the present disclosure. For example, in the description, when the first feature is formed above or on the second feature, this may include embodiments where the first feature and the second feature are formed in direct contact, and it may also include embodiments where additional features may be formed between the first feature and the second feature, such that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or words in various examples. This repetition is for the purpose of simplicity and clarity, but does not itself specify the relationship between the various embodiments and / or architectures discussed.

[0048] Furthermore, spatial relative terms may be used herein, such as "beneath", "below", "lower", "above", "upper", etc., to facilitate the description of the relationship between an element or a feature and another (other) element or feature as depicted in the drawings. These spatially relative terms cover not only the directions depicted in the drawings but also different directions in the use or operation of the device. The device may be positioned in different ways (e.g., rotated 90 degrees or in other orientations), and the spatially relative descriptions used herein may have corresponding interpretations.

[0049] The integration of gate-all-around (GAA) nanosheet field-effect transistors (FETs) involves a series of steps, such as forming stacked nanosheets, fin exposure and shallow trench isolation (STI) formation, dummy gate formation, inner spacer and junction formation (where source / drain (S / D) epitaxial layers are selectively formed on either side of the exposed nanosheet ends), and replacement metal gate formation. In 2 nanometer / 3 nanometer / 4 nanometer / 5 nanometer (N2 / N3 / N4 / N5) nanosheet devices, the reduction of channel resistance (R ch ) leads to an increase in current I and improves the device yield. Therefore, the channel geometry or profile and the geometry of the source / drain (S / D) regions play an important role in determining the value of R ch . For example, the shape of the source / drain (S / D) regions can affect the distance and depth of epitaxial growth of adjacent channel pairs. A longer distance between channels and a shallower depth of epitaxial growth may result in an increase in channel resistance (R ch ). The shape of the defined space for forming the source / drain (S / D) regions may also lead to incomplete epitaxial growth, further increasing the channel resistance (R ch ). Therefore, a lower value of current I can be expected. A detailed description of a nanosheet device with improved channel and source / drain (S / D) profiles in a nanosheet device is provided below with reference to the accompanying drawings.

[0050] Although embodiments of the present disclosure discuss nanosheet field-effect transistors (FETs), embodiments of some aspects of the present disclosure can be used in other processes and / or other devices, such as planar field-effect transistors (planar FETs), fin field-effect transistors (FinFETs), horizontal gate all around (HGAA) field-effect transistors (FETs), vertical gate all around (VGAA) field-effect transistors (FETs), and other suitable devices. Those of ordinary skill in the art will readily understand other modifications that may be contemplated within the scope of the present disclosure. In the case of adopting a gate all around (GAA) transistor structure, the gate all around (GAA) transistor structure can be patterned by any suitable method. For example, one or more optical lithography processes (including double patterning processes or multiple patterning processes) can be used to pattern the structure. Generally, double patterning processes or multiple patterning processes combine optical lithography processes with self-alignment processes, thereby allowing the creation of patterns having pitches, for example, smaller than those obtainable using a single, direct optical lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and the sacrificial layer is patterned using an optical lithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the gate all around (GAA) structure.

[0051] Figures 1 to 5C and Figures 8A to 9C illustrate an exemplary process for fabricating a semiconductor device structure 100 in accordance with some embodiments of the present disclosure. It should be understood that for additional embodiments of the method, additional operations may be provided before, during, and after the processes illustrated in Figures 1 to 5C and Figures 8A to 9C and some of the operations described below may be replaced or eliminated. The order of the operations / processes is not restricted and may be interchanged.

[0052] Figures 1 to 5C and Figures 8A to 9C are cross-sectional views of various stages of fabricating a semiconductor device structure 100 along the X-Z plane in accordance with some embodiments. As Figure 1As shown, the semiconductor device structure 100 includes a semiconductor layer stack 104 formed above a substrate 102. The substrate 102 can be a semiconductor substrate. The substrate 102 can include a crystalline semiconductor material, such as but not limited to: silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimonide phosphide (GaSbP), gallium arsenide antimonide (GaAsSb), and indium phosphide (InP). In one embodiment, the substrate 102 is made of silicon. In some embodiments, the substrate 102 is a silicon-on-insulator (SOI) substrate having an insulating layer (not shown) disposed between two silicon layers for enhanced insulation. On the one hand, the insulating layer is an oxygen-containing layer.

[0053] The substrate 102 can include respective regions doped with impurities (e.g., dopants having p-type impurities or n-type impurities). Depending on the circuit design, the dopant can be, for example, boron for p-type field-effect transistors (p-type FETs) and phosphorus for n-type field-effect transistors (n-type FETs).

[0054] The semiconductor layer stack 104 includes a plurality of semiconductor layers made of different materials to facilitate the formation of a plurality of nanosheet channels in a multi-gate device (e.g., a nanosheet field-effect transistor (FETs)). In some embodiments, the semiconductor layer stack 104 includes a plurality of first semiconductor layers 106 and a plurality of second semiconductor layers 108. In some embodiments, the semiconductor layer stack 104 includes a plurality of alternating first semiconductor layers 106 and a plurality of second semiconductor layers 108, and the plurality of first semiconductor layers 106 and the plurality of second semiconductor layers 108 are disposed parallel to each other. The plurality of first semiconductor layers 106 and the plurality of second semiconductor layers 108 are made of a plurality of semiconductor materials having different etch selectivities and / or different oxidation rates. For example, the plurality of first semiconductor layers 106 can be made of silicon (Si), and the plurality of second semiconductor layers 108 can be made of silicon germanium (SiGe). In some examples, the plurality of first semiconductor layers 106 can be made of silicon germanium (SiGe) and the plurality of second semiconductor layers 108 can be made of silicon (Si). In some embodiments, the plurality of first semiconductor layers 106 can be made of silicon germanium (SiGe) having a first germanium (Ge) concentration range, and the plurality of second semiconductor layers 108 can be made of silicon germanium (SiGe) having a second germanium (Ge) concentration range, where the second germanium (Ge) concentration range is less than or greater than the first germanium (Ge) concentration range. In any case, the second semiconductor layer 108 can have a germanium (Ge) concentration in the range of between about 20% and 30%.

[0055] The thicknesses of the plurality of first semiconductor layers 106 and the plurality of second semiconductor layers 108 can vary according to application and / or device performance considerations. In some embodiments, the thickness of each of the plurality of first semiconductor layers 106 and the plurality of second semiconductor layers 108 can be in the range between about 5 nanometers (nm) and about 30 nm. The thickness of each second semiconductor layer 108 can be equal to, less than, or greater than the thickness of the first semiconductor layer 106. In some embodiments, the thickness of each first semiconductor layer 106 is in the range between about 10 nm and about 30 nm, and the thickness of each second semiconductor layer 108 is in the range between about 5 nm and about 20 nm. The plurality of second semiconductor layers 108 can ultimately be removed and the plurality of second semiconductor layers 108 are used to define the vertical distance between adjacent channels of the semiconductor device structure 100.

[0056] The first semiconductor layer 106 or a portion thereof can form the nanosheet channels of the semiconductor device structure 100 in a subsequent manufacturing stage. The term "nanosheet" is used herein to denote any portion of a material having nanoscale (and even microscale) dimensions and having an elongated shape, regardless of the cross-sectional shape of the portion. Thus, the term refers to elongated portions of material having a circular cross-section and a substantially circular cross-section, as well as beam-shaped or rod-shaped portions of material including, for example, a cylindrical or substantially rectangular cross-section. The nanosheet channels of the semiconductor device structure 100 can be surrounded by gate electrodes. The semiconductor device structure 100 can include nanosheet transistors. Nanosheet transistors can be referred to as nanosheet transistors, nanowire transistors, gate-all-around (GAA) transistors, multi-bridge channel (MBC) transistors, or any transistor having a gate electrode surrounding the channel. The use of the first semiconductor layer 106 to define the channels of the semiconductor device structure 100 is further discussed below.

[0057] The first semiconductor layer 106 and the second semiconductor layer 108 are formed by any suitable deposition process, such as epitaxy. For example, epitaxial growth of the plurality of layers of the semiconductor layer stack 104 can be performed by a molecular beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes. Although as Figure 1Shown are three first semiconductor layers 106 and three second semiconductor layers 108 arranged alternately, but it will be understood that any number of first semiconductor layers 106 and second semiconductor layers 108 can be formed in the semiconductor layer stack 104, depending on the predetermined number of nanosheet channels of each field effect transistor (FET). For example, the number of first semiconductor layers 106 (i.e., the number of channels) can be between 2 and 8.

[0058] In Figure 2 , an etch stop layer 110 is formed on the semiconductor layer stack 104, and a sacrificial (dummy) gate layer 112 is deposited on the etch stop layer 110. The sacrificial gate layer 112 can include a sacrificial gate dielectric layer, a sacrificial gate electrode layer, and a mask layer, which are formed by sequentially depositing a blanket layer of sacrificial gate dielectric material, sacrificial gate electrode material, and a mask layer, followed by a patterning process and an etching process. For example, the patterning process includes a lithography process (e.g., optical lithography or electron beam lithography), which may also include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques, and / or combinations thereof. In some embodiments, the etching process can include dry etching (e.g., reactive ion etching (RIE)), wet etching, other etching methods, and / or combinations thereof.

[0059] After patterning the sacrificial gate layer into a plurality of sacrificial gate structures 112, the etch stop layer 110 exposed between adjacent sacrificial gate structures 112 is removed to expose portions of the semiconductor layer stack 104, as Figure 3 shown. The plurality of portions of the semiconductor layer stack 104 covered by the sacrificial gate structures 112 can act as channels of the semiconductor device structure 100 in subsequent processes, while the plurality of exposed portions of the semiconductor layer stack 104 can be removed to define source / drain (S / D) regions, which will be discussed in detail below. In Figure 3 , three sacrificial gate structures 112 are shown. It should be understood that in some embodiments, more sacrificial gate structures 112 can be arranged along the X direction.

[0060] Figure 4 Shown is the formation of gate spacers, which can include depositing conformally a single layer or multiple layers on the exposed surfaces, the exposed surfaces including the sidewalls of the sacrificial gate structures 112 and the top surface of the substrate 102 between adjacent sacrificial gate structures 112. An anisotropic process, such as reactive ion etching (RIE), is performed to remove the conformal layer on the horizontal surfaces, the horizontal surfaces including the top surface of the sacrificial gate structures 112 and the surface in contact with the semiconductor layer stack 104, while retaining the conformal layer deposited on the sidewalls of the sacrificial gate structures 112. In Figure 4In the illustrated embodiment, the gate spacer includes spacer layers 114 and 116. Each of the spacer layers 114 and 116 can be formed by an atomic layer deposition (ALD) process or other suitable process and made of materials such as silicon dioxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride (SiCN), silicon oxycarbide, silicon oxynitride (SiOCN), and / or combinations thereof, or other similar materials.

[0061] In Figures 5A to 5C , the exposed portion of the semiconductor layer stack 104 is removed until the underlying substrate 102 is exposed. In some embodiments, the exposed portion of the semiconductor layer stack 104 is removed to expose a portion of the substrate 102 underlying the semiconductor layer stack 104. In Figures 5A to 5C the illustrated embodiment, the exposed portion of the substrate 102 between adjacent semiconductor layer stacks 104 can also be removed to create a recessed top surface slightly below the contact surface between the substrate 102 and the bottommost layer of the semiconductor layer stack 104 (e.g., the second semiconductor layer 108). The process of removing the exposed portion of the semiconductor layer stack 104 defines the source / drain regions. According to some embodiments, portions of the semiconductor layer stack 104 can be removed by anisotropic dry etching (e.g., anisotropic plasma etching). The etching process determines the profile of the source / drain (S / D) regions and the channels (nanosheets) to be formed in subsequent steps. For example, the dry etching can include plasma etching using an etching gas such as trifluoromethane (CHF 3 ), hydrogen bromide (HBr), or a combination thereof. Dilution gases such as helium (He), argon (Ar), nitrogen (N 2 ) or oxygen (O 2 ) can be used as passivation gases to improve selectivity during the etching process. The etching power can be controlled from about 10 watts (W) to about 4000 W. The etching pressure can be adjusted from about 1 millitorr (mTorr) to about 800 mTorr. The gas flow rate can be from about 20 standard cubic centimeters per minute (sccm) to about 3000 sccm.

[0062] As described above, the geometry or profile of the source / drain (S / D) regions and the nanosheet channels to be formed subsequently can determine the channel resistance R chThe values are used to determine the performance of the semiconductor device (nanosheet device) structure 100. According to some embodiments, anisotropic plasma etching, a method of removing material from a surface using a reactive plasma, is used to etch the semiconductor layer stack 104 with a desired profile. In anisotropic plasma etching, a plasma is generated by applying a high voltage to break down the molecules of the etching gas into constituent atoms and then ionize the atoms. When the ionized atoms, i.e., ions, contact the material on the surface, the material is removed from the surface. In the etching process, a bias power can also be applied to push the ions in a desired direction, such as vertically downward or at an inclined angle downward. Figure 6 Shows various pulse schemes that can be used to perform anisotropic plasma etching and define source / drain (S / D) regions with different profiles. For example, in the synchronous pulse scheme, the source power (Source) for generating the plasma and ions and the bias power (Bias) that can control the movement of the ions are turned on and off synchronously. In the delayed scheme or offset scheme, the on / off states of the source power and the bias power are offset or delayed from each other. In the dual-pulse scheme, one source power and two bias powers (including Bias1 and Bias2) are provided. However, the first bias power (Bias1) and the second bias power (Bias2) are not turned on or off simultaneously at any time during the etching process. That is, only one bias power (Bias1 and Bias2) is on at a time. Therefore, although three powers are provided, it is still a dual-pulse mode because only two powers (including the source power and either of the bias powers) can be on simultaneously. In the hybrid pulse scheme, two powers are used, including the source power and the bias power. However, in each pulse cycle, the source power and the bias power can both be on, one on and the other off, one off and the other on, or both off.

[0063] By selecting an appropriate pulse scheme, the source / drain (S / D) regions can be defined with a desired profile. For example, as Figure 5A shown, the profile can be formed by selecting the dual-pulse scheme, the hybrid pulse scheme, or a combination of these two pulse schemes. The profile of the source / drain (S / D) region as Figure 5B shown can be defined by selecting the synchronous scheme, the delayed scheme, or a combination of these two schemes. The synchronous pulse scheme, the delayed pulse scheme, and the hybrid pulse scheme can be performed using a source power of about 150 W to about 1500 W at 26 megahertz (MHz) and a bias power of about 90 W to about 900 W at about 13 MHz. The dual-pulse scheme can be performed using a source power of about 150 W to about 1500 W at 26 MHz, a first bias power of about 90 W to about 900 W at 13 MHz, and a second bias power of about 10 W to about 150 W at 400 kilohertz (kHz). In Figure 5AAmong them, the width A of the top first semiconductor layer 106 1 is wider than the width A of the middle first semiconductor layer 106 2 and the width A of the middle first semiconductor layer 106 2 is wider than the width A of the bottom first semiconductor layer 106 3 That is, A 1 >A 2 >A 3 . Therefore, the width A of the top part of the space defining the source / drain (S / D) region between adjacent first semiconductor layers 106 1 ' is wider than the width A of the middle part of this space 2 ' and the width A of the middle part of this space 2 ' is wider than the width A of the bottom part of this space 3 ', that is, A 1 '<A 2 '<A 3 . In Figure 5B , the width B of the middle first semiconductor layer 106 2 is wider than the width B of the bottom first semiconductor layer 106 3 while the width B 3 ' of the space between adjacent semiconductor layer stacks 104 is narrower than the width B 2 ' of the middle part of this space. The widths B 2 and B 2 ' can be approximately the same as the widths B 1 and B 1 ' respectively, that is, B 3 <B 1 ~B 2 and B 3 '>B 1 '~B 2 . The difference between A 1 and A 3 and the difference between B 3 and B 1 can be in the range of about 5 nm to about 10 nm. Similarly, the difference between A 1 ' and A 3 ' and between B 3 ' and B 1 ' / B 2 ' can be in the range of about 10 nm to about 5 nm.

[0064] Figure 5C shows the profiles of nanosheets and source / drain (S / D) regions formed subsequently using different pulse patterns according to some embodiments. To form as Figure 5CFor the profile shown, a pulse scheme of applying three pulse powers simultaneously is selected, including the source power (Source), the first bias power (Bias1), and the second bias power (Bias2). For example, as Figure 7A shown, three generators including a source power generator, a first bias power generator, and a second bias power generator are turned on simultaneously to supply the source power, the first bias power, and the second bias power simultaneously at certain stages of the etching process. Power is supplied simultaneously at certain stages of the etching process. For example, the source power (Source), the first bias power (Bias1), and the second bias power (Bias2) are turned on simultaneously and continuously at a later stage of the etching process for removing the bottom portion of the semiconductor layer stack 104 (e.g., at time point T0). As described above, the source power generates ions, and the plurality of ions can remove the semiconductor layer stack 104 in contact therewith. The first bias power (Bias1) and the second bias power (Bias2) are applied to push the ions in a specific direction. For example, the second bias power with a lower frequency tends to push the ions more vertically than the first bias power with a higher frequency. For example, in order to form a profile as Figure 5C shown, a first bias power (Bias1) with a frequency of about 13 MHz and a second bias power (Bias2) with a frequency of about 2,400 kHz or 1.2 MHz can be applied to control the ions towards the semiconductor layer stack 104. The first bias power Bias1 of 13 MHz can be used to push ion "A" at an ion angle θ of about 70° to about 80° with respect to the horizontal line 1 flowing downward, as Figure 7B shown. The second bias power Bias2 with a frequency of about 2,400 kHz or 1.2 MHz can be used to push ion "B" at an ion angle θ of about 90° with respect to the horizontal line 2 flowing downward. By controlling the powers of the first bias power (Bias1) and the second bias power (Bias2), the semiconductor layer stack 104 is allowed to be etched into a tapered profile, as Figure 5C shown.

[0065] According to some embodiments, in order to avoid over-etching the sidewalls of the bottom portion of the semiconductor layer stack 104, that is, to avoid excessive lateral action of the ions, the first bias power (Bias1) is not greater than about 200 W. In order to avoid over-etching of the substrate, the second bias power (Bias2) is at most not higher than 50 W. In some embodiments, the source power is about 150 W to about 1500 W at 26 MHz, the first bias power is about 90 W to about 200 W at 13 MHz, and the second bias power is about 10 W to about 50 W at about 400 kHz or 1.2 MHz. As Figure 7AAs shown, the source power (Source), the first bias power (Bias1), and the second bias power (Bias2) are always on during a certain etching stage. For example, when performing an etching process on the lower part of the semiconductor layer stack 104, the source power (Source), the first bias power (Bias1), and the second bias power (Bias2) are not periodically turned off. Since there is no cleaning operation or vacuum operation during the entire etching stage, the additional gases and by-products generated during the etching process will not be pumped out and will ultimately be deposited on the bottom part of the semiconductor layer stack 104. The additional protection of the deposited by-products further ensures a wider bottom of the semiconductor layer stack 104 after the etching process is performed. In some embodiments, as Figure 7A shown, the pulse scheme can be applied to certain stages of the etching process (e.g., removing the bottom part of the semiconductor layer stack 104), while other stages of the etching process (e.g., removing the upper part of the semiconductor layer stack 104) can be performed by using other pulse schemes (e.g., any one or more of the pulse schemes as Figure 6 shown).

[0066] Thus, a tapered profile of the nanosheet as Figure 5C shown can be formed, i.e., a width that gradually increases from the top to the bottom. As Figure 5C shown, the width C of the bottom first semiconductor layer 106 3 is greater than the width C of the middle first semiconductor layer 106 2 , and the width C of the middle first semiconductor layer 106 2 is greater than the width C of the top first semiconductor layer 106 1 , i.e., C 3 > C 2 > C 1 . Therefore, the width C 3 ' of the bottom part of the space for forming the source / drain (S / D) regions in subsequent processing steps is less than the width C 2 ' of the middle part of this space, and the width C 2 ' of the middle part of this space is less than the width C 1 ' of the top part of this space, i.e., C 3 '< C 2 '< C 1 '. According to some embodiments, the difference between C 3 and C 1 can range from about 5 nm to about 10 nm, while the difference between C 3 ' and C 1 ' can range from 10 nm to about 5 nm.

[0067] During Figures 8A to 8CIn [description], an edge portion of each second semiconductor layer 108 of the semiconductor layer stack 104 is horizontally removed along the X direction. The edge portion of the second semiconductor layer 108 is removed to form a cavity. In some embodiments, a plurality of portions of the second semiconductor layer 108 are removed by a selective wet etching process. When the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of silicon and / or SiGe (i.e., the first semiconductor layer 106 has a lower germanium concentration than the second semiconductor layer 108), a wet etchant can be used to selectively etch the second semiconductor layer 108. The wet etchant is, for example but not limited to, ammonium hydroxide (NH 4 OH), tetramethylammonium hydroxide (TMAH), ethylenediaminepyrocatechol (EDP), or potassium hydroxide (KOH) solution.

[0068] After removing the edge portion of each second semiconductor layer 108, a dielectric layer is deposited in the cavity to form an internal spacer 144. The internal spacer 144 can be made of silicon oxynitride (SiON), SiCN, silicon oxycarbide (SiOC), SiOCN, or silicon nitride (SiN). The formation of the internal spacer 144 can first form a conformal dielectric layer by using a conformal deposition process such as ALD, and then perform anisotropic etching to remove portions of the conformal dielectric layer other than the internal spacer 144. During the anisotropic etching process, the internal spacer 144 is protected by the first semiconductor layer 106. The remaining second semiconductor layers 108 cover between the dielectric spacers 144 along the X direction.

[0069] In Figures 8A to 8C [description], source / drain (S / D) epitaxial features 146 are formed in the space defined for forming source / drain (S / D) regions between adjacent semiconductor layer stacks 104. Figures 8A to 8C Respectively shown based on Figures 8A to 8CManufacturing stages of the semiconductor device structure 100 of the illustrated embodiment. The source / drain (S / D) epitaxial features 146 can be formed by any suitable process, such as a cyclic deposition etch (CDE) epitaxy process, a selective etch growth (SEG) process, ALD, molecular beam epitaxy (MBE), or any combination thereof. One of the pair of source / drain (S / D) epitaxial features 146 can be a source region located on one side of the semiconductor layer stack 104, and the other of the pair of source / drain (S / D) epitaxial features 146 can be a drain region located on the other side of the semiconductor layer stack 104. The pair of source / drain (S / D) epitaxial features 146 includes a source epitaxial feature 146 and a drain epitaxial feature 146 connected by subsequently forming a channel from the first semiconductor layer 106. In the present utility model, the source and the drain can be used interchangeably, and their structures are substantially the same.

[0070] Each epitaxial feature 146 can include multiple layers or multiple portions formed from the bottom to the top of a plurality of spaces for forming the source / drain (S / D) regions. In some embodiments, the epitaxial feature 146 can include a first epitaxial layer 146a formed on the exposed portion of the substrate 102 and a second epitaxial layer 146b formed on the first epitaxial layer 146a. The first epitaxial layer 146a can include a semiconductor material such as Si, silicon phosphide (SiP), silicon carbide (SiC), silicon arsenide (SiAs), silicon carbon phosphide (SiCP), SiGe, or Ge. In some embodiments, the first epitaxial layer 146a is formed of undoped silicon. In some embodiments, the first epitaxial layer 146a is formed of undoped silicon germanium. That is, the first epitaxial layer 146a does not include a dopant. The first epitaxial layer 146a without a dopant avoids possible dopant diffusion into the region of the substrate 102 located under and adjacent to the sacrificial gate structure 112 and between the source / drain (S / D) epitaxial features 146.

[0071] Optionally, an intermediate epitaxial layer (not shown in the figures) may be conformally formed on the first epitaxial layer 146a and in contact with the first semiconductor layer 106 and the dielectric spacer 144. In some embodiments, the intermediate epitaxial layer may include the same material as the first epitaxial layer 146a and have a higher dopant concentration. In some embodiments, the intermediate epitaxial layer is formed of silicon germanium, and the Ge concentration ranges between about 25% and 40%. Depending on the conductivity type of the device to be formed thereon, the intermediate epitaxial layer may have an n-type dopant or a p-type dopant. The intermediate epitaxial layer serves as a drain resistance layer to prevent possible diffusion of subsequent backside metallization elements into the gate region. The intermediate epitaxial layer may also serve as a lattice transitional layer between the first epitaxial layer 146a and the second epitaxial layer 146b. In some embodiments, the intermediate epitaxial layer is a boron-rich layer. In such a case, the intermediate epitaxial layer contains boron and the dopant concentration ranges between about 1E20 atoms / cm 3 ) and about 8E20 atoms / cm 3 . In some embodiments, the intermediate epitaxial layer contains phosphorus and the dopant concentration ranges between about 1E20 atoms / cm 3 and about 5E20 atoms / cm 3 .

[0072] The second epitaxial layer 146b is formed on the first epitaxial layer 146a (or the intermediate epitaxial layer, if used) and has at least sidewalls surrounded by the first epitaxial layer 146a. In some embodiments, at least three surfaces of the second epitaxial layer 146b are in contact with the first epitaxial layer 146a. The second epitaxial layer 146b forms the main part of the source / drain (S / D) epitaxial feature 146. Similarly, the second epitaxial layer 146b may be a semiconductor material such as Si, SiP, SiC, SiAs, SiCP, SiGe, or Ge. In some embodiments, the second epitaxial layer 146b may include the same material as the first epitaxial layer 146a. In some embodiments, the second epitaxial layer 146b is formed of silicon germanium, and the Ge concentration ranges between about 50% and 60%. Depending on the conductivity type of the device to be formed thereon, the second epitaxial layer 146b may have an n-type dopant or a p-type dopant. In either case, the dopant concentration of the second epitaxial layer 146b is higher than that of the first epitaxial layer 146a. The higher dopant concentration of the second epitaxial layer 146b can reduce the contact resistance of the epitaxial source / drain (S / D) feature and provide better conductivity for the source / drain metal contacts to be formed in subsequent process steps. In some embodiments, the second epitaxial layer 146b contains boron and the dopant concentration is about 8E20 atoms / cm 3Between about 3E21 atoms / cm 3 In some embodiments, the second epitaxial layer 146b contains phosphorus and the dopant concentration is between about 5E20 atoms / cm 3 And about 4E21 atoms / cm 3 In the range between.

[0073] After forming the source / drain (S / D) epitaxial features 146, a contact etch stop layer (CESL) 162 is conformally formed on the exposed surface of the semiconductor device structure 100. The contact etch stop layer (CESL) 162 covers the exposed surfaces of the source / drain (S / D) epitaxial features 146 and the gate spacers 116. The contact etch stop layer (CESL) 162 may include an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbonitride, silicon oxynitride, carbon nitride, silicon oxide, silicon carbon oxide, etc. or a combination thereof, and may be formed by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), ALD or any suitable deposition technique. Next, an interlayer dielectric (ILD) layer 164 is formed on the contact etch stop layer (CESL) 162 above the semiconductor device structure 100. The material of the interlayer dielectric (ILD) layer 164 may include an oxide formed with tetraethylorthosilicate (TEOS), undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG) and / or other suitable dielectric materials containing Si, O, C and / or H. The interlayer dielectric (ILD) layer 164 may be deposited by a PECVD process or other suitable deposition techniques. In some embodiments, after forming the interlayer dielectric (ILD) layer 164, the semiconductor device structure 100 may be heat treated to anneal the interlayer dielectric (ILD) layer 164. A planarization operation such as chemical mechanical planarization (CMP) is performed on the semiconductor device structure 100 to remove a portion of the thickness of the interlayer dielectric (ILD) layer 164, a portion of the contact etch stop layer (CESL) 162, and a portion of a mask layer (not shown in the figure) until the sacrificial gate structure 112 is exposed.

[0074] At Figures 9A to 9CIn [the structure], the sacrificial gate structure 112 and the second semiconductor layer 108 are removed. Plasma dry etching and / or wet etching can be used to remove the sacrificial gate structure 112. The sacrificial gate structure 112 and the second semiconductor layer 108 can be removed by any suitable process, such as dry etching, wet etching, or a combination thereof. Subsequently, the etch stop layer 110 is removed, which can also be performed by any suitable process, such as dry etching, wet etching, or a combination thereof. In some embodiments, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution can be used to selectively remove the sacrificial gate structure 112 without removing the gate spacers 114, the interlayer dielectric (ILD) layer 164, and the contact etch stop layer (CESL) 162.

[0075] The removal of the sacrificial gate structure 112 and the second semiconductor layer 108 is used to expose the inner spacers 144 and the first semiconductor layer 106 and to form a plurality of openings between the gate spacers 116 and between the first semiconductor layer 106. The removal process can be any suitable etching process, such as dry etching, wet etching, or a combination thereof. The etching process can be a selective etching process that removes the second semiconductor layer 108 without removing the gate spacers 114 and 116, the interlayer dielectric (ILD) layer 164, the contact etch stop layer (CESL) 162, the inner spacers 144, and the first semiconductor layer 106.

[0076] After the sacrificial gate structure 112 and the second semiconductor layer 108, an alternative gate structure 190 is formed. Each alternative gate structure 190 can include a gate dielectric layer 180 and a gate electrode layer 182. In some embodiments, an interfacial layer (IL) (not shown in the figure) can be formed on the exposed surface of the first semiconductor layer 106. The interfacial layer (IL) can include an oxide, a nitride, and / or a dielectric layer or the interfacial layer (IL) can be formed of an oxide, a nitride, and / or a dielectric layer. The above-mentioned oxide (e.g., silicon oxide) is formed by thermal oxidation or chemical oxidation of the first semiconductor layer 106. The above-mentioned nitride is, for example, silicon nitride, silicon oxynitride, nitrogen oxide, etc. The above-mentioned dielectric layer is, for example, hafnium silicate. The interfacial layer (IL) can be formed by CVD, ALD, a cleaning process, or any suitable process. Next, the gate dielectric layer 180 is formed on the exposed surface of the semiconductor device structure 100 (e.g., on the interfacial layer (IL) (if present), on the sidewalls of the gate spacers 116, on the top surface of the interlayer dielectric (ILD) layer 164, on the top surface of the contact etch stop layer (CESL) 162, on the top surface of the dielectric spacers 144). The gate dielectric layer 180 can include a high-k dielectric material or be made of a high-k dielectric material. The high-k dielectric material is, for example, hafnium dioxide (HfO 2) hafnium silicate (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), hafnium zirconium oxide (HfZrO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), lanthanum oxide (LaO), aluminum oxide (AlO), aluminum silicon oxide (AlSiO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta 2 O 5 ), yttrium oxide (Y 2 O 3 ), silicon oxynitride (SiON), or other suitable high-k materials. The gate dielectric layer 180 can be a conformal layer formed by a conformal process such as an ALD process, a PECVD process, a molecular beam deposition (MBD) process, etc., or a combination thereof. The gate dielectric layer 180 can have a thickness in the range of about 0.3 nm to about 5 nm.

[0077] After forming the gate dielectric layer 180, a gate electrode layer 182 is formed on the gate dielectric layer 180. The gate electrode layer 182 fills a plurality of openings formed by removing the sacrificial gate structure 112 and the second semiconductor layer 108, and the gate electrode layer 182 surrounds a portion of each first semiconductor layer 106. The gate electrode layer 182 includes one or more layers of conductive materials, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, titanium nitride (TiN), tungsten nitride (WN), tungsten carbonitride (WCN), titanium aluminide (TiAl), titanium tantalum nitride (TiTaN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum carbonitride (TaCN), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), metal alloys, other suitable materials, and / or combinations thereof. The gate electrode layer 182 can be formed by PVD, CVD, ALD, electroplating, or other suitable methods. In some embodiments, one or more optional conformal layers (not shown in the figures) can be conformally (and sequentially, if more than one layer) deposited between the gate dielectric layer 180 and the gate electrode layer 182. One or more optional conformal layers can include one or more barrier layers and / or capping layers and one or more work function adjustment layers. One or more barrier layers and / or capping layers can include or can be nitrides of tantalum and / or titanium, silicon nitrides of tantalum and / or titanium, carbonitrides of tantalum and / or titanium, and / or aluminum nitrides of tantalum and / or titanium, nitrides of tungsten, carbonitrides of tungsten, and / or carbides of tungsten, etc., or combinations thereof. One or more work function adjustment layers can include or can be nitrides of titanium and / or tantalum, silicon nitrides of titanium and / or tantalum, carbonitrides of titanium and / or tantalum, aluminum nitrides of titanium and / or tantalum, aluminum oxides of titanium and / or tantalum, and / or aluminum carbides of titanium and / or tantalum, nitrides of tungsten, carbonitrides of tungsten, and / or carbides of tungsten, cobalt, platinum, etc., or combinations thereof.

[0078] The top surfaces of the partial gate electrode layer 182, the partial one or more optional conformal layers (if any), and the interlayer dielectric (ILD) layer 164, above the top surface of the contact etch stop layer (CESL) 162 and above the top surfaces of the gate spacers 114 / 116, can be removed by a planarization process (e.g., by a CMP process). The resulting structure of the semiconductor device structure 100 can be referred to a cross-sectional view in the (a) x-z plane and (b) a perspective view of a block of the semiconductor device structure 100 cut along the line I-I' in (a) and looking in the direction indicated by the arrows at the top and bottom of the portion (b). As Figure 10 shown, the semiconductor device structure 10 may include shallow trench isolations (STI) 103 that have been previously formed in the substrate 102. The shallow trench isolations 103 have been formed in the substrate 102 before forming the respective portions such as channels, gates, source / drain (S / D) regions, and other features. Figure 10 are respectively enlarged cross-sectional views of the bottom portion of the semiconductor device structure 100 enclosed by the dashed lines as

[0079] Figures 11A to 11C shown. The tapered source / drain (S / D) regions produce a notching profile as Figures 9A to 9C shown. The tapered profile of the stack of channels, i.e., the gradually widening profile, as Figure 11A shown, can be referred to as a foot profile. The epitaxial space, i.e., the lateral space for the epitaxial features 146 that can grow between an adjacent pair of channels, is respectively denoted as Figure 11C E1, E2, and E3 of the notching profile, bowing profile, and foot profile in Figures 11A to 11C with the relationship of E1>E2>E3. The maximum height of the horizontal epitaxial features 146 from the first epitaxial layer 146a to the bottom side of the bottommost channel (i.e., the first semiconductor layer 106) is respectively denoted as H1, H2, and H3 for the notching profile, bowing profile, and foot profile, with the relationship of H1<H2<H3. In some embodiments, H1 ranges from about 3 nm to about 5 nm, H2 ranges from about 5 nm to about 10 nm, and H3 ranges from about 10 nm to about 20 nm. According to the relationships of E1, E2, E3, H1, H2, and H3, the channel resistances R ch of the notching profile, bowing profile, and foot profile are respectively denoted as R1, R2, and R3, with the relationship of R1≥R2>R3.

[0080] In addition to the longer epitaxial lengths E1, E2 and the smaller heights H1, H2 resulting in higher channel resistances R1 and R2, the narrower bottom portion of the space for epitaxial growth may further increase the channel resistances R1 and R2 due to incomplete epitaxial growth. For example, a structure with a notch profile as shown in Figure 9A has a narrower space for epitaxial growth in the upper portion than in the bottom portion. Since the space for the second epitaxial layer 146b to be filled in the upper portion is smaller, the upper portion can be completely filled before the space in the bottom portion is completely filled. That is, early merge may occur in the upper portion of the space and prevent the second epitaxial layer 146b from growing continuously at the bottom portion of the space. As a result, voids 170 as shown in Figure 12 can be formed. The generation of voids 170 may disrupt the connection between adjacent channels or result in a longer conductive path extending along the voids to connect adjacent channels. Since resistance is inversely proportional to distance, the voids further increase the value of the channel resistance R1. The channel resistance R2 of the bow-shaped profile may also increase due to the same problem. In contrast, a profile that tapers towards the bottom as shown in Figure 9C allows the narrower lower portion of the space to be merged or completely filled before the wider upper portion of the space can be merged. This prevents the formation of voids caused by early merge in the upper portion. As a result, the conductive path does not become longer and cause an increase in the channel resistance R3.

[0081] During sheet formation (SHF), i.e., during the formation of channels, the second semiconductor layer 108 made of SiGe is removed to create an opening. Then the opening is filled with a metal such as the material used to form the gate electrode layer 182, as shown in Figures 9A to 9C , Figure 10 and Figures 11A to 11C . Since a higher concentration of Ge in SiGe may result in easier lateral etching, in order to further assist in forming the tapered or foot profile of the channel region as shown in Figure 11C , the bottom second semiconductor layer 108 can be formed with a higher Ge concentration compared to the upper second semiconductor layer 108. For example, the bottom second semiconductor layer 108 can have a Ge concentration of about 35% to about 45%, the middle second semiconductor layer 108 can have a Ge concentration of about 25% to about 35%, and the top second semiconductor layer 108 can have a Ge concentration of about 15% to about 25%. Therefore, the etching time for the upper portion is longer than that for the bottom portion.

[0082] According to one embodiment, a method of forming a nanosheet field effect transistor (FET) is provided. A plurality of first semiconductor layers and a plurality of second semiconductor layers are alternately formed on a substrate. The alternately formed plurality of first semiconductor layers and the plurality of second semiconductor layers are patterned into a plurality of semiconductor layer stacks, the plurality of semiconductor layer stacks being spaced apart from each other in a space along a direction, and each semiconductor layer stack having a cross-sectional profile that gradually widens towards the substrate along the direction. An epitaxial feature is formed in the space. The patterned plurality of second semiconductor layers are removed from each semiconductor layer stack. The method further includes patterning the plurality of semiconductor layer stacks using a plasma etching process. The patterning process may include an etching process that simultaneously applies source power, a first bias power, and a second bias power.

[0083] In some embodiments, the source power is higher than the first bias power, and the first bias power is higher than the second bias power. The source power can be controlled at a first power level to generate a plurality of ions from an etching gas, the first bias power can be controlled at a second power level to push the plurality of ions downward at a first ion angle relative to a horizontal line, and the second bias power can be controlled at a third power level to push the plurality of ions downward at a second ion angle relative to the horizontal line. The first ion angle is about 70° to about 80° and the second ion angle is about 90°. To pattern the plurality of semiconductor layer stacks, the upper portion of the semiconductor layer stack is etched by a first pulse scheme; and the lower portion of the semiconductor layer stack is etched by a second pulse scheme different from the first pulse scheme. The second pulse scheme may include continuously applying source power, the first bias power, and the second bias power without evacuating additional gas and additional by-products.

[0084] In some embodiments, the above method may further include alternately forming a plurality of silicon layers and a plurality of silicon germanium layers on the substrate to form a semiconductor layer stack, wherein the silicon germanium layer has a gradually decreasing germanium concentration from the bottom silicon germanium layer towards the top silicon germanium layer. Before patterning the plurality of first semiconductor layers and the plurality of second semiconductor layers, a plurality of sacrificial gate structures are formed on the plurality of first semiconductor layers and the plurality of second semiconductor layers. Conformal spacers are formed on the sidewalls of each sacrificial gate structure. The semiconductor layer stack exposed between the sacrificial gate structures is removed by patterning the semiconductor layer stack.

[0085] According to some embodiments, a method for forming a void-free source / drain region is provided. The method includes etching a semiconductor layer stack on a substrate to form a space exposing the substrate, the space having a cross-sectional profile that tapers towards the substrate; forming a first epitaxial layer at the bottom of the space; and forming a second epitaxial layer on the first epitaxial layer in the space. The space having a tapered cross-sectional profile is achieved by performing an etching process using a pulse scheme that simultaneously uses a source power, a first bias power, and a second bias power. The second bias power is less than the first bias power, and the first bias power is less than the source power. The source power has a first power level and a first frequency to generate a plurality of ions from an etching gas, the first bias power has a second power level and a second frequency to push the plurality of ions downward at a first ion angle relative to a horizontal line, and the second bias power has a third power level and a third frequency to push the plurality of ions downward at a second ion angle relative to the horizontal line. During the etching process, the source power, the first bias power, and the second bias power are continuously applied without pumping out additional gas and additional plural by-products. In some embodiments, a plurality of silicon layers and a plurality of silicon-germanium layers are alternately formed on the substrate to form a semiconductor layer stack, and the silicon-germanium layers have a germanium concentration that gradually decreases from a bottom silicon-germanium layer towards a top silicon-germanium layer.

[0086] According to some embodiments, a semiconductor device structure includes a channel region, a first source / drain feature, a gate dielectric layer, and a gate electrode layer. The channel region includes a first channel layer formed of a first material and a second channel layer formed of the first material, the first channel layer having a first width, the second channel layer being disposed below the first channel layer and having a second width greater than the first width. The first source / drain feature has sidewalls in contact with the first channel layer and the second channel layer. The gate dielectric layer is disposed to surround a plurality of exposed surfaces of each of the first channel layer and the second channel layer. The gate electrode layer is disposed on the gate dielectric layer. According to some embodiments, the structure further includes a third channel layer disposed below the second channel layer and having a third width greater than the second width. In some embodiments, the channel region further includes a plurality of additional channel layers disposed below the second channel layer, and the widths of the additional channel layers gradually decrease from the second width. The source / drain feature has a profile that tapers from the top level of the first channel layer horizontally to the bottom level of the second channel layer.

[0087] According to some embodiments, a semiconductor device structure is provided that includes a substrate, a channel region, and source / drain regions. The channel region is longitudinally located on the substrate and includes a bottom first semiconductor layer and a top first semiconductor layer that are spaced apart from each other, with the top first semiconductor layer located above the bottom first semiconductor layer. The source / drain regions are located on the substrate and are adjacent to and in contact with the channel region. The bottom first semiconductor layer has a width greater than that of the top first semiconductor layer. In some embodiments, the source / drain regions include a first epitaxial layer and a second epitaxial layer. The first epitaxial layer is located on the substrate, and the second epitaxial layer is located on the first epitaxial layer and has sidewalls that are at least surrounded by the first epitaxial layer. In some embodiments, the channel region further includes an intermediate first semiconductor layer located between the bottom first semiconductor layer and the top first semiconductor layer. The bottom first semiconductor layer has a width greater than that of the intermediate first semiconductor layer, and the intermediate first semiconductor layer has a width greater than that of the top first semiconductor layer. In some embodiments, the semiconductor device structure further includes a gate dielectric layer and a gate electrode layer. The gate dielectric layer is disposed to surround a plurality of exposed surfaces of the bottom first semiconductor layer and the top first semiconductor layer. The gate electrode layer is disposed on the gate dielectric layer.

[0088] According to some embodiments, a semiconductor device structure is provided that includes a substrate, a nanosheet channel region, and source / drain epitaxial features. The nanosheet channel region includes a bottom first semiconductor layer, an intermediate first semiconductor layer, and a top first semiconductor layer that are spaced apart from each other and are longitudinally located on the substrate from bottom to top. The source / drain epitaxial features are located on the substrate and are adjacent to and in contact with the nanosheet channel region. The source / drain epitaxial features have a cross-sectional profile that tapers gradually towards the substrate, such that the bottom first semiconductor layer has a width greater than that of the intermediate first semiconductor layer, and the intermediate first semiconductor layer has a width greater than that of the top first semiconductor layer. In some embodiments, the semiconductor device structure further includes a gate dielectric layer and a gate electrode layer. The gate dielectric layer is disposed to surround a plurality of exposed surfaces of the bottom first semiconductor layer, the intermediate first semiconductor layer, and the top first semiconductor layer. The gate electrode layer is disposed on the gate dielectric layer.

[0089] The features of several embodiments are outlined above, so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis to design or modify other processes and structures to achieve the same objectives and / or advantages as those introduced in these embodiments. Those skilled in the art should also understand that these equivalent constructs do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions, and variations without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device structure, characterized in that: include: A channel area, including: a first channel layer, wherein the first channel layer has a first width; and a second channel layer disposed below the first channel layer, wherein the second channel layer has a second width greater than the first width; a first source / drain feature having a sidewall in contact with the first channel layer and the second channel layer; a gate dielectric layer disposed around a plurality of exposed surfaces of each of the first channel layer and the second channel layer; and A gate electrode layer is disposed on the gate dielectric layer.

2. The semiconductor device structure according to claim 1, wherein: Also includes: A third channel layer is disposed below the second channel layer, wherein the third channel layer has a third width greater than the second width.

3. The semiconductor device structure according to claim 2, wherein: The channel region further includes a plurality of additional channel layers disposed below the second channel layer, wherein the widths of the plurality of additional channel layers gradually decrease from the second width.

4. The semiconductor device structure according to claim 2, wherein: The source / drain feature has a profile that gradually narrows from a top level of the first channel layer to a bottom level of the second channel layer.

5. A semiconductor device structure, characterized in that: include: a substrate; a channel region vertically disposed on the substrate, wherein the channel region includes a bottom first semiconductor layer and a top first semiconductor layer that are separated from each other; and a source / drain region located on the substrate and adjacent to and in contact with the channel region; The width of the bottom first semiconductor layer is greater than the width of the top first semiconductor layer.

6. The semiconductor device structure according to claim 5, wherein: The source / drain region includes a first epitaxial layer and a second epitaxial layer. The first epitaxial layer is located on the substrate, and the second epitaxial layer is located on the first epitaxial layer and at least has a sidewall surrounded by the first epitaxial layer.

7. The semiconductor device structure according to claim 5, wherein: The channel area also includes: a middle first semiconductor layer, located between the bottom first semiconductor layer and the top first semiconductor layer, The width of the bottom first semiconductor layer is greater than the width of the middle first semiconductor layer, and the width of the middle first semiconductor layer is greater than the width of the top first semiconductor layer.

8. The semiconductor device structure according to claim 5, wherein: Also includes: a gate dielectric layer disposed around the exposed surfaces of the bottom first semiconductor layer and the top first semiconductor layer; and A gate electrode layer is disposed on the gate dielectric layer.

9. A semiconductor device structure, characterized in that: include: a substrate; A nanosheet channel region, comprising a bottom first semiconductor layer, a middle first semiconductor layer and a top first semiconductor layer, which are separated from each other and vertically located from bottom to top on the substrate; and a source / drain epitaxial feature located on the substrate adjacent to and in contact with the nanosheet channel region, The source / drain epitaxial feature has a cross-sectional profile that gradually narrows toward the substrate, so that the width of the bottom first semiconductor layer is greater than the width of the middle first semiconductor layer and the width of the middle first semiconductor layer is greater than the width of the top first semiconductor layer.

10. The semiconductor device structure according to claim 9, wherein: Also includes: a gate dielectric layer disposed around the exposed surfaces of the bottom first semiconductor layer, the middle first semiconductor layer, and the top first semiconductor layer; and A gate electrode layer is disposed on the gate dielectric layer.

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