Semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device includes a plurality of semiconductor layers vertically separated from each other; a gate structure including a lower portion and an upper portion, wherein the lower portion encapsulates each of the semiconductor layers; and a plurality of diffusion cap layers disposed between the semiconductor layer and the gate structure and separating the semiconductor layer and the gate structure. In some embodiments, the diffusion cap layer acts as a diffusion barrier for the semiconductor layer.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] The semiconductor integrated circuit (IC) industry has been growing rapidly in recent years. Technological advancements in integrated circuit materials and design have led to the continuous evolution of integrated circuit generations. With the emergence of each new generation of products, the circuits have become smaller and more complex than the previous generation, thereby having a higher functional density (i.e., the number of interconnect devices that can be provided per wafer area) and smaller geometric dimensions (i.e., the smallest elements or lines that can be formed using a manufacturing process). This scaling process is beneficial for improving production efficiency and reducing associated costs. However, as the feature size continues to shrink, the manufacturing process becomes more challenging and it becomes increasingly difficult to ensure the reliability of semiconductor devices. Therefore, the industry continuously faces the challenge of developing processes that can form smaller and more reliable integrated circuits. Summary of the Utility Model

[0003] The present disclosure provides a semiconductor device, including a plurality of semiconductor layers vertically separated from each other, a gate structure, and a plurality of diffusion cap layers. The gate structure includes a lower portion and an upper portion, wherein the lower portion wraps each of the semiconductor layers. The diffusion cap layers are disposed between the semiconductor layers and the gate structure and separate the semiconductor layers and the gate structure, wherein the diffusion cap layers serve as a plurality of diffusion barriers for the semiconductor layers.

[0004] The present disclosure also provides a semiconductor device, including a fin structure, a gate structure, a plurality of intermediate layers, and a plurality of inner spacers. The fin structure is disposed on a substrate and has a plurality of semiconductor layers vertically separated from each other. The gate structure includes a lower portion and an upper portion, wherein the lower portion wraps each of the semiconductor layers of the fin structure. The intermediate layers are disposed between the semiconductor layers and the gate structure and separate the semiconductor layers and the gate structure. The inner spacers are vertically disposed between the semiconductor layers and separate the lower portion of the gate structure from a plurality of source / drain structures.

[0005] The present disclosure further provides a semiconductor device. The semiconductor device includes a substrate, a fin structure, an active gate structure, a gate spacer, and a plurality of source / drain structures. The fin structure extends on the substrate along a first lateral direction of the substrate, wherein the fin structure includes a plurality of semiconductor layers and a plurality of diffusion cap layers, wherein the diffusion cap layers serve as a plurality of diffusion barriers for the semiconductor layers. The active gate structure is on the fin structure and each of the semiconductor layers that wrap the fin structure, wherein the diffusion cap layer is disposed between the active gate structure and the semiconductor layer and separates the active gate structure and the semiconductor layer, wherein the active gate structure extends along a second direction perpendicular to the first lateral direction of the substrate. The gate spacer is on a plurality of sidewalls of the active gate structure. The source / drain structures are each electrically coupled to the fin structure, wherein the source / drain structures are on a plurality of opposite sides of a lower portion of the active gate structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When with Figure 1 When read together, various aspects of the present disclosure can be best understood from the following detailed description. It should be noted that various feature sizes may not be drawn to scale according to standard practice in the industry. In fact, various feature sizes may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 schematically illustrates a perspective view of a gate-all-around (GAA) field-effect-transistor (FET) device according to some embodiments;

[0008] Figure 2 According to some embodiments Figure 1 a cross-sectional view of a portion of a gate-all-around field effect transistor device;

[0009] Figure 3 According to some embodiments Figure 1 A cross-sectional view of an isolated portion of a gate-all-around field effect transistor device;

[0010] Figure 4 A flowchart illustrating an exemplary method of manufacturing a semiconductor device according to some embodiments; and

[0011] Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 and Figure 12 In some embodiments, the Figure 4 An exemplary semiconductor device (or a portion of an exemplary all-gate field effect transistor device) fabricated by the method of FIG. 1 , and cross-sectional views thereof at various fabrication stages.

[0012]

Symbol Explanation

[0013] 100: Full-gate field-effect transistor device

[0014] 102: Substrate

[0015] 104: Semiconductor layer

[0016] 105: Diffusion cap layer

[0017] 106: Isolation region

[0018] 107: Gate dielectric layer

[0019] 108: Gate structure

[0020] 109: Gate metal layer

[0021] 110: Source / drain structure

[0022] 111: Contact etch stop layer

[0023] 113: Interlayer dielectric

[0024] 114: Gate spacer

[0025] 116: First conformal layer

[0026] 118: Second conformal layer

[0027] 120: Inner spacer

[0028] 122: First surface

[0029] 124: First surface

[0030] 200: Method

[0031] 210: Square

[0032] 212: Square

[0033] 214: Square

[0034] 216: Square

[0035] 218: Square

[0036] 220: Square

[0037] 222: Square

[0038] 224: Square

[0039] 226: Square

[0040] 228: Square

[0041] 230: Square

[0042] 232: Square

[0043] 234: Square

[0044] 300: Semiconductor device

[0045] 302: Substrate

[0046] 401: Fin structure

[0047] 410: First semiconductor layer

[0048] 415: Diffusion cap layer

[0049] 420: Second semiconductor layer

[0050] 503: Etch stop layer

[0051] 510A: Virtual gate structure

[0052] 510B: Virtual gate structure

[0053] 610A: Semiconductor layer

[0054] 610B: Semiconductor layer

[0055] 615A: Diffusion cap layer

[0056] 615B: Diffusion cap layer

[0057] 620A: Semiconductor layer

[0058] 620B: Semiconductor layer

[0059] 631A: Etch stop layer

[0060] 631B: Etch stop layer

[0061] 710A: First inner spacer

[0062] 710B: Second inner spacer

[0063] 910A: Source / drain structure

[0064] 910B: Source / drain structure

[0065] 910C: Source / drain structure

[0066] 919: Contact etch stop layer

[0067] 921: Interlayer dielectric

[0068] 950A: All-gate transistor

[0069] 950B: All-gate transistor

[0070] 1000A: Gate trench

[0071] 1000B: Gate trench

[0072] 1120: Gate spacer

[0073] 1122: Second conformal layer

[0074] 1124: First conformal layer

[0075] 1500A: Active gate structure

[0076] 1500B: Active gate structure

[0077] 1502A: Gate dielectric layer

[0078] 1502B: Gate dielectric layer

[0079] 1504A: Gate metal layer

[0080] 1504B: Gate metal layer

[0081] A - A: Cross section

[0082] A1: Height

[0083] A2: Height

[0084] A3: Height

[0085] d 1 : First direction

[0086] G1: Height

[0087] G2: Height

[0088] G3: Height

[0089] X: Direction

[0090] Y: Direction

[0091] Z: Direction

[0092] θ1: Interior angle

[0093] θ2: Angle Detailed implementation

[0094] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and compositions are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first feature on or above a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. Such repetition is for simplicity and clarity and does not in itself specify a relationship between the various embodiments and / or configurations discussed.

[0095] As used herein, terms such as "first," "second," and "third" are used to describe various elements, components, regions, layers, and / or portions, but these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, and / or portion from another. The terms "first," "second," and "third" as used herein do not denote an order or sequence unless explicitly stated in the context.

[0096] For the sake of brevity, common techniques related to the manufacture of common semiconductor devices may not be described in detail herein. In addition, the various operations and processes described herein may be incorporated into a more comprehensive operation or process having additional functions not described in detail herein. In particular, various processes in semiconductor device manufacturing may be well known, and thus, for the sake of brevity, many common processes will only be briefly mentioned or completely omitted herein without providing well-known process details. As will be readily apparent to those of ordinary skill in the art upon a complete reading of the present disclosure, the structures disclosed herein may employ a variety of techniques and may be incorporated into various semiconductor devices and products. In addition, it should be noted that semiconductor device structures include different numbers of components, and a single component shown in the figures may represent multiple components.

[0097] In addition, spatial relative terms, such as "upper", "above", "on top", "above it", "thereon", "lower", "below", "underneath", "beneath", "thereunder", etc., may be used in this document to make the description easier to describe the relationship between one element or feature shown in the figure and another element or feature. Spatial relative terms are intended to include different orientations of the device in use or operation other than the orientations described in the figure. The device may be oriented in other ways (rotated 90 degrees or other directions), and the spatial relative terms used herein may be interpreted correspondingly. When a spatial relative term (such as those listed above) is used to describe a first element relative to a second element, the first element may be directly on top of the other element, or there may be elements or layers in between the two. When an element or layer is referred to as "on" another element or layer, it may be directly on top of the other element and in contact with the other element or layer.

[0098] It should be noted that references in the specification to "an embodiment", "an example embodiment", "an exemplary embodiment", "example", "exemplification", etc., indicate that the embodiment may include a specific feature, structure, or characteristic, but each embodiment may not necessarily include the specific feature, structure, or characteristic. Moreover, such terms do not necessarily refer to the same embodiment. In addition, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly stated or not, the relationship of that feature, structure, or characteristic to other embodiments will be within the understanding of those of ordinary skill in the art.

[0099] Some embodiments of the present disclosure will now be described with reference to the accompanying drawings, where like reference numerals are generally used to indicate the same elements herein. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a complete understanding of the claimed subject matter. However, it is apparent that the claimed subject matter may be practiced without these specific details. In other instances, structures and devices may be shown in block diagram form in order to facilitate describing the claimed subject matter.

[0100] Additional operations may be provided before, between, and / or after the stages described in the embodiments. Some of the stages described may be replaced or eliminated for different embodiments. Other features may be added to the semiconductor device structure. Some of the features described below may be replaced or eliminated for different embodiments. Although some embodiments are described with operations performed in a particular order, these operations may be performed in another logical order.

[0101] As used herein, a "layer" is a region, such as a region including any boundary, and does not necessarily include a uniform thickness. For example, a layer may be a region that includes at least some thickness variations.

[0102] Embodiments of the present disclosure are discussed in the context of forming a gate-all-around (GAA) field-effect transistor (FET) device. In some embodiments, a fin including a plurality of first semiconductor layers, a plurality of second semiconductor layers, and a plurality of diffusion cap layers is formed, where the first semiconductor layer and the second semiconductor layer serve as a sacrificial layer and a channel layer, respectively, and the diffusion cap layer is disposed between the first semiconductor layer and the second semiconductor layer to serve as a diffusion barrier therebetween. A dummy gate structure is formed on the fin, and an etch stop layer is provided between the dummy gate structure and the fin. Then, gate spacers are formed on the sidewalls of the dummy gate structure. Next, source / drain structures are formed on opposite sides of the dummy gate structure and have an interlayer dielectric (ILD) covering thereon. When forming the interlayer dielectric, the dummy gate structure, a plurality of portions of the etch stop layer, and a plurality of portions of the sacrificial layer are removed to form and extend a gate trench. Next, an active gate structure is formed in the gate trench to wrap each channel layer.

[0103] The semiconductor devices and methods disclosed herein provide a diffusion cap layer to reduce or eliminate diffusion between the first semiconductor layer and the second semiconductor layer, thereby reducing the likelihood of shape deformation of the second semiconductor layer in the manufacturing process.

[0104] Figure 1 , Figure 2 and Figure 3 Perspective, cross-sectional, and isolation cross-sectional views, respectively, illustrate an exemplary gate-all-around field-effect transistor device 100 according to various embodiments. The gate-all-around field-effect transistor device 100 includes a substrate 102 and a plurality of semiconductor layers 104 (also referred to as nanostructures (e.g., nanosheets, nanowires, etc.)) above the substrate 102. The semiconductor layers 104 are vertically separated from each other (relative to Figure 1in the direction). The isolation region 106 is formed on the opposite side of the protruding portion of the substrate 102, where the semiconductor layer 104 is disposed above the protruding portion. The gate structure 108 wraps around each semiconductor layer 104 (e.g., the entire circumference of each semiconductor layer 104). In this example, the gate structure 108 includes a gate dielectric layer 107 and a gate metal layer 109. The source / drain structure 110 is disposed on the opposite side of the gate structure 108. The source / drain structure may refer to the source or the drain individually or collectively, depending on the context. The interlayer dielectric (ILD) 113 is disposed on the source / drain structure 110, and a contact etch stop layer (CESL) 111 is provided therebetween. The inner spacer 120 is located on the sidewalls of the gate structure 108 between the semiconductor layers 104. The gate spacer 114 is disposed between the gate structure 108 and the contact etch stop layer 111. In this example, the gate spacer 114 includes a first conformal layer 116 along the sidewalls of the gate structure 108 and a second conformal layer 118 along the sidewalls of the contact etch stop layer 111. The intermediate layer or diffusion cap layer 105 is disposed between the semiconductor layer 104, the gate structure 108, and the inner spacer 120. The diffusion cap layer 105 is configured to reduce the possibility of shape deformation of the semiconductor layer 104 during the manufacturing process, thereby facilitating a reduction in the resistance across the semiconductor layer 104. For example, the diffusion cap layer 105 may reduce or eliminate diffusion between the semiconductor layers 104 and diffusion between the sacrificial semiconductor layers (not shown; removed during the manufacturing process).

[0105] In some embodiments, each of the semiconductor layers 104 has a height of about 8 nanometers to 9 nanometers (e.g., Figure 2 the heights A1, A2, and A3 therein), where the height is measured along a direction perpendicular to the first direction d 1 in the direction, and the first direction d 1 extends along the semiconductor layer 104 between the source / drain structures 110. In some embodiments, the multiple regions of the gate structure 108 disposed between the semiconductor layer 104 and the source / drain structure 110 each have a height of about 6 nanometers to 7 nanometers perpendicular to the first direction (e.g., Figure 2 the heights G1, G2, and G3 therein).

[0106] In some embodiments, the multiple regions of the gate structure 108 disposed between the semiconductor layer 104 and the source / drain structure 110 have a cross-sectional shape along the first direction, and the inner corner angle of the cross-sectional shape (e.g., Figure 3 the inner corner angle θ1 therein) is about 90 degrees to 105 degrees. In some embodiments, the first surface 122 of the gate structure 108 and the first surface 124 of the inner spacer 120 define a clamping angle therebetween (e.g., Figure 3The angle θ2) therein is about 165 degrees to 180 degrees, where the first surface 122 of the gate structure 108 and the first surface 124 of the inner spacer 120 are both in contact with the diffusion capping layer 105.

[0107] Figures 1 to 3 The figure illustrates a simplified all-gate field-effect transistor device. Therefore, it should be understood that one or more features in a complete all-gate field-effect transistor device may not be Figures 1 to 3 shown therein. In addition, Figure 1 Some cross-sections shown in subsequent figures are provided as references. As shown, the cross-section A-A extends along the longitudinal axis of the semiconductor layer 104 and along the current flow direction between the source / drain structures (e.g., in the direction Y). For clarity, subsequent figures refer to this reference cross-section. For example, Figure 2 and Figure 3 depict Figure 1 multiple portions of the all-gate field-effect transistor device along the cross-section A-A.

[0108] Figure 4 The figure shows a flowchart of a method 200 for forming a semiconductor device (e.g., a non-planar transistor device) according to one or more embodiments of the present disclosure. For example, at least some operations (or steps) in the method 200 can be used to form a fin field-effect transistor device, an all-gate field-effect transistor device (e.g., the all-gate field-effect transistor device 100), a nanosheet transistor device, a nanowire transistor device, a vertical transistor device, etc. It should be noted that the method 200 is only an example and is not intended to limit the present disclosure. Therefore, it can be understood that additional operations can be provided before, between, and after Figure 4 the method 200, and some other operations may only be briefly described herein. For convenience, some operations of the method 200 will be described in the respective manufacturing stages of an exemplary semiconductor device 300 as shown in Figures 5 to 12 . However, the method 200 is not limited to the exemplary semiconductor device 300 or Figures 5 to 12 the example shown.

[0109] Figures 5 to 12 The operations shown in Figures 1 to 3 are intended to form an all-gate field-effect transistor device similar to the all-gate field-effect transistor device 100 shown in Figures 5 to 12 . It should be understood that the semiconductor device 300 may include many other elements, such as but not limited to inductors, fuses, capacitors, coils, etc., which are not shown in Figures 5 to 12 for clarity of illustration. Figure 1 The cross-sectional view of

[0110] Method 200 may start from block 210. At block 212, method 200 includes providing a substrate 302, as Figure 5 shown. Substrate 302 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., and it may be doped (e.g., with p-type or n-type dopants) or undoped. Substrate 302 may be a wafer, such as a silicon wafer. Generally, a semiconductor-on-insulator substrate includes a semiconductor material layer formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate, typically a silicon or glass substrate. Other substrates may also be used, such as multi-layer or gradient substrates. In some embodiments, the semiconductor material of substrate 302 may include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP, and / or GaInAsP; or combinations thereof.

[0111] At block 214, method 200 includes forming a fin structure 401, where fin structure 401 includes a plurality of first semiconductor layers 410 and a plurality of second semiconductor layers 420 alternately disposed on top of each other (e.g., along direction Z), and fin structure 401 further includes a plurality of spacer layers 415 between the first semiconductor layers 410 and the second semiconductor layers 420 (and on substrate 302) to form a stack on substrate 302. For example, the first layer of spacer layer 415 is disposed on substrate 302, the first layer of first semiconductor layer 410 is disposed on the first layer of spacer layer 415, then the second layer of spacer layer 415 is disposed on the first layer of first semiconductor layer 410, then the first layer of second semiconductor layer 420 is disposed on the second layer of spacer layer 415, then the third layer of spacer layer 415 is disposed on the first layer of second semiconductor layer 420, then the second layer of first semiconductor layer 410 is disposed on the third layer of spacer layer 415, and so on. Fin structure 401 extends along the lateral direction (e.g., direction Y) of substrate 302. The provided spacer layers 415 are configured to reduce or eliminate diffusion between the first semiconductor layers 410 and the second semiconductor layers 420 during the manufacturing process. Thus, the possibility of shape deformation of the second semiconductor layer 420 is reduced, thereby facilitating a reduction in resistance across the second semiconductor layer 420.

[0112] This stack may include any number of alternately disposed first semiconductor layers 410 and second semiconductor layers 420, with spacer layers 415 therebetween. For example, in Figure 6Among them, the stack includes three layers of first semiconductor layers 410, with two layers of second semiconductor layers 420 alternately disposed therebetween, and another layer of second semiconductor layer 420 disposed on the topmost layer of the first semiconductor layer 410 and the second semiconductor layer 420, and a total of six layers of diffusion cap layers 415 are disposed between the first semiconductor layer 410, the second semiconductor layer 420 and the substrate 302. It should be understood that the semiconductor device 300 may include any number of first semiconductor layers 410, any number of second semiconductor layers 420 and any number of diffusion cap layers 415, wherein any one of the first semiconductor layer 410 or the second semiconductor layer 420 is the topmost semiconductor layer of the fin structure 401, which is also within the scope of the present disclosure.

[0113] The first semiconductor layer 410 and the second semiconductor layer 420 may each have different thicknesses. In addition, the first semiconductor layer 410 may have different thicknesses from one layer to another. The second semiconductor layer 420 may have different thicknesses from one layer to another. The thickness of each of the first semiconductor layer 410 and the second semiconductor layer 420 may range from, for example, a few nanometers to several tens of nanometers. The first layer in the stack (e.g., the one closest to the substrate 302) may be thicker than the other first semiconductor layers 410 and second semiconductor layers 420. In one embodiment, each of the first semiconductor layers 410 has a thickness range of about 5 nanometers (nm) to about 20 nanometers (e.g., about 6 nanometers to 7 nanometers), each of the second semiconductor layers 420 has a thickness range of about 5 nanometers to about 20 nanometers (e.g., about 8 nanometers to 9 nanometers), and each diffusion cap layer 415 has a thickness range of about 1 nanometer to about 4 nanometers (e.g., about 1 nanometer to 2 nanometers). In some embodiments, when the thickness of the diffusion cap layer 415 is 1 nanometer or greater, a sufficient diffusion barrier is provided to hinder, reduce or eliminate the diffusion between the first semiconductor layer 410 and the second semiconductor layer 420, thereby reducing the possibility of shape deformation of the second semiconductor layer 420 during the manufacturing process. In some embodiments, when the thickness of the diffusion cap layer 415 is 4 nanometers or less, sufficient space can be provided for the first semiconductor layer 410 (and the portions of the active gate structures 1500A and 1500B that finally replace the first semiconductor layer 410 as described below), thereby promoting the reduction of the resistance of the channel electrically coupled to the source / drain structures 910A, the source / drain structures 910B and the source / drain structures 910C (as described below).

[0114] The first semiconductor layer 410 and the second semiconductor layer 420 have different compositions. In different embodiments, the first semiconductor layer 410 and the second semiconductor layer 420 have compositions that provide different oxidation rates and / or different etching selectivities between the first semiconductor layer 410 and the second semiconductor layer 420. In one embodiment, the first semiconductor layer 410 comprises silicon germanium (Si 1-x Ge x ), and the second semiconductor layer comprises silicon (Si). In one embodiment, each of the second semiconductor layers 420 is silicon and can be undoped or substantially dopant-free (i.e., having an extrinsic dopant concentration of about 0 cm -3 to about 1x10 17 cm -3 ), where, for example, no intentional doping is performed when forming the second semiconductor layer 420 (e.g., silicon). The diffusion cap layer 415 has a composition that reduces the likelihood of diffusion between the first semiconductor layer 410 and the second semiconductor layer 420. In one embodiment, the diffusion cap layer 415 comprises silicon nitride (SiN).

[0115] In different embodiments, the second semiconductor layer 420 can be intentionally doped. For example, when the semiconductor device 300 is configured as n-type (and operates in enhancement mode), each of the second semiconductor layers 420 can be silicon doped with a p-type dopant such as boron (B), aluminum (Al), indium (In), and gallium (Ga); and when the semiconductor device 300 is configured as p-type (and operates in enhancement mode), each of the second semiconductor layers 420 can be silicon doped with an n-type dopant such as phosphorus (P), arsenic (As), and antimony (Sb). In another example, when the semiconductor device 300 is configured as n-type (and operates in depletion mode), each of the second semiconductor layers 420 can be silicon doped with an n-type dopant; and when the semiconductor device 300 is configured as p-type (and operates in depletion mode), each of the second semiconductor layers 420 can be silicon doped with a p-type dopant. In some embodiments, each of the first semiconductor layers 410 is Si-Ge and comprises less than 50% (x < 0.5) molar ratio of Ge. For example, the Ge molar ratio can account for about 15% to 35% in the first semiconductor layer 410 of Si 1- x Ge x . In addition, different compositions can be included between the first semiconductor layers 410, and different compositions can be included between the second semiconductor layers 420.

[0116] Either the first semiconductor layer 410 or the second semiconductor layer 420 may include other materials, such as compound semiconductor materials, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductor materials, such as GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP; or combinations thereof. The materials of the first semiconductor layer 410 and the second semiconductor layer 420 may be selected based on providing different oxidation rates and / or etch selectivities.

[0117] In various examples, the fin structure 401 may be formed by first forming the first semiconductor layer 410, the second semiconductor layer 420, and the diffusion capping layer 415 in an interleaved manner to define a stack, and then patterning the stack and the semiconductor substrate 302.

[0118] In various examples, the first semiconductor layer 410, the second semiconductor layer 420, and the diffusion capping layer 415 may be epitaxially grown from the semiconductor substrate 302. For example, each of the first semiconductor layer 410, the second semiconductor layer 420, and the diffusion capping layer 415 may be grown by a molecular beam epitaxy (MBE) process; a chemical vapor deposition (CVD) process, such as a metal organic CVD (MOCVD) process; and / or other suitable epitaxial growth processes. During epitaxial growth, the crystal structure of the semiconductor substrate 302 extends upward, resulting in the first semiconductor layer 410, the second semiconductor layer 420, and the diffusion capping layer 415 having the same crystal orientation as the semiconductor substrate 302.

[0119] In various instances, the stack and the substrate 302 may be patterned using, for example, lithography and etching techniques. For example, a mask layer (which may include multiple layers, such as a pad oxide layer and a pad nitride layer covering thereon) is formed on the topmost semiconductor layer (e.g., Figure 6 the second semiconductor layer 420 in ). The pad oxide layer may be a thin film containing silicon oxide, such as formed using a thermal oxidation process. The pad oxide layer may serve as an adhesion layer between the topmost second semiconductor layer 420 (or the topmost first semiconductor layer 410 in some other embodiments) and the overlying pad nitride layer. In some embodiments, the pad nitride layer is formed of silicon nitride, silicon oxynitride, silicon carbonitride, etc. or combinations thereof. For example, the pad nitride layer may be formed using low-pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD).

[0120] The mask layer can be patterned using lithography techniques. Generally speaking, lithography techniques utilize a photoresist material (not shown), which is deposited, irradiated (exposed), and developed to remove portions of the photoresist material. The remaining photoresist material protects the underlying material (such as the mask layer in this example) from subsequent processing steps (such as etching). For example, the photoresist material is used to pattern the pad oxide layer and the pad nitride layer to form a pattern mask.

[0121] The pattern mask can then be used to pattern the exposed portions of the first semiconductor layer 410, the second semiconductor layer 420, the diffusion cap layer 415, and the substrate 302 to form trenches (or openings), thereby defining fin structures 401 between adjacent trenches. When multiple fin structures 401 are formed, such trenches can be provided between any adjacent structures of the fin structures 401. In some embodiments, the fin structures 401 are formed by etching trenches in the first semiconductor layer 410, the second semiconductor layer 420, the diffusion cap layer 415, and the substrate 302 using, for example, reactive ion etch (RIE), neutral beam etch (NBE), or a combination thereof. The etching can be anisotropic. In some embodiments, the trenches can be strips parallel to each other (when viewed from the top) and closely spaced from each other. In some embodiments, the trenches can be continuous and surround the fin structures 401.

[0122] At block 216, method 200 includes forming an etch stop layer (ESL) 503 at the uppermost of the first semiconductor layer 410 or the second semiconductor layer 420, as Figure 7 shown. The etch stop layer 503 can be formed over the fin structures 401. In some other embodiments, the etch stop layer 503 can be formed only on the top surfaces of the fin structures 401. The etch stop layer 503 can be formed by a deposition process, such as chemical vapor deposition (CVD) (such as plasma enhanced chemical vapor deposition (PECVD), high aspect ratio process (HARP), or a combination thereof), atomic layer deposition (ALD) process, another suitable process, or a combination thereof. The etch stop layer 503 can be formed of a material resistant to the etchant used to remove portions of the dummy gate structures 510A and the dummy gate structures 510B formed in subsequent steps of method 200 discussed in more detail below. In some examples, the etch stop layer 503 can include or be formed of silicon monoxide (SiO).

[0123] At block 218, method 200 includes forming one or more dummy gate structures 510A and dummy gate structure 510B on the etch stop layer 503, as Figure 8 shown. The dummy gate structures 510A and 510B may each extend in a lateral direction (e.g., direction X), which is perpendicular to the lateral direction in which the fin structure 401 extends. In various embodiments, the dummy gate structures 510A and 510B may be disposed at corresponding active (e.g., metal) gate structures formed subsequently. For example, in Figure 8 , each of the dummy gate structures 510A and 510B is placed on a corresponding portion of the fin structure 401, with the etch stop layer 503 sandwiched therebetween. This covered portion of the fin structure 401 subsequently forms a conduction channel, and this conduction channel includes a portion of the second semiconductor layer 420, and each of the dummy gate structures 510A and 510B is replaced by an active gate structure 1500A and an active gate structure 1500B to surround each portion of the second semiconductor layer 420.

[0124] In some embodiments, each of the dummy gate structures 510A and 510B includes a material that is not conducive to epitaxial growth. Thus, during a subsequent process stage where epitaxial growth is performed (e.g., when forming the source / drain structures 910A, 910B, and 910C), epitaxial growth can be significantly limited around the dummy gate structures 510A and 510B (e.g., along the sidewalls of the dummy gate structures 510A and 510B). In some embodiments, the dummy gate structures 510A and 510B may each include one or more silicon-based dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbon oxynitride, silicon carbon oxide, multilayers thereof, or combinations thereof, and may be deposited. In some embodiments, the dummy gate structures 510A and 510B may each include one or more metal-based materials, such as cobalt, tungsten, hafnium oxide, aluminum oxide, or combinations thereof, and may be deposited.

[0125] Figure 9 is a cross-sectional view of the semiconductor device 300, which is a cross-section at various stages of the process, where portions of the etch stop layer 503 that are not located below the dummy gate structures 510A and 510B are removed. The portions of the etch stop layer 503 that are not located below the dummy gate structures 510A and 510B may be removed by an etching process, for example, having one or more steps. By removing these portions of the etch stop layer 503, the topmost second semiconductor layer 420 of the fin structure 401 is exposed.

[0126] The etching process may include a plasma etching process to have a certain amount of anisotropic characteristics. In such a plasma etching process (including radical plasma etching, remote plasma etching, and other suitable plasma etching processes), gas sources such as chlorine gas (C1 2 ), hydrogen bromide (HBr), carbon tetrafluoride (CF 4 ), fluoroform (CHF 3 ), difluoromethane (CH 2 F 2 ), fluoromethane (CH 3 F), hexafluoro-1,3-butadiene (C 4 F 6 ), boron trichloride (BCl 3 ), sulfur hexafluoride (SF 6 ), hydrogen gas (H 2 ), nitrogen trifluoride (NF 3 ), hydrogen fluoride (HF), ammonia gas (NH 3 ) and other suitable gas sources and their combinations can be used together with passivation gases such as nitrogen gas (N 2 ), oxygen gas (O 2 ), carbon dioxide (CO 2 ), sulfur dioxide (SO 2 ), carbon monoxide (CO), methane (CH4), silicon tetrachloride (SiCl 4 ) and other passivation gases and their combinations. In addition, for the plasma etching process, the gas source and / or the passivation gas can be diluted with gases such as argon (Ar), helium (He), neon (Ne) and other suitable dilution gases and their combinations to control the above etching rate. As a non-limiting example, in the etching process, a power source of 10 watts to 4000 watts, a bias power of 0 watts to 4000 watts, a pressure of 1 millitorr to 8 torr, and an etching gas flow rate of 0 sccm to 5000 sccm, such as about 20 sccm to 3000 sccm, can be used. However, it should be noted that power sources, bias powers, pressures, and flow rates outside these ranges can also be considered.

[0127] In another example, the etching process may include a wet etching process to have a certain amount of isotropic characteristics and can be combined with the plasma etching process. In such a wet etching process, main etching chemicals such as hydrofluoric acid (HF), fluorine gas (F 2 ) and other suitable main etching chemicals and their combinations can be combined with auxiliary etching chemicals such as sulfuric acid (H 2 SO 4 ), hydrogen chloride (HCl), hydrogen bromide (HBr), ammonia gas (NH 3 ), phosphoric acid (H 3 PO 4) and other suitable auxiliary etching chemicals and their combinations, as well as solvents such as deionized water, alcohols, acetone, and other suitable solvents and their combinations are used together to control the above etching rate.

[0128] The dummy gate structure 510A and the dummy gate structure 510B can be used as masks to etch the portions of the etch stop layer 503 that do not overlap with them. Thus, along the Z direction, each newly formed sidewall in the remaining portion of the etch stop layer 503 is aligned with the sidewall of the dummy gate structure 510A or the dummy gate structure 510B. For example, in Figure 9 , the etch stop layer 631A is the remaining portion of the etch stop layer 503 covered by the dummy gate structure 510A, and the etch stop layer 631B is the remaining portion of the etch stop layer 503 covered by the dummy gate structure 510B.

[0129] At block 220, the method 200 includes forming gate spacers 1120, as Figure 9 shown. The gate spacers 1120 are formed along the sidewalls of the dummy gate structure 510A and the dummy gate structure 510B. The gate spacers 1120 can each be formed as a single conformal layer or a combination of two or more conformal layers, with each conformal layer arranged on the sidewalls of their respective dummy gate structure 510A and dummy gate structure 510B. It should be understood that any gate spacers formed by a combination of any number of conformal layers can be formed and are also within the scope of the present disclosure. In Figure 9 the example, the gate spacers 1120 include a first conformal layer 1124 and a second conformal layer 1122.

[0130] In some embodiments, each of the second conformal layer 1122 and the first conformal layer 1124 can include a dielectric material selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbide, silicon oxycarbide, etc. or combinations thereof. The first conformal layer 1124 and the second conformal layer 1122 can be formed using, for example, atomic layer deposition (ALD), low-pressure chemical vapor deposition (LPCVD), or plasma-enhanced chemical vapor deposition (PECVD). The thickness range of each conformal layer can be from about to about

[0131] In some embodiments, the first conformal layer 1124 can be deposited on the sidewalls of the dummy gate structure 510A, the dummy gate structure 510B, and the topmost layer of the second semiconductor layer 420. Then, the second conformal layer 1122 can be deposited on the first conformal layer 1124. Thereafter, the portions of the second conformal layer 1122 and the first conformal layer 1124 located on the topmost layer of the second semiconductor layer 420 can be removed, for example, by an etching process.

[0132] After the etching process, the gate spacer 1120 may include a second conformal layer 1122 with one sidewall exposed and a first conformal layer 1124 with an L-shaped profile. Specifically, the L-shaped first conformal layer 1124 includes a vertical portion and a horizontal portion, where the vertical portion is located between the dummy gate structures 510A, 510B and the second conformal layer 1122, and one of the sidewalls of the horizontal portion is exposed.

[0133] At block 222, method 200 includes removing portions of the fin structure 401, as Figure 9 shown. The dummy gate structures 510A and 510B can be used as masks to etch portions of the fin structure 401 not covered by them, such that the fin structure 401 has one or more alternating stacks, and the stacks include remaining portions of the first semiconductor layer 410 and the second semiconductor layer 420 and a remaining portion of the diffusion cap layer 415 therebetween. Thus, along the Z direction, the newly formed sidewalls of the fin structure 401 are aligned with the sidewalls of the dummy gate structure 510A or the dummy gate structure 510B. For example, in Figure 9 FIG., the semiconductor layer 610A, the semiconductor layer 620A, and the diffusion cap layer 615A are respectively the remaining portions of the first semiconductor layer 410, the second semiconductor layer 420, and the diffusion cap layer 415 covered by the dummy gate structure 510A; and the semiconductor layer 610B, the semiconductor layer 620B, and the diffusion cap layer 615B are respectively the remaining portions of the first semiconductor layer 410, the second semiconductor layer 420, and the diffusion cap layer 415 covered by the dummy gate structure 510B.

[0134] At block 224, method 200 includes forming a first inner spacer 710A along the respective etched ends of the semiconductor layer 610A and forming a second inner spacer 710B along the respective etched ends of the semiconductor layer 610B, as Figure 9 shown. To form the first inner spacer 710A and the second inner spacer 710B, the respective end portions of each of the semiconductor layer 610A and the semiconductor layer 610B can be removed first. The end portions of the semiconductor layer 610A and the semiconductor layer 610B can be removed (e.g., etched) using a “pull-back” process to pull back the semiconductor layer 610A and the semiconductor layer 610B to an initial pull-back distance. Although in the Figure 9 illustrated embodiment, the etched ends of each of the semiconductor layer 610A and the semiconductor layer 610B are approximately vertical (e.g., parallel to the sidewalls of the dummy gate structures 510A and 510B), it should be understood that the etched ends can be curved inward or outward. In an example where the semiconductor layer 620A and the semiconductor layer 620B include silicon, the semiconductor layer 610A and the semiconductor layer 610B include silicon germanium (i.e., Si 1-x Ge x), and the spacer capping layer includes silicon nitride (SiN), and the recess process may include an isotropic etching process of hydrogen chloride (HCl) gas to etch SiGe without etching silicon or nitrogen. Thus, the semiconductor layer 620A, the semiconductor layer 620B, the spacer capping layer 615A, and the spacer capping layer 615B remain intact in this process.

[0135] Next, a first inner spacer 710A and a second inner spacer 710B may be formed along the etched ends of each of the semiconductor layers 610A and 610B. Thus, the first inner spacer 710A and the second inner spacer 710B (e.g., their respective inner sidewalls) may follow the profile of the etched ends of the semiconductor layers 610A and 610B. In some embodiments, the first inner spacer 710A and the second inner spacer 710B may be conformally formed by chemical vapor deposition (CVD) or by monolayer doping (MLD) of a nitride followed by reactive ion etching of the spacer. The first inner spacer 710A and the second inner spacer 710B may be deposited using, for example, a conformal deposition process and a subsequent isotropic or anisotropic etching process to remove excess spacer material on the sidewalls of the stack of the fin structure 401 and on the surface of the semiconductor substrate 302. The materials of the first inner spacer 710A and the second inner spacer 710B may be formed of the same or different materials as the dummy gate structures 510A and 510B. For example, the first inner spacer 710A and the second inner spacer 710B may be formed of silicon nitride, silicon boron carbonitride, silicon carbonitride, silicon carbon oxynitride, or any other type of dielectric material (e.g., a dielectric material having a dielectric constant k value less than about 5) to form insulating gate sidewall spacers of the transistor.

[0136] At block 226, method 200 includes forming source / drain structures 910A, source / drain structures 910B, source / drain structures 910C, a contact etch stop layer (CESL) 919, and an interlayer dielectric (ILD) 921, as Figure 11As shown. The source / drain structures 910A, 910B, and 910C can be formed using, for example, an epitaxial layer growth process on the exposed ends of each semiconductor layer 620A and semiconductor layer 620B. In some embodiments, the bottom surfaces of the source / drain structures 910A, 910B, and 910C can be flush with the top surface of an isolation structure (not shown) embedded in the lower portion of the fin structure 401. In some other embodiments, the bottom surfaces of the source / drain structures 910A, 910B, and 910C can be lower than the top surface of such an isolation structure. On the other hand, in some embodiments, the top surfaces of the source / drain structures 910A, 910B, and 910C can be higher than the top surfaces of the topmost semiconductor layers 610A and 610B, as Figure 10 shown. In some other embodiments, the top surfaces of the source / drain structures 910A, 910B, and 910C can be flush with or lower than the top surfaces of the topmost semiconductor layers 610A and 610B.

[0137] The source / drain structures 910A, 910B, and 910C are electrically coupled to the corresponding semiconductor layers 620A and 620B. For example, the source / drain structures 910A and 910B can be electrically coupled to the semiconductor layer 620A; and the source / drain structures 910B and 910C can be electrically coupled to the semiconductor layer 620B. In different embodiments, the semiconductor layer 620A can be collectively referred to as the conduction channel of a first fully gated transistor (hereinafter referred to as "fully gated transistor 950A"); and the semiconductor layer 620B can be collectively referred to as the conduction channel of a second fully gated transistor (hereinafter referred to as "fully gated transistor 950B"). It should be noted that at this stage of the process, the fully gated transistors 950A and 950B are not yet complete.

[0138] In-situ doping (ISD) can be used to form the doped source / drain structures 910A, 910B, and 910C, thereby forming junctions for the fully gated transistors 950A and 950B. N-type and p-type transistors are formed by implanting different types of dopants into selected regions of the device (e.g., the source / drain structures 910A, 910B, and 910C) to form junctions. An N-type device can be formed by injecting arsenic (As) or phosphorus (P), and a p-type device can be formed by injecting boron (B).

[0139] When forming source / drain structures 910A, source / drain structure 910B, and source / drain structure 910C, a contact etch stop layer 919 can be formed by depositing a dielectric material on the partially formed all-gate transistors 950A and all-gate transistors 950B. Then, by depositing a large amount of additional dielectric material on the contact etch stop layer 919 and polishing the bulk oxide (e.g., using CMP) to the horizontal plane of the dummy gate structures 510A and dummy gate structures 510B, the interlayer dielectric 921 can be formed. The dielectric materials of the contact etch stop layer 919 and the interlayer dielectric 921 can include silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or a combination thereof.

[0140] At block 228, method 200 includes removing the dummy gate structures 510A and dummy gate structures 510B and a portion of the etch stop layers 631A and etch stop layers 631B, as Figure 11 shown. After forming the interlayer dielectric 921 ( Figure 10 ), the dummy gate structures 510A and dummy gate structures 510B are removed, thereby forming gate trenches 1000A and gate trenches 1000B, respectively. The dummy gate structures 510A and dummy gate structures 510B can be removed by known etching processes, such as RIE or chemical oxide removal (COR). After removing the dummy gate structures 510A and dummy gate structures 510B (forming gate trenches 1000A and gate trenches 1000B), the top surfaces of the etch stop layers 631A and etch stop layers 631B are exposed. Although not shown, it should be understood that in some embodiments, in addition to the top surfaces of the etch stop layers 631A and etch stop layers 631B, the sidewalls of the semiconductor layers 610A and semiconductor layers 610B and semiconductor layers 620A and semiconductor layers 620B (in the facing direction X) are also exposed.

[0141] Portions of the etch stop layers 631A and 631B that do not extend along the sidewalls of the gate trenches 1000A and 1000B can be removed by an etching process and may thus include one or more steps. By removing these portions of the etch stop layers 631A and 631B, the top surfaces of the topmost semiconductor layers 620A and 620B are exposed. The etching process can include, for example, a plasma etching process, a wet etching process, or a combination thereof, as previously described for Figure 9 described.

[0142] Each sidewall of the remaining portions (if any) of the etch stop layers 631A and 631B is vertically aligned with the sidewalls jointly formed by the first conformal layer 1124 and the second conformal layer 1122 of the gate spacer 1120. These vertically aligned sidewalls of the gate spacer 1120 are exposed in the gate trenches 1000A and 1000B.

[0143] At block 230, method 200 includes removing the semiconductor layers 610A and 610B, as Figure 11 shown. The semiconductor layers 610A and 610B can be removed by using a selective etchant (e.g., hydrochloric acid (HCl)) while leaving the semiconductor layers 620A, 620B, the diffusion cap layers 615A and 615B substantially intact. After removing the semiconductor layers 610A and 610B, according to various embodiments, the respective bottom surfaces and / or top surfaces of each of the diffusion cap layers 615A and 615B can be exposed by the "extended" gate trenches 1000A and 1000B. For example, when removing the semiconductor layers 610A and 610B, the gate trenches 1000A and 1000B can be extended from the regions above the topmost semiconductor layers 610A and 610B to the regions below the topmost semiconductor layers 610A and 610B. Thus, the bottom surfaces of each of the topmost diffusion cap layers 615A and 615B can be exposed, and the corresponding top and bottom surfaces of each of the remaining diffusion cap layers 615A and 615B can also be exposed.

[0144] At block 232, method 200 includes forming one or more active gate structures 1500A and 1500B as Figure 12 shown. The active gate structures 1500A and 1500B can be formed in the extended gate trenches 1000A and 1000B ( Figure 11), while leaving other components (e.g., gate spacer 1120) substantially intact. Thus, active gate structure 1500A and active gate structure 1500B can inherit the dimensions and profiles of gate trench 1000A and gate trench 1000B, respectively. The upper portion can be surrounded by gate spacer 1120, and the lower portion can enclose each of semiconductor layer 620A / semiconductor layer 620B and diffusion capping layer 615A / diffusion capping layer 615B.

[0145] In some embodiments, each of active gate structure 1500A and active gate structure 1500B includes a gate dielectric and a gate metal. In such embodiments, the gate dielectric and the gate metal can each form one or more layers.

[0146] In Figure 12 the example of, gate dielectric layer 1502A, gate dielectric layer 1502B, gate metal layer 1504A, and gate metal layer 1504B enclose each of semiconductor layer 620A, semiconductor layer 620B, diffusion capping layer 615A, and diffusion capping layer 615B, such as the top surface, bottom surface, and sidewalls facing direction X. Gate dielectric layer 1502A and gate dielectric layer 1502B can be formed of different high-k dielectric materials or similar high-k dielectric materials. Examples of high-k dielectric materials include metal oxides, nitrides, or silicates of Hf, Al, Zr, Ta, La, Mg, Ba, Ti, Pb, and combinations thereof, etc. Gate dielectric layer 1502A and gate dielectric layer 1502B can include a stack of multiple high-k dielectric materials. Gate dielectric layer 1502A and gate dielectric layer 1502B can be deposited using any suitable method, including, for example, molecular beam deposition (MBD), atomic layer deposition (ALD), PECVD, etc. In some embodiments, gate dielectric layer 1502A and gate dielectric layer 1502B can optionally include a substantially thin oxide (e.g., SiO 2 ) layer, and a native oxide layer can be formed on the surface of each of diffusion capping layer 615A and diffusion capping layer 615B.

[0147] The gate metal layer 1504A and the gate metal layer 1504B can wrap around each of the semiconductor layer 620A, the semiconductor layer 620B, the diffusion cap layer 615A, and the diffusion cap layer 615B, and have the gate dielectric layer 1502A and the gate dielectric layer 1502B disposed therebetween. Specifically, the gate metal layer 1504A and the gate metal layer 1504B can include a plurality of gate metal portions adjacent to each other along the direction Z. Each gate metal portion can extend not only along a horizontal plane (e.g., a plane extended by the direction X and the direction Y), but also along a vertical direction (e.g., the direction Z). Therefore, two adjacent portions of the gate metal portion can be adjacent to each other to wrap between the corresponding semiconductor layer 620A, the semiconductor layer 620B, the diffusion cap layer 615A, and the diffusion cap layer 615B, where the gate dielectric layer 1502A and the gate dielectric layer 1502B are disposed therebetween.

[0148] The gate metal layer 1504A and the gate metal layer 1504B can include a stack of various metal materials. For example, the gate metal layer 1504A and the gate metal layer 1504B can be a p-type work function layer, an n-type work function layer, a multi-layer thereof, or a combination. The work function layer can also be referred to as a work function metal. For example, the p-type work function metal can include TiN, TAN, Ru, Mo, Al, WN, ZrSi 2 , MoSi 2 , TaSi 2 , NiSi 2 , WN, other suitable p-type work function materials, or a combination thereof. For example, the n-type work function metal can include Ti, Ag, TaAl, TaAIC, TiAin, TAC, TACN, TaSiN, Mn, Zr, other suitable n-type work function materials, or a combination thereof. The work function value is associated with the material composition of the work function layer. Therefore, the material of the work function layer is selected to adjust the work function value in order to achieve the target threshold voltage V in the formed device. The work function layer can be deposited by CVD, physical vapor deposition (PVD), ALD, and / or other suitable processes.

[0149] Method 200 can end at block 234.

[0150] Therefore, the present disclosure provides a semiconductor device and a method formed using a diffusion cap layer.

[0151] The semiconductor devices and methods disclosed herein provide diffusion cap layers (e.g., diffusion cap layer 615A and diffusion cap layer 615B) to reduce or eliminate diffusion between a first semiconductor layer and a second semiconductor layer, thereby reducing the likelihood of shape distortion of the second semiconductor layer during manufacturing. For example, in a composition where the first semiconductor layer comprises silicon germanium and the second semiconductor layer comprises silicon, the thermal energy generated during the manufacturing of the semiconductor may cause germanium to diffuse from the first semiconductor layer to the second semiconductor layer. When the first semiconductor layer is removed using an etching process, a portion of the second semiconductor layer including the diffused germanium may also be etched and removed. In such an example, the second semiconductor layer may have a distorted shape, which may increase the resistance. In such an example, the diffusion cap layer 615A and the diffusion cap layer 615B may be formed of, for example, silicon nitride to prevent the diffusion of germanium and thereby maintain the shape of the second semiconductor layer and thereby facilitate a reduction in resistance.

[0152] In one aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes a plurality of semiconductor layers vertically separated from each other, a gate structure, and a plurality of diffusion cap layers. The gate structure includes a lower portion and an upper portion, wherein the lower portion wraps each of the semiconductor layers. The diffusion cap layers are disposed between the semiconductor layers and the gate structure and separate the semiconductor layers and the gate structure, wherein the diffusion cap layers serve as a plurality of diffusion barriers for these semiconductor layers. In some embodiments, each of the diffusion cap layers has a thickness of about 1 nanometer to 2 nanometers such that diffusion between the semiconductor layers is sufficiently impeded to prevent deformation of the semiconductor layers. In some embodiments, the semiconductor layers include silicon. In some embodiments, the diffusion cap layers include silicon nitride. In some embodiments, the diffusion cap layers are silicon nitride layers. In some embodiments, the semiconductor layers extend between a plurality of source / drain structures along a first direction and are electrically coupled to the source / drain structures, and a plurality of regions of the lower portion of the gate structure are disposed between the semiconductor layers and the source / drain structures, wherein each of the semiconductor layers has a height of about 8 nanometers to 9 nanometers perpendicular to the first direction, and each of the regions of the lower portion of the gate structure has a height of about 6 nanometers to 7 nanometers perpendicular to the first direction. In some embodiments, the semiconductor layers extend between a plurality of source / drain structures along a first direction and are electrically coupled to the source / drain structures, a plurality of regions of the lower portion of the gate structure are disposed between the semiconductor layers and the source / drain structures, and these regions of the lower portion of the gate structure have a plurality of cross-sectional shapes along the first direction, and these cross-sectional shapes have a plurality of inner corner angles of about 90 degrees to 105 degrees. In some embodiments, the semiconductor device further includes a plurality of inner spacers vertically disposed between the semiconductor layers and separating the lower portion of the gate structure from the plurality of source / drain structures, wherein an angle of about 165 degrees to 180 degrees is defined between a plurality of first surfaces of the lower portion of the gate structure and a plurality of first surfaces of these inner spacers, wherein the first surfaces of the lower portion of the gate structure and the first surfaces of the inner spacers are both in contact with the diffusion cap layer.

[0153] In another aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes a fin structure, a gate structure, a plurality of intermediate layers, and a plurality of inner spacers. The fin structure is disposed on a substrate and has a plurality of semiconductor layers vertically separated from each other. The gate structure includes a lower portion and an upper portion, wherein the lower portion wraps each of the semiconductor layers of the fin structure. The intermediate layers are disposed between the semiconductor layers and the gate structure and separate the semiconductor layers and the gate structure. The inner spacers are vertically disposed between the semiconductor layers and separate the lower portion of the gate structure from a plurality of source / drain structures. In some embodiments, the intermediate layers serve as a plurality of diffusion barriers for the semiconductor layers. In some embodiments, each of the intermediate layers has a thickness of about 1 nanometer to 2 nanometers such that diffusion between the semiconductor layers is sufficiently impeded to prevent deformation of the semiconductor layers. In some embodiments, the semiconductor layers include silicon and the intermediate layers include silicon nitride. In some embodiments, the semiconductor layers extend between the source / drain structures along a first direction and are electrically coupled to the source / drain structures, and a plurality of regions of the lower portion of the gate structure are disposed between the semiconductor layers and the source / drain structures, wherein each of the semiconductor layers has a height of about 8 nanometers to 9 nanometers perpendicular to the first direction, and each of the regions of the lower portion of the gate structure has a height of about 6 nanometers to 7 nanometers perpendicular to the first direction. In some embodiments, the semiconductor layers extend between the source / drain structures along a first direction and are electrically coupled to the source / drain structures, a plurality of regions of the lower portion of the gate structure are disposed between the semiconductor layers and the source / drain structures, and these regions of the lower portion of the gate structure have a plurality of cross-sectional shapes along the first direction, and these cross-sectional shapes have a plurality of inner corner angles of about 90 to 105 degrees. In some embodiments, an included angle of about 165 degrees to 180 degrees is defined between a plurality of first surfaces of the lower portion of the gate structure and a plurality of first surfaces of the inner spacers, wherein the first surfaces of the lower portion of the gate structure and the first surfaces of the inner spacers are both in contact with the intermediate layers.

[0154] In yet another aspect of the present disclosure, a method of manufacturing a semiconductor device is disclosed. The method includes the following operations. Form a fin structure on a substrate that extends along a first lateral direction of the substrate, wherein the fin structure includes a plurality of alternating first semiconductor layers, a plurality of second semiconductor layers, and a plurality of diffusion cap layers between the first semiconductor layers and the second semiconductor layers, wherein the diffusion cap layers serve as a plurality of diffusion barriers between the first semiconductor layers and the second semiconductor layers. Form an etch stop layer on the fin structure. Form a dummy gate structure on a portion of the fin structure, wherein the dummy gate structure extends along a second direction perpendicular to the first lateral direction of the substrate, and wherein a plurality of portions of the etch stop layer are located between the fin structure and the dummy gate structure. Line the plurality of sidewalls of the dummy gate structure with a plurality of gate spacers, wherein the gate spacers are separated from the fin structure by the etch stop layer. Remove the plurality of portions of the fin structure that are not located under the dummy gate structure. Form a plurality of source / drain structures each electrically coupled to an end of the fin structure, wherein the source / drain structures are formed at the plurality of positions previously occupied by the portions of the fin structure. Remove the dummy gate structure to form a gate trench. Remove the first semiconductor layer such that the second semiconductor layers are vertically separated from each other by a plurality of spaces. Form an active gate structure in the gate trench, wherein the active gate structure wraps each of the second semiconductor layers of the fin structure by filling these spaces, and wherein the diffusion cap layer is disposed between the active gate structure and the second semiconductor layer and separates the active gate structure and the second semiconductor layer. In some embodiments, each of the diffusion cap layers has a thickness of about 1 nanometer to 2 nanometers such that diffusion between the second semiconductor layers is sufficiently hindered to prevent deformation of the second semiconductor layers. In some embodiments, the first semiconductor layer includes silicon germanium, the second semiconductor layer includes silicon, and the diffusion cap layer reduces the germanium diffusing from the first semiconductor layer to the second semiconductor layer. In some embodiments, the diffusion cap layer includes silicon nitride. In some embodiments, the second semiconductor layers extend between the source / drain structures along a first direction and are electrically coupled to the source / drain structures, and a plurality of regions of the active gate structure are disposed between the second semiconductor layers and the source / drain structures, wherein each of the second semiconductor layers has a height of about 8 nanometers to 9 nanometers perpendicular to the first direction, and each of the regions of the active gate structure has a height of about 6 nanometers to 7 nanometers perpendicular to the first direction. In some embodiments, the method further includes disposing a plurality of inner spacers vertically between the second semiconductor layers, the inner spacers separating the active gate structure from the source / drain structures, wherein an angle of about 165 degrees to 180 degrees is defined between a plurality of first surfaces of the active gate structure and a plurality of first surfaces of the inner spacers, and wherein the first surfaces of the active gate structure and the first surfaces of the inner spacers are both in contact with the diffusion cap layer.

[0155] The present disclosure also provides a semiconductor device. The semiconductor device includes a substrate, a fin structure, an active gate structure, a gate spacer, and a plurality of source / drain structures. The fin structure extends on the substrate along a first lateral direction of the substrate, wherein the fin structure includes a plurality of semiconductor layers and a plurality of diffusion cap layers, and the diffusion cap layers serve as a plurality of diffusion barriers for the semiconductor layers. The active gate structure is on the fin structure and wraps each of the semiconductor layers in the fin structure, wherein the diffusion cap layer is disposed between the active gate structure and the semiconductor layer and separates the active gate structure and the semiconductor layer, and the active gate structure extends along a second direction perpendicular to the first lateral direction of the substrate. The gate spacer is on a plurality of sidewalls of the active gate structure. The source / drain structures are each electrically coupled to the fin structure, and the source / drain structures are on a plurality of opposite sides of a lower portion of the active gate structure. In some embodiments, the semiconductor layer is a silicon layer.

[0156] The foregoing has outlined features of some embodiments so that those of ordinary skill in the art may better understand the aspects of the present disclosure. Those of ordinary skill in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those of ordinary skill in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: include: a plurality of semiconductor layers separated vertically from one another; a gate structure, the gate structure comprising a lower portion and an upper portion, wherein the lower portion wraps around each of the plurality of semiconductor layers; as well as A plurality of diffusion cap layers are disposed between the plurality of semiconductor layers and the gate structure and separate the plurality of semiconductor layers from the gate structure, wherein the plurality of diffusion cap layers serve as a plurality of diffusion barriers for the plurality of semiconductor layers.

2. The semiconductor device according to claim 1, wherein Each of the plurality of diffusion cap layers has a thickness of 1 nanometer to 2 nanometers, so that a diffusion between the plurality of semiconductor layers is sufficiently hindered to prevent a deformation of the plurality of semiconductor layers.

3. The semiconductor device according to claim 1, wherein The multiple semiconductor layers extend along a first direction between multiple source / drain structures and are electrically coupled with the multiple source / drain structures, and the multiple regions of the lower portion of the gate structure are arranged between the multiple semiconductor layers and the multiple source / drain structures, wherein each of the multiple semiconductor layers has a height of 8 nanometers to 9 nanometers perpendicular to the first direction, and each of the multiple regions of the lower portion of the gate structure has a height of 6 nanometers to 7 nanometers perpendicular to the first direction.

4. The semiconductor device according to claim 1, wherein: The multiple semiconductor layers extend along a first direction between multiple source / drain structures and are electrically coupled with the multiple source / drain structures, the multiple regions of the lower portion of the gate structure are arranged between the multiple semiconductor layers and the multiple source / drain structures, and the multiple regions of the lower portion of the gate structure have multiple cross-sectional shapes along the first direction, and the multiple cross-sectional shapes have multiple internal angles ranging from 90 degrees to 105 degrees.

5. The semiconductor device according to claim 1, wherein: It also includes a plurality of inner spacers vertically arranged between the plurality of semiconductor layers and separating the lower portion of the gate structure from the plurality of source / drain structures, wherein the plurality of first surfaces of the lower portion of the gate structure and the plurality of first surfaces of the plurality of inner spacers define an angle of 165 degrees to 180 degrees, wherein the plurality of first surfaces of the lower portion of the gate structure and the plurality of first surfaces of the plurality of inner spacers are both in contact with the plurality of diffusion cap layers.

6. A semiconductor device, characterized in that: include: A fin structure is disposed on a substrate and has a plurality of semiconductor layers vertically separated from each other; a gate structure comprising a lower portion and an upper portion, wherein the lower portion wraps around each of the plurality of semiconductor layers of the fin structure; A plurality of intermediate layers, disposed between the plurality of semiconductor layers and the gate structure and separating the plurality of semiconductor layers and the gate structure; as well as A plurality of inner spacers are vertically disposed between the plurality of semiconductor layers and separate the lower portion of the gate structure from a plurality of source / drain structures.

7. The semiconductor device according to claim 6, wherein: Each of the plurality of intermediate layers has a thickness of 1 nm to 2 nm, so that diffusion between the plurality of semiconductor layers is sufficiently hindered to prevent deformation of the plurality of semiconductor layers.

8. The semiconductor device according to claim 6, wherein: The multiple semiconductor layers extend along a first direction between the multiple source / drain structures and are electrically coupled with the multiple source / drain structures, and the multiple regions of the lower portion of the gate structure are arranged between the multiple semiconductor layers and the multiple source / drain structures, wherein each of the multiple semiconductor layers has a height of 8 nanometers to 9 nanometers perpendicular to the first direction, and each of the multiple regions of the lower portion of the gate structure has a height of 6 nanometers to 7 nanometers perpendicular to the first direction.

9. The semiconductor device according to claim 6, wherein: The multiple semiconductor layers extend between the multiple source / drain structures along a first direction and are electrically coupled with the multiple source / drain structures, the multiple regions of the lower portion of the gate structure are arranged between the multiple semiconductor layers and the multiple source / drain structures, and the multiple regions of the lower portion of the gate structure have multiple cross-sectional shapes along the first direction, and the multiple cross-sectional shapes have multiple internal angles ranging from 90 degrees to 105 degrees.

10. A semiconductor device, characterized in that: include: a substrate; A fin structure extends on the substrate along a first lateral direction of the substrate, wherein the fin structure comprises a plurality of semiconductor layers and a plurality of diffusion cap layers, wherein the plurality of diffusion cap layers serve as a plurality of diffusion barriers for the plurality of semiconductor layers; an active gate structure on the fin structure and wrapping each of the plurality of semiconductor layers of the fin structure, wherein the plurality of diffusion cap layers are disposed between the active gate structure and the plurality of semiconductor layers and separate the active gate structure and the plurality of semiconductor layers, and the active gate structure extends along a second lateral direction perpendicular to the first lateral direction of the substrate; A plurality of gate spacers are on a plurality of sidewalls of the active gate structure; as well as A plurality of source / drain structures are each electrically coupled to the fin structure, wherein the plurality of source / drain structures are on opposite sides of a lower portion of the active gate structure.

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