Radio frequency switch device

Abstract

The utility model discloses a radio frequency switch device. In the radio frequency switch device, a core region low-voltage tube P-type well PWCO is arranged between a body region and a P-type semiconductor substrate PSUB; a deep N-type well DNW is arranged between the device region and the P-type semiconductor substrate PSUB; and the P-type channel region is formed by a switch tube P-type well (PWSW) penetrating through the deep N-type well (DNW). Compared with a silicon-on-insulator radio frequency switch device structure, a deep N-type well (DNW) is arranged between a device region and a P-type semiconductor substrate (PSUB), and a P-type channel region is formed by a switch tube P-type well (PWSW) penetrating through the deep N-type well (DNW), so that an insulating layer is prevented from being integrally inserted between an active layer and a substrate layer, the silicon-on-insulator radio frequency switch device structure can be compatible with an existing bulk silicon process device platform, and the performance of the silicon-on-insulator radio frequency switch device structure is improved. And the aim of greatly reducing the influence of the substrate capacitance on the device in a turn-off state is fulfilled as the structure of a silicon radio frequency switch device on an insulator.

Description

Technical Field

[0001] The utility model relates to the technical field of radio frequency front-end devices, and particularly relates to a radio frequency switch device. Background Art

[0002] Under the requirements of 5G, the radio frequency switch should not only meet the requirements of high power and high frequency, but also cooperate with a more complex radio frequency signal path for structural improvement. In the selection of materials and processes, compound semiconductor processes are mostly used for radio frequency switches, such as gallium nitride and gallium arsenide processes, or the RF-SOI (Silicon-On-Insulator) process is still used.

[0003] Silicon-on-insulator (SOI) is a special silicon wafer. The main feature of its structure is that an insulating layer (buried oxide layer) is inserted between the active layer and the substrate layer to cut off the electrical connection between the active layer and the substrate. This structural feature brings many advantages to SOI-based devices, such as small parasitic effects, high speed, low power consumption, high integration, and strong radiation resistance.

[0004] For example, Chinese patent document CN 105161500 A discloses a silicon-on-insulator radio frequency switch device structure. In this structure, as Figure 1 shown, the buried oxide layer 60 is arranged on the silicon-based bottom layer 70 (substrate) as the insulating layer, and the channel region 30, source region 31, and drain region 32 are arranged above the buried oxide layer 60. The channel region 30, source region 31, and drain region 32 are surrounded by the isolation region 50 to achieve full dielectric isolation between the radio frequency switch device and the substrate. This structure can achieve higher linearity and lower insertion loss. However, this method has the disadvantages of long development cycle, high difficulty, and higher production cost at the same time, and it cannot be compatible with the existing bulk silicon process device platform. Summary of the Utility Model

[0005] Term Explanation

[0006] DTI: Deep-Trench-Isolation

[0007] DNW: Deep-N-type-Well

[0008] SOI: Silicon-On-Insulator

[0009] PWCO, P type Well for Core mos with low voltage in the core area

[0010] NWCO: N type Well for Core mos, the low-voltage tube in the core area

[0011] PWSW: P type Well for Switch mos, the P-type well of the switching tube

[0012] PSUB: P-type silicon substrate

[0013] The purpose of the present utility model is to provide a radio frequency switch device, which can not only be compatible with the existing bulk silicon process device platform, but also greatly reduce the influence of the substrate capacitance on the device in the off state.

[0014] To achieve the above object, the present utility model provides a radio frequency switch device, which includes: a P-type semiconductor substrate PSUB; and a body region and a device region located above the P-type semiconductor substrate PSUB, wherein, when observed from a top view, the body region surrounds the device region;

[0015] A core region low-voltage tube P-type well PWCO is provided between the body region and the P-type semiconductor substrate PSUB; PWCO is essentially a well region ion implantation specially implanted for the core tube.

[0016] A deep N-type well DNW is provided between the device region and the P-type semiconductor substrate PSUB;

[0017] The device region includes a P-type channel region, and an N-type source region and an N-type drain region respectively located on both sides of the P-type channel region;

[0018] The P-type channel region is formed by a switching tube P-type well PWSW that penetrates the deep N-type well DNW. The switching tube P-type well PWSW divides the deep N-type well DNW into two independent sub-regions. An N-type source region is formed above one sub-region, and an N-type drain region is formed above the other sub-region. DNW is either a buried oxide layer or a PN junction formed by N-type IMP and the P-type substrate.

[0019] Preferably, the switching tube P-type well PWSW is only formed under the channel to reduce the contact area between the source-drain and the device well region, thereby reducing the radio frequency off-capacitance.

[0020] Preferably, the deep N-type well DNW is arranged on the P-type semiconductor substrate PSUB, and its depth is less than the depth of the core region low-voltage tube P-type well PWCO.

[0021] Preferably, the depth of the switching tube P-type well PWSW is greater than the depth of the deep N-type well DNW.

[0022] Preferably, a source electrode is provided on the surface of the source region, and a drain electrode is provided on the surface of the drain region.

[0023] Preferably, a conductor block serving as a gate (Gate) is provided on the upper surface of the deep N-type well region (DNW).

[0024] Preferably, the N-type source region and the body region are isolated by a shallow trench isolation (STI); the N-type drain region and the body region are isolated by a shallow trench isolation (STI).

[0025] Preferably, the doping concentration of the deep N-type well (DNW) is lower than the doping concentrations of the N-type source region and the N-type drain region.

[0026] The deep N-type well (DNW) is provided to make the region in contact with the N+ regions of the source region and the drain region also N-type, thereby reducing the junction capacitance.

[0027] In addition, the concentration of the DNW is smaller than the concentration of the N+ regions of the source region and the drain region, making the PN junction depletion layer formed with the substrate wider and having a higher breakdown voltage.

[0028] Preferably, an N-type source region and an N-type drain region are formed by heavily doping (ion implantation) the upper part of the deep N-type well (DNW).

[0029] Preferably, when observed from a top view, a DNW ring is disposed around the outside of the body region, and the DNW ring and the body region are isolated by a shallow trench isolation (STI).

[0030] The STI isolates a ring-shaped active region for ion implantation (NWCO). After the DNW is taken out, different voltage biases can be applied.

[0031] Compared with the silicon-on-insulator radio frequency switch device structure, a deep N-type well (DNW) is provided between the device region and the P-type semiconductor substrate (PSUB). The P-type channel region is formed by a switching transistor P-type well (PWSW) penetrating the deep N-type well (DNW), thereby avoiding the overall insertion of an insulating layer between the active layer and the substrate layer, being able to be compatible with the existing bulk silicon process device platform, and achieving the purpose of greatly reducing the influence of the substrate capacitance on the device in the off state, just like the silicon-on-insulator radio frequency switch device structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a schematic diagram of a radio frequency switch structure of the prior art.

[0033] Figure 2 is a schematic top view of a radio frequency switch structure according to an embodiment of the present invention.

[0034] Figure 3 is along Figure 2 the A-A line in

[0035] Figure 4 is a schematic cross-sectional view along Figure 2 the B-B line in Detailed implementation manners

[0036] In the drawings, the same or similar reference numerals are used to denote the same or similar elements or elements having the same or similar functions. The embodiments of the present invention will be described in detail below with reference to the drawings.

[0037] The radio frequency switch device according to the present invention is essentially a radio frequency switch chip. As Figures 2 to 4 shown, the radio frequency switch device according to an embodiment of the present invention includes: a P-type semiconductor substrate PSUB; and a body region and a device region located above the P-type semiconductor substrate PSUB, wherein, when observed from a top view perspective, the body region surrounds the device region. From the top view Figure 2 view, a body ring surrounds the device region, that is to say, the body ring surrounds the source electrode, the drain electrode and the gate electrode. Specifically, the body ring is formed by performing P+ heavy doping at the upper part of the P-type well PWCO of the core region low-voltage transistor.

[0038] As Figure 3 and Figure 4 shown, a core region low-voltage transistor P-type well PWCO is provided between the body region and the P-type semiconductor substrate PSUB. PWCO is essentially a well region ion implantation specially implanted for the core transistor.

[0039] A deep N-type well DNW is provided between the device region and the P-type semiconductor substrate PSUB. The deep N-type well DNW is not a buried oxide layer in the prior art, but an N-type IMP, which is used to form a PN junction with the P-type substrate.

[0040] The device region includes a P-type channel region, and an N-type source region and an N-type drain region respectively located on both sides of the P-type channel region. Referring to Figure 3 and Figure 4 , the P-type channel region is formed by a switching transistor P-type well PWSW that vertically penetrates the deep N-type well DNW. The switching transistor P-type well PWSW divides the deep N-type well DNW into two independent sub-regions on the left and right sides. An N-type source region is formed above one sub-region, and an N-type drain region is formed above the other sub-region. The left-right direction, that is Figure 3 the left-right direction in Figure 3 is also Figure 2 the left-right direction in Figure 3 The Y direction in

[0041] As Figure 3 andFigure 4 As shown, the P-type well PWSW of the switching transistor is only formed under the channel to reduce the contact area between the source / drain and the device well region, thereby reducing the RF off-capacitance.

[0042] The deep N-type well DNW is directly disposed on the P-type semiconductor substrate PSUB and is formed by N-type doping or ion implantation. As Figure 3 and Figure 4 shown, the depth of the deep N-type well DNW is less than the depth of the P-type well PWCO of the low-voltage transistor in the core region. The depth of the P-type well PWSW of the switching transistor is greater than the depth of the deep N-type well DNW. Thus, the depths of the P-type well PWCO of the low-voltage transistor in the core region and the P-type well PWSW of the switching transistor can be set to be the same, facilitating the use of the same doping process conditions for both.

[0043] For facilitating circuit connection, a source electrode is disposed on the surface of the source region, and a drain electrode is disposed on the surface of the drain region.

[0044] Similarly, a conductor block serving as a gate Gate is disposed on the upper surface of the deep N-type well region DNW. For example, a polysilicon gate is provided.

[0045] The N-type source region and the body region are isolated by a shallow trench isolation STI; the N-type drain region and the body region are isolated by a shallow trench isolation STI.

[0046] The doping concentration of the deep N-type well DNW is lower than the doping concentrations of the N-type source region and the N-type drain region. The deep N-type well DNW is provided so that the region in contact with the N+ regions of the source region and the drain region is also N-type, thereby reducing the junction capacitance.

[0047] The concentration of DNW is smaller relative to the concentration of the N+ regions of the source region and the drain region, making the PN junction depletion layer formed with the substrate wider and having higher breakdown voltage.

[0048] By performing heavy doping (ion implantation) on the upper part of the deep N-type well DNW, an N-type source region and an N-type drain region are formed. Ion implantation is to ionize the impurities to be doped into the semiconductor in an ion source, and then accelerate the selected ions after passing through a mass analysis magnetic pole and inject them into the substrate. For example, boron ions (B+3) are injected through the SiO2 film into the substrate to form a P-type well.

[0049] Preferably, when observed from a top view, a DNW ring is disposed around the outside of the body region, and the DNW ring and the body region are isolated by a shallow trench isolation STI.

[0050] The STI isolates a ring-shaped active region for ion implantation NWCO. After taking out the DNW, different voltage biases can be given.

[0051] Compared with the silicon-on-insulator radio frequency switch device structure, a deep N-type well (DNW) is provided between the device region and the P-type semiconductor substrate (PSUB). The P-type channel region is formed by a switching transistor P-type well (PWSW) that penetrates the deep N-type well (DNW), thereby avoiding the overall insertion of an insulating layer between the active layer and the substrate layer. It can be compatible with the existing bulk silicon process device platform and, like the silicon-on-insulator radio frequency switch device structure, achieves the purpose of significantly reducing the influence of the substrate capacitance on the device in the off state.

[0052] Compared with the existing SOI technology, the present utility model utilizes a high-resistance wafer plus deep well isolation. A PN junction is directly formed by the deep N-type well and the P substrate to play an isolation role. At the same time, deep trench isolation technology is used around the device. This structure can basically reach a level similar to that of SOI wafer isolated by a dielectric layer. In addition, only the channel region of the device well is implanted to reduce the contact area between the source / drain and the device well region, thereby reducing the radio frequency off capacitance. Based on the existing bulk silicon process, the present utility model only needs to change the implantation position of the device well region to significantly reduce the off capacitance under radio frequency signals. Other structures basically do not need to be changed, greatly reducing the process development cycle and cost.

[0053] The radio frequency switch device of the present utility model can be formed by the following process steps.

[0054] 1. First, perform deep N-type well region implantation to form DNW; DNW is a single piece at the bottom. This step does not involve the DNW ring (NWCO), and the DNW ring is a ring-shaped structure formed in the vertical direction.

[0055] 2. Prepare the processes related to the active region;

[0056] 3. Prepare the deep trench isolation structure, that is, form the STI structure. For example, dry etching can be used;

[0057] 4. Well region ion implantation, for example, form structures such as PWSW, PWCO, NWCO, etc.;

[0058] 5. Prepare the gate oxide and gate;

[0059] 6. LDD ion implantation, that is, the lightly doped drain region;

[0060] 7. Prepare the SPACER structure, the purpose is to pull the source / drain implantation farther away from the channel to reduce the influence;

[0061] 8. Source / drain ion implantation;

[0062] 9. ILD and the subsequent metal wiring process.

[0063] Thus, it can be manufactured in a manner compatible with the existing bulk silicon process.

[0064] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Those of ordinary skill in the art should understand that the technical solutions described in the foregoing embodiments can be modified, or some of the technical features can be equivalently replaced; these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A radio frequency switch device, characterized in that: include: P-type semiconductor substrate (PSUB); and a body region and a device region located above a P-type semiconductor substrate (PSUB), wherein, when viewed from a top view, the body region surrounds the device region; A core region low voltage tube P-type well (PWCO) is provided between the body region and the P-type semiconductor substrate (PSUB); A deep N-type well (DNW) is provided between the device region and the P-type semiconductor substrate (PSUB); The device region includes a P-type channel region, and an N-type source region and an N-type drain region respectively located on both sides of the P-type channel region; The P-type channel region is formed by a switch tube P-type well (PWSW) penetrating the deep N-type well (DNW), and the switch tube P-type well (PWSW) separates the deep N-type well (DNW) into two independent sub-regions, forming an N-type source region above one sub-region and forming an N-type drain region above the other sub-region.

2. The radio frequency switch device according to claim 1, characterized in that: The switch tube P-type well (PWSW) is only formed below the channel to reduce the contact area between the source and drain and the device well region, thereby reducing the RF turn-off capacitance.

3. The radio frequency switch device according to claim 1, characterized in that: The deep N-type well (DNW) is arranged on the P-type semiconductor substrate (PSUB), and its depth is smaller than the depth of the core area low voltage tube P-type well (PWCO).

4. The radio frequency switch device according to claim 1, characterized in that: The depth of the switch tube P-type well (PWSW) is greater than the depth of the deep N-type well (DNW).

5. The radio frequency switch device according to claim 1, characterized in that: A source electrode is arranged on the surface of the source region, and a drain electrode is arranged on the surface of the drain region.

6. The radio frequency switch device according to claim 1, characterized in that: A conductor block used as a gate is disposed on the upper surface of the deep N-type well (DNW).

7. The radio frequency switch device according to claim 1, characterized in that: The N-type source region is isolated from the body region by shallow trench isolation (STI); the N-type drain region is isolated from the body region by shallow trench isolation (STI).

8. The radio frequency switch device according to claim 1, characterized in that: The doping concentration of the deep N-type well (DNW) is lower than the doping concentrations of the N-type source region and the N-type drain region.

9. The radio frequency switch device according to claim 8, characterized in that: An N-type source region and an N-type drain region are formed by heavily doping the upper portion of the deep N-type well (DNW).

10. The radio frequency switch device according to claim 1, characterized in that: In a top view, a DNW ring is arranged around the body region, and the DNW ring is isolated from the body region by a shallow trench isolation (STI).

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