Waveform programmable signal generator based on FPGA

Abstract

The utility model discloses a waveform programmable signal generator based on an FPGA, comprising a digital circuit realized by the FPGA, a DAC chip peripheral circuit and an analog signal conditioning circuit, the digital circuit realized by the FPGA comprises a step length signal generation circuit, the input end of the step length signal generation circuit is connected with a frequency signal and a clock frequency, and the output end of the step length signal generation circuit is connected with a digital signal. The output end of the step length signal generating circuit is connected with the input end of the phase accumulator circuit, the output end of the phase accumulator circuit is connected with the input end of the phase amplitude meter circuit, and the output end of the phase amplitude meter circuit is connected with the input end of the signal amplitude adjusting circuit. The waveform generator is simple in structure, a digital circuit and an analog circuit are combined, that is, control signals of various needed analog waveforms are generated through the FPGA and sent to the DAC device, then post-stage conditioning is carried out through the analog circuit, and therefore the waveform generator with the programmable waveforms and the wide amplitude frequency range can be achieved.

Description

Technical Field

[0001] The utility model relates to the technical field of waveform generators, in particular to a waveform programmable signal generator based on FPGA. Background Art

[0002] Waveform generators have been widely used in various fields such as communication, control, and measurement. For example, sine waves, square waves, and sawtooth waves are often used in circuit design and debugging. With the development of electronic technology, digitalization is gradually becoming a development trend of the electronics industry, and companies are expanding their products in the direction of digitalization, miniaturization, and integration. Conventional waveform generators have limited waveform types and the amplitude and frequency range of the output signal are small, which cannot meet the increasingly complex circuit test scenarios. For this reason, a waveform programmable signal generator based on FPGA is proposed. Utility Model Content

[0003] The purpose of the utility model is to provide a waveform programmable signal generator based on FPGA to solve the problems raised in the above background technology.

[0004] To achieve the above-mentioned purpose, the utility model provides the following technical solutions: a waveform programmable signal generator based on FPGA, comprising a digital circuit implemented by FPGA, a DAC chip peripheral circuit and an analog signal conditioning circuit, wherein the digital circuit implemented by FPGA comprises a step signal generating circuit, the input end of the step signal generating circuit is connected to a frequency signal and a clock frequency, the output end of the step signal generating circuit is connected to the input end of a phase accumulator circuit, the output end of the phase accumulator circuit is connected to the input end of a phase amplitude table circuit, and the output end of the phase amplitude table circuit is connected to the input end of a signal amplitude adjustment circuit.

[0005] As a further solution of the utility model: the step signal generating circuit calculates the step signal m and transmits it to the phase accumulator circuit. The step signal m is obtained by the following formula: m=fout (output frequency)*2^28 / fclk (clock signal).

[0006] As a further solution of the utility model: the DAC chip peripheral circuit includes a reference voltage source circuit and an SPI interface communication circuit. The reference voltage source circuit input is a 5V DC power supply signal, and the output is a 2.5V reference power supply connected to the DAC chip. The SPI interface communication circuit pin is connected to the digital circuit pin implemented by FPGA, and the periodic digital code value generated by the digital circuit is transmitted through the SPI interface.

[0007] As a further solution of the utility model: the analog signal conditioning circuit includes a signal following circuit, a reference voltage generating circuit and a signal waveform amplifying circuit; the input end of the signal following circuit is connected to the voltage output end of the DAC chip, the input end of the reference voltage generating circuit is connected to the output end of the reference voltage source circuit, and the input end of the signal waveform amplifying circuit is connected to the output end of the signal following circuit and the output end of the reference voltage generating circuit.

[0008] As a further solution of the utility model: the digital circuit implemented by the FPGA transmits data to the DAC chip peripheral circuit through the SPI interface.

[0009] Compared with the prior art, the beneficial effect of the utility model is: by combining digital circuits with analog circuits, that is, generating control signals of various required analog waveforms to DAC devices through FPGA, and then performing post-stage conditioning through analog circuits, a waveform generator with programmable waveforms and a wide range of amplitude and frequency can be realized. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A schematic diagram of a digital circuit implemented by FPGA of the utility model;

[0011] Figure 2 This is a schematic diagram of the analog signal conditioning circuit of the utility model;

[0012] Figure 3 This is a schematic diagram of the peripheral circuit of the DAC chip of the utility model. DETAILED DESCRIPTION

[0013] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0014] See also Figure 1-3In an embodiment of the utility model, a waveform programmable signal generator based on FPGA includes a digital circuit implemented by FPGA, a DAC chip peripheral circuit and an analog signal conditioning circuit. The digital circuit implemented by FPGA includes a step signal generating circuit. The input end of the step signal generating circuit is connected to the frequency signal and the clock frequency. The output end of the step signal generating circuit is connected to the input end of the phase accumulator circuit. The output end of the phase accumulator circuit is connected to the input end of the phase amplitude table circuit. The output end of the phase amplitude table circuit is connected to the input end of the signal amplitude adjustment circuit. The digital circuit implemented by FPGA is used to generate digital code value data with adjustable amplitude, frequency and waveform type and transmit the digital code value data to the DAC chip through the SPI interface; the DAC chip peripheral circuit realizes the power supply of the DAC chip and the generation of a reference voltage source to ensure the normal operation of the DAC digital-to-analog converter; the analog signal conditioning circuit realizes the signal following and signal conditioning amplification functions.

[0015] See also Figure 1-3 In one embodiment, in this embodiment, preferably, the step signal generating circuit calculates the step signal m and transmits it to the phase accumulator circuit, and the step signal m is obtained by the following formula: m=fout (output frequency)*2^28 / fclk (clock signal).

[0016] Specifically, the step signal generating circuit calculates the step signal m through the input signal frequency parameters and clock frequency parameters according to the step formula: m=fout (output frequency)*2^28 / fclk (clock signal), and transmits it to the phase accumulator circuit. The phase accumulator circuit increases a step length m in each clock cycle according to the step signal, and generates an address signal to output to the phase amplitude table circuit; the phase amplitude table circuit outputs the waveform data content stored in advance to the signal amplitude adjustment circuit according to the address signal (the storage of the waveform data content is generated by the matlab code in the coe format file and then initialized and stored in the ROM memory; the signal amplitude adjustment circuit obtains the digital code value that the DAC chip needs to convert through the data output by the phase amplitude table and the configured signal amplitude parameters through multiplication operation, and the above The above content is prior art and can be queried through the public content on the Internet, source: https: / / zhuanlan.zhihu.com / p / 345641105 or https: / / blog.csdn.net / DengFengLai123 / article / details / 112104775); the phase amplitude table circuit stores the signal waveform data generated by the signal programming code through the ROM memory, and the signal programming code draws the data code value of one cycle of the generated signal through the matlab programming language. The data of one cycle contains 1024 data points, and each data point is 2 bytes; the signal waveform is flexibly adjusted through the matlab programming language and the programmability of the FPGA device.

[0017] See also Figure 3 In one embodiment, in this embodiment, preferably, the DAC chip peripheral circuit includes a reference voltage source circuit and an SPI interface communication circuit, the reference voltage source circuit input is a 5V DC power supply signal, and the output is a 2.5V reference power supply connected to the DAC chip, the SPI interface communication circuit pin is connected to the digital circuit pin implemented by the FPGA, and the periodic digital code value generated by the digital circuit is transmitted through the SPI interface. Specifically, the DAC chip peripheral circuit includes a reference voltage source chip, which outputs a 2.5V reference voltage to the DAC chip as a working reference; the SPI interface communication pin is connected to the FPGA pin, and the periodic digital code value generated by the digital circuit is transmitted through the SPI interface.

[0018] See also Figure 2 In one embodiment, in this embodiment, preferably, the analog signal conditioning circuit includes a signal following circuit, a reference voltage generating circuit and a signal waveform amplifying circuit; the input end of the signal following circuit is connected to the voltage output end of the DAC chip, the input end of the reference voltage generating circuit is connected to the output end of the reference voltage source circuit, and the input end of the signal waveform amplifying circuit is connected to the output end of the signal following circuit and the output end of the reference voltage generating circuit.

[0019] Specifically, the input of the signal follower circuit is the voltage output pin of the DAC chip, in order to perform impedance matching between the DAC voltage output signal and the subsequent circuit; the reference voltage generating circuit generates a constant 1.25V reference voltage through resistor voltage division and op amp following, in order to cooperate with the subsequent signal waveform amplification circuit to generate a bipolar periodic signal; the signal waveform amplification circuit first implements the signal's DC offset 1.25V function, and then implements the 5-fold amplification function of the signal amplitude, thereby outputting a signal waveform that meets the expected amplitude in the last stage.

[0020] See also Figure 1-3 In one embodiment, in this embodiment, preferably, the digital circuit implemented by the FPGA transmits data to the DAC chip peripheral circuit through the SPI interface.

[0021] Although this specification is described according to implementation modes, not every implementation mode includes only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

[0022] Therefore, the above description is only a preferred embodiment of the present application and is not intended to limit the scope of implementation of the present application; that is, all equivalent changes made according to the scope of the claims of the present application are within the protection scope of the claims of the present application.

Claims

1. A waveform programmable signal generator based on FPGA, characterized in that: The invention comprises a digital circuit implemented by FPGA, a DAC chip peripheral circuit and an analog signal conditioning circuit. The digital circuit implemented by FPGA comprises a step signal generating circuit. The input end of the step signal generating circuit is connected to a frequency signal and a clock frequency. The output end of the step signal generating circuit is connected to an input end of a phase accumulator circuit. The output end of the phase accumulator circuit is connected to an input end of a phase amplitude meter circuit. The output end of the phase amplitude meter circuit is connected to an input end of a signal amplitude regulating circuit.

2. The waveform programmable signal generator based on FPGA according to claim 1, characterized in that: The step signal generating circuit calculates the step signal m and transmits it to the phase accumulator circuit. The step signal m is obtained by the following formula: m=fout*2^28 / fclk.

3. The waveform programmable signal generator based on FPGA according to claim 1, characterized in that: The DAC chip peripheral circuit includes a reference voltage source circuit and an SPI interface communication circuit. The reference voltage source circuit inputs a 5V DC power supply signal and outputs a 2.5V reference power supply connected to the DAC chip. The pins of the SPI interface communication circuit are connected to the pins of the digital circuit implemented by the FPGA, and the periodic digital code values ​​generated by the digital circuit are transmitted through the SPI interface.

4. The waveform programmable signal generator based on FPGA according to claim 1, characterized in that: The analog signal conditioning circuit includes a signal following circuit, a reference voltage generating circuit and a signal waveform amplifying circuit; the input end of the signal following circuit is connected to the voltage output end of the DAC chip, the input end of the reference voltage generating circuit is connected to the output end of the reference voltage source circuit, and the input end of the signal waveform amplifying circuit is connected to the output end of the signal following circuit and the output end of the reference voltage generating circuit.

5. The waveform programmable signal generator based on FPGA according to claim 1, characterized in that: The digital circuit implemented by the FPGA transmits data to the DAC chip peripheral circuit through the SPI interface.

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