Electronic structure and electronic package

Abstract

The utility model relates to an electronic structure and an electronic packaging piece, which comprise the steps of supporting or fixing the electronic structure and the electronic packaging piece by utilizing a bearing piece and an adhesive layer, and supporting or fixing the electronic structure and the electronic packaging piece by utilizing double bearing pieces, thereby avoiding the warping problem of the electronic structure and the electronic packaging piece.

Description

Technical Field

[0001] The present application relates to electronic packaging technology, and in particular to an electronic structure and an electronic packaging component. Background Art

[0002] Figures 1A to 1D The cross-sectional view is a schematic diagram of a conventional method for manufacturing a semiconductor package.

[0003] First, if Figure 1A As shown, a carrier 16 and a packaging structure 19 are provided, and the packaging structure 19 is disposed with its lower side on the upper side of the carrier 16 .

[0004] Specifically, a bonding layer 161 is formed on the upper side of the carrier 16 by coating to serve as a sacrificial release layer. The packaging structure 19 is disposed on the bonding layer 161 .

[0005] The package structure 19 includes a first insulating layer 111, a first semiconductor chip 12, an adhesive layer 121, a conductive element 123, a second insulating layer 124, a conductive pillar 112, a first packaging glue 113, a redistribution layer 13, a second semiconductor chip 14, a first conductive bump 142, an underfill 143, and a second packaging glue 144. The redistribution layer 13 includes an insulating layer 131 and a circuit layer 132 combined with the insulating layer 131.

[0006] A plurality of electrode pads 122 are provided on the active surface of the upper side of the first semiconductor chip 12. The plurality of conductive elements 123 are bonded to the plurality of electrode pads 122. The second insulating layer 124 is provided on the active surface of each of the first semiconductor chips 12 and is located around the plurality of conductive elements 123. The first semiconductor chip 12 is bonded to the first insulating layer 111 by the adhesive layer 121 at the inactive surface on the lower side thereof. A plurality of conductive pillars 112 are provided around the first semiconductor chip 12. The first encapsulation colloid 113 covers the plurality of conductive pillars 112, the first semiconductor chip 12, the adhesive layer 121 and the second insulating layer 124. The redistribution layer 13 is provided on the upper side of the first semiconductor chip 12, the plurality of conductive elements 123, the second insulating layer 124, the plurality of conductive pillars 112 and the first encapsulation colloid 113.

[0007] The second semiconductor chip 14 has an upper non-active surface and a lower active surface, and the active surface has a plurality of electrode pads 141 to combine with a plurality of first conductive bumps 142. The second semiconductor chip 14 is flip-chip bonded to the upper side of the redistribution layer 13 through the electrode pads 141 and the first conductive bumps 142. The bottom glue 143 covers the plurality of first conductive bumps 142. The second encapsulation glue 144 is disposed on the upper side of the redistribution layer 13 and covers the second semiconductor chip 14 and the bottom glue 143.

[0008] like Figure 1B As shown, the carrier 16 and the bonding layer 161 are removed, the package structure 19 is turned upside down, and then an under bump metallurgy (UBM) 151 and a plurality of second conductive bumps 152 are formed on the upper side thereof.

[0009] like Figure 1C As shown, the packaging structure 19 is ground to remove a portion of the second packaging resin 144 and the second semiconductor chip 14 and expose the second semiconductor chip 14 .

[0010] Figures 1A to 1C The conventional semiconductor structure 1 shown is a large-format semiconductor structure. In other words, the semiconductor structure 1 includes a plurality of packaging structures 19, and Figures 1A to 1C The manufacturing method shown is a method for manufacturing multiple packaging structures 19 simultaneously. Figures 1A to 1C After the manufacturing process shown, the large-format semiconductor structure 1 can be cut into a plurality of individual semiconductor packages 100, such as Figure 1D shown.

[0011] However, in the application of the central processing unit (CPU) of a thin notebook computer, the height restriction restricts the conventional semiconductor package 100 to be extremely thin, and it is easy to cause significant warpage after the carrier 16 is removed, resulting in difficulty in the subsequent process of forming the second conductive bump 152 and the grinding operation.

[0012] Therefore, how to overcome the above-mentioned problems of the prior art has become a topic that needs to be solved urgently. Utility Model Content

[0013] To solve the above problems, the present application provides an electronic structure, including a packaging module having a wiring section and a component section and a component side carrier. The wiring section has a first side and a second side opposite to each other, and includes a first electronic component and a redistribution layer. The component section has a first side and a second side opposite to each other, and its second side is arranged on the first side of the wiring section, and includes a second electronic component. The redistribution layer electrically connects the first electronic component and the second electronic component. The component side carrier has a first side and a second side opposite to each other, and its second side is arranged on the first side of the component section.

[0014] The present application further provides an electronic package, comprising a packaging module defining a wiring section and a component section, a conductive bump, and an adhesive layer. The wiring section has a first side and a second side opposite to each other, and comprises a first electronic component and a redistribution layer. The component section has a first side and a second side opposite to each other, and its second side is arranged on the first side of the wiring section, and comprises a second electronic component. The conductive bump is arranged on the second side of the wiring section, and the redistribution layer electrically connects the first electronic component and the second electronic component. The adhesive layer is arranged on the second side of the wiring section to cover the conductive bump.

[0015] The present application also provides a method for manufacturing an electronic package, comprising: providing a wiring side carrier and a packaging module, wherein the packaging module is defined with a wiring section and a component section, the wiring side carrier, the wiring section and the component section each having a first side and a second side opposite to each other, the component section being arranged with its second side on the first side of the wiring section; arranging the packaging module with the second side of the wiring section on the first side of the wiring side carrier; and arranging the component side carrier having a first side and a second side opposite to each other with its second side on the first side of the component section.

[0016] The present application utilizes a carrier and an adhesive layer to support or fix the electronic structure and the electronic package, and utilizes a double carrier to support or fix the electronic structure and the electronic package, thereby avoiding the warping problem of the electronic structure and the electronic package. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figures 1A to 1D The cross-sectional view is a schematic diagram of a conventional method for manufacturing a semiconductor package.

[0018] FIG. 2A to FIG. 2E It is a cross-sectional schematic diagram of a method for manufacturing an electronic package according to a first embodiment of the present application.

[0019] Figure 3A and Figure 3B It is a cross-sectional schematic diagram of a method for manufacturing an electronic package according to a second embodiment of the present application.

[0020] Main component symbols

[0021] 1 Semiconductor structure

[0022] 100 Semiconductor Packages

[0023] 111 First insulation layer

[0024] 112 Conductive column

[0025] 113 First Encapsulation Colloid

[0026] 12 First Semiconductor Chip

[0027] 121 Adhesive layer

[0028] 122 electrode pads

[0029] 123 Conductive elements

[0030] 124 Second insulation layer

[0031] 13 Redistribution Layer

[0032] 131 Insulation layer

[0033] 132 Line Layer

[0034] 14. Second semiconductor chip

[0035] 141 Electrode pads

[0036] 142 first conductive bump

[0037] 143 Primer

[0038] 144 Second packaging colloid

[0039] 151 Under Bump Metal

[0040] 152 second conductive bump

[0041] 16 Bearing

[0042] 161 Binding layer

[0043] 19 Package Structure

[0044] 2,3 Electronic structure

[0045] 200,300 Electronic packaging

[0046] 211 First insulation layer

[0047] 212 Conductive column

[0048] 213 First coating layer

[0049] 22 First Electronic Components

[0050] 221 Adhesive layer

[0051] 222 Electrode pads

[0052] 223 Conductive components

[0053] 224 Second insulation layer

[0054] 23 Redistribution Layer

[0055] 231 Insulation layer

[0056] 232 Line Layer

[0057] 24 Second electronic component

[0058] 241 Electrode pads

[0059] 242 first conductive bump

[0060] 243 Primer

[0061] 244 Second coating layer

[0062] 251 Under Bump Metal

[0063] 252 second conductive bump

[0064] 26 Wiring side support

[0065] 261 Wiring side bonding layer

[0066] 27 Component side bearing

[0067] 271 Component side bonding layer

[0068] 28 glue layer

[0069] 29 Packaging Module

[0070] 291 Wiring Sections

[0071] 292 Component section. DETAILED DESCRIPTION

[0072] The following describes the implementation methods of the present application through specific embodiments. A person having ordinary knowledge in the technical field can easily understand other advantages and effects of the present application from the contents disclosed in this specification.

[0073] FIG. 2A to FIG. 2E It is a cross-sectional schematic diagram of a method for manufacturing an electronic package according to a first embodiment of the present application.

[0074] First, if Figure 2A As shown, a wiring side carrier 26 and a packaging module 29 are provided, wherein the packaging module 29 is defined with a wiring section 291 and a component section 292 , the component section 292 is disposed on the wiring section 291 , and the thickness of the component section 292 is greater than the thickness of the wiring section 291 .

[0075] FIG. 2A to FIG. 2E All components, such as the packaging module 29, the wiring section 291, the component section 292, the wiring side carrier 26, and other components, have a first side and a second side opposite to each other, wherein the first side refers to FIG. 2A to FIG. 2C The upper side of Figure 2D and Figure 2E In contrast, the second side refers to FIG. 2A to FIG. 2CThe lower side of Figure 2D and Figure 2E The component section 292 is disposed at the first side of the wiring section 291 with its second side, and the entire packaging module 29 is disposed at the first side of the wiring side carrier 26 with the second side of the wiring section 291 .

[0076] Specifically, a wiring side bonding layer 261 having a release film or other adhesive film is formed on the first side of the wiring side carrier 26 by coating, wherein the wiring side bonding layer 261 serves as a sacrificial release layer. The packaging module 29 is disposed on the first side of the wiring side bonding layer 261 with the second side of the wiring section 291.

[0077] The wiring section 291 of the package module 29 includes a first insulating layer 211 , at least one first electronic component 22 (two first electronic components 22 are shown in this embodiment), an adhesive layer 221 , a plurality of conductive components 223 , a second insulating layer 224 , a plurality of conductive pillars 212 , a first encapsulating layer 213 , and a redistribution layer 23 .

[0078] The material forming the first insulating layer 211 may be polybenzoxazole (PBO), polyimide (PI), prepreg (PP) or other dielectric materials.

[0079] Each of the first electronic components 22 can be an active component, a passive component or a combination thereof, wherein the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor, and an inductor.

[0080] The conductive element 223 may be made of copper or other conductive materials, and the second insulating layer 224 may be made of poly(p-oxadiazole) (PBO), polyimide (PI), prepreg (PP) or other dielectric materials.

[0081] The conductive pillars 212 may be made of copper or other conductive materials.

[0082] The first coating layer 213 is made of an insulating material, such as polyimide (PI) or epoxy resin packaging colloid or packaging material. The first coating layer 213 can be formed by molding, lamination or coating.

[0083] The redistribution layer 23 includes at least one insulating layer 231 and at least one circuit layer 232 combined with the insulating layer 231. The circuit layer 232 may be made of copper or other conductive materials, and the insulating layer 231 may be made of poly(p-oxadiazole) (PBO), polyimide (PI), prepreg (PP) or other dielectric materials.

[0084] A plurality of electrode pads 222 are provided on the active surface of the first side of each of the first electronic components 22. The plurality of conductive components 223 are bonded to the plurality of electrode pads 222. The second insulating layer 224 is provided on the active surface of each of the first electronic components 22 and is provided around the conductive components 223. The non-active surface of the second side of each of the first electronic components 22 is bonded to the first side of the first insulating layer 211 through the adhesive layer 221. The conductive pillar 212 is provided on the first side of the first insulating layer 211 and is provided around the first electronic components 22. The first encapsulating layer 213 encapsulates the conductive pillar 212, the first electronic components 22, the adhesive layer 221 and the second insulating layer 224. The redistribution layer 23 is provided on the first side of the first electronic components 22, the conductive components 223, the second insulating layer 224, the conductive pillar 212 and the first encapsulating layer 213.

[0085] The component section 292 of the package module 29 includes at least one second electronic component 24, a plurality of first conductive bumps 242, an underfill 243, and a second encapsulating layer 244. The underfill 243 encapsulates the first conductive bumps 242. The second encapsulating layer 244 is disposed on the first side of the redistribution layer 23 and encapsulates the second electronic component 24 and the underfill 243.

[0086] The second electronic component 24 can be an active component, a passive component or a combination thereof, and the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor and an inductor. The second electronic component 24 has a non-active surface on a first side and an active surface on a second side. The active surface has a plurality of electrode pads 241 to combine with a plurality of first conductive bumps 242.

[0087] Each of the first conductive bumps 242 can be formed of a solder material or a conductive metal material. The second electronic component 24 is flip-chip bonded to the first side of the redistribution layer 23 through the electrode pads 241 on its active surface and the first conductive bumps 242 to electrically connect the circuit layer 232 of the redistribution layer 23. For example, a primer 243 can be used to cover the plurality of first conductive bumps 242.

[0088] The second coating layer 244 is made of insulating material, such as polyimide (PI), epoxy resin or packaging material. The second coating layer 244 can also be formed by molding, lamination or coating.

[0089] The conductive pillar 212 is electrically connected to the circuit layer 232 of the redistribution layer 23. The circuit layer 232 of the redistribution layer 23 is electrically connected to each first electronic component 22 through the conductive element 223 and the electrode pad 222 of the first electronic component 22. In addition, the circuit layer 232 of the redistribution layer 23 is electrically connected to the second electronic component 24 through the first conductive bump 242 and the electrode pad 241 of the second electronic component 24. Thus, the conductive pillar 212 is electrically connected to the first electronic component 22 and the second electronic component 24.

[0090] like Figure 2B As shown, the upper end of the packaging module 29 is ground to remove a portion of the second coating layer 244 and the second electronic component 24 , and to expose the second electronic component 24 .

[0091] like Figure 2C As shown, a device side support 27 is provided, and the device side support 27 is disposed with its second side on the first side of the device section 292. At this time, an external force must be applied to allow the device side support 27 to be combined with the packaging module 29.

[0092] Specifically, a component side bonding layer 271 having a release film or other adhesive film is formed on the second side of the component side carrier 27 by coating, for example, wherein the component side bonding layer 271 serves as a sacrificial release layer. The packaging module 29 is disposed with the first side of the component section 292 on the second side of the component side bonding layer 271, so as to be sandwiched between the wiring side carrier 26 and the component side carrier 27.

[0093] like Figure 2D As shown, the wiring side carrier 26 and the wiring side bonding layer 261 are removed, and then an under bump metallurgy (UBM) 251 and a plurality of second conductive bumps 252 are formed on the second side of the wiring section 291. The under bump metallurgy 251 may be partially formed in the first insulating layer 211.

[0094] The under bump metal layer 251 can be made of a conductive metal material. Each of the second conductive bumps 252 can be formed of a solder material or a conductive metal material.

[0095] The second conductive bump 252 is electrically connected to the conductive pillar 212 through the UBM layer 251 . Thus, the second conductive bump 252 is electrically connected to the first electronic component 22 and the second electronic component 24 .

[0096] like Figure 2E As shown, the element-side bearing member 27 and the element-side bonding layer 271 are removed.

[0097] FIG. 2A to FIG. 2D The electronic structure 2 shown is a large-format electronic structure. In other words, the electronic structure 2 includes a plurality of packaging modules 29, and FIG. 2A to FIG. 2DThe manufacturing method shown is a method for manufacturing a plurality of packaging modules 29 simultaneously, so at this stage, the large-format electronic structure 2 can be cut into a plurality of separate electronic packages 200 .

[0098] Figure 3A and Figure 3B It is a cross-sectional schematic diagram of a method for manufacturing an electronic package according to a second embodiment of the present application.

[0099] First, continue FIG. 2A to FIG. 2D The method shown, such as Figure 3A As shown, a glue layer 28 is formed on the second side of the wiring section 291 so that the glue layer 28 covers the second conductive bump 252 .

[0100] Then, if Figure 3B As shown, the element-side bearing member 27 and the element-side bonding layer 271 are removed.

[0101] Figure 3A The electronic structure 3 shown is also a large-format electronic structure. Therefore, at this stage, the large-format electronic structure 3 can be cut into a plurality of individual electronic packages 300 .

[0102] The electronic structures 2 and 3 of the present application are optimized by process. Figure 2B During the grinding process shown in the figure, the wiring side carrier 26 is still provided. The fixing function of the wiring side carrier 26 can reduce the occurrence of warpage, and the component side carrier 27 is provided after grinding to further reduce the warpage of the electronic package 200, 300. In addition, the provision of the adhesive layer 28 can avoid the warpage problem caused by the removal of the component side carrier 27. Therefore, the electronic package 200, 300 of the present application will not be warped significantly, which is helpful for wafer handling and process operations.

[0103] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone with ordinary knowledge in the art may modify and change the above embodiments without violating the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be as set forth in the claims.

Claims

1. An electronic structure, characterized in that include: A packaging module, which is defined with a wiring section and a component section disposed on the wiring section, wherein the wiring section has a first side and a second side opposite to each other, and includes a first electronic component and a redistribution layer, and the component section has a first side and a second side opposite to each other, and includes a second electronic component, and the second side of the component section is disposed on the first side of the wiring section, and the redistribution layer is electrically connected to the first electronic component and the second electronic component; as well as The component side bearing member has a first side and a second side opposite to each other, and the second side is arranged on the first side of the component section.

2. The electronic structure according to claim 1, characterized in that The thickness of the device section is greater than the thickness of the wiring section.

3. The electronic structure according to claim 1, characterized in that The electronic structure includes: The wiring side bearing member is arranged on the second side of the wiring section.

4. The electronic structure according to claim 1, characterized in that The electronic structure includes: A conductive bump is disposed on the second side of the wiring section; and The conductive pillar is embedded in the wiring section and electrically connects the conductive bump and the redistribution layer.

5. The electronic structure according to claim 4, characterized in that The electronic structure includes: The adhesive layer is disposed on the second side of the wiring section to cover the conductive bump.

6. An electronic package, characterized in that: include: A packaging module, which is defined with a wiring section and a component section disposed on the wiring section, wherein the wiring section has a first side and a second side opposite to each other, and includes a first electronic component and a redistribution layer, and the component section has a first side and a second side opposite to each other, and includes a second electronic component, and the second side of the component section is disposed on the first side of the wiring section, and the redistribution layer is electrically connected to the first electronic component and the second electronic component; A conductive bump is disposed on the second side of the wiring section; and The adhesive layer is disposed on the second side of the wiring section to cover the conductive bump.

7. The electronic package according to claim 6, wherein: The thickness of the device section is greater than the thickness of the wiring section.

Images