Packaging structure
By using solder balls with high melting point cores between the packaging substrate and the chip structure, the problem of tin defects in the packaging process of artificial intelligence chips is solved, the performance and reliability of the packaging structure are improved, and the production yield is improved.
Patent Information
- Application Number
- CN202520797449.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-25
- Publication Date
- 2025-06-06
- Estimated Expiration
- 2035-04-25
AI Technical Summary
During the packaging process of artificial intelligence chips, due to warping and stress accumulation of large-sized chips or multi-chip modules, tin defects are prone to occur, affecting the performance and reliability of the chip.
Solder balls with internal cores with higher melting points than tin are used to solder between the packaging substrate and the chip structure, and the structural stability of the core is used to reduce the lateral expansion of the solder balls, thereby reducing the risk of tin connection.
By using solder balls with high melting point cores, the occurrence of tin connection is effectively reduced, the performance and reliability of the packaging structure are improved, and the yield of production is improved.
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Figure CN222953084U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor packaging technology, and in particular to a packaging structure. Background Art
[0002] Artificial intelligence chip (AI chip) is an integrated circuit designed specifically for artificial intelligence (AI) applications. As the computing power of artificial intelligence chips increases exponentially, more chips are needed to form core particles, so the ball grid array package (BGA) technology is derived, and the chip is soldered to the circuit board through BGA to form a control circuit board. As the size of the chiplet, CoW module (Chip on Wafer) or interposer becomes larger and larger, during the C4 bump (Flipchip) welding process, due to the superposition of various warping effects, bridge defects are prone to occur. Bridge defects can cause poor electrical connection between the chip and the substrate, affecting the performance and reliability of the chip. This problem is particularly prominent in large-size chips or multi-chip modules because the larger area increases the cumulative effect of warping and stress. In addition, with the increase in chip functions and the improvement in integration, the number and density of solder joints are also increasing, which further increases the risk of bridge occurrence. Utility Model Content
[0003] To solve the above problems, the present application provides a packaging structure, which can effectively reduce the occurrence of tin bridging by using a solder ball with a core having a higher melting point than tin between the packaging substrate and the chip structure, thereby improving the performance and reliability of the packaging structure and improving the production yield.
[0004] The technical solution adopted for this purpose is a packaging structure, including:
[0005] A packaging substrate, a plurality of first connection structures and a chip structure;
[0006] The first connection structure includes a first substrate pad, a first solder ball and a first conductive terminal, wherein the first substrate pad is arranged in a first welding area of the packaging substrate, the first conductive terminal is arranged on a surface of the chip structure facing the packaging substrate, the first solder ball is connected between the first substrate pad and the first conductive terminal, and the first solder ball has a core with a higher melting point than tin.
[0007] In a preferred embodiment of the present application, it can be further configured that the inner core of the first solder ball is a copper ball core.
[0008] In a preferred embodiment of the present application, it can be further configured to further include: a plurality of second connection structures;
[0009] The second connection structure includes a second substrate pad, a second solder ball and a second conductive terminal, wherein the second substrate pad is arranged on a second welding area of the packaging substrate, the second conductive terminal is arranged on a surface of the chip structure facing the packaging substrate, the second solder ball is connected between the second substrate pad and the second conductive terminal, and the second solder ball is a tin ball.
[0010] In a preferred embodiment of the present application, it can be further configured that the first solder ball is ellipsoidal, and the length of the major axis of the first solder ball is The particle size of the copper core is ,satisfy .
[0011] In a preferred embodiment of the present application, it can be further configured that the particle size of the copper ball core is satisfy: .
[0012] In a preferred embodiment of the present application, it can be further configured that the melting point of the tin alloy in the first solder ball is 150° C. to 260° C.
[0013] In a preferred embodiment of the present application, it can be further configured as follows:
[0014] The distance between adjacent first substrate pads on the first welding area is ,in ;
[0015] The spacing between adjacent second substrate pads on the second welding area is ,in .
[0016] In a preferred embodiment of the present application, it can be further configured to further include a bottom filling layer, wherein the bottom filling layer is arranged on the surface of the packaging substrate close to the chip structure, and the bottom filling layer is used to fill the gap between the packaging substrate and the chip structure.
[0017] In a preferred embodiment of the present application, it can be further configured to further include: a third conductive terminal, wherein the third conductive terminal is arranged on a surface of the packaging substrate on a side away from the chip structure.
[0018] In a preferred embodiment of the present application, it can be further configured to further include: a reinforcement structure, which is arranged at the periphery of the welding area on the surface of the packaging substrate facing the chip structure.
[0019] In summary, compared with the prior art, the beneficial effects brought by the technical solution provided by the embodiment of the present application include at least the following: the packaging structure proposed in the present application includes a packaging substrate, a plurality of first connection structures and a chip structure; the first connection structure includes a first substrate pad, a first solder ball and a first conductive terminal, wherein the first substrate pad is arranged in a first welding area of the packaging substrate, the first conductive terminal is arranged on the surface of the chip structure facing the packaging substrate, the first solder ball is connected between the first substrate pad and the first conductive terminal, and the first solder ball has a core with a higher melting point than tin. By arranging a solder ball with a core with a higher melting point than tin between the packaging substrate and the chip structure, the structural stability of the core can be utilized to effectively reduce the risk of solder balls being connected due to external expansion during welding in a dense ball grid array, and the performance and reliability of the packaging structure can be improved. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 A schematic cross-sectional view of a package structure in which solder bonding occurs provided by an exemplary embodiment of the present application;
[0021] Figure 2 A schematic cross-sectional view of a packaging structure provided for yet another exemplary embodiment of the present application;
[0022] Figure 3 A schematic top view of a packaging substrate provided for another exemplary embodiment of the present application;
[0023] Figure 4 A schematic top view of a packaging substrate provided for yet another exemplary embodiment of the present application;
[0024] Figure 5 A schematic structural diagram of a first solder ball provided for yet another exemplary embodiment of the present application;
[0025] Figure 6 A schematic cross-sectional view of a packaging structure provided for yet another exemplary embodiment of the present application;
[0026] Figure 7 A schematic top view of a packaging substrate provided for yet another exemplary embodiment of the present application;
[0027] Figure 8 A schematic cross-sectional view of a packaging structure provided for yet another exemplary embodiment of the present application;
[0028] Fig. 9 A schematic cross-sectional view of a packaging structure provided for yet another exemplary embodiment of the present application;
[0029] Fig.10 A schematic cross-sectional view of a packaging structure provided for yet another exemplary embodiment of the present application;
[0030] Fig.11 A schematic cross-sectional view of a chip structure provided for yet another exemplary embodiment of the present application. DETAILED DESCRIPTION
[0031] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0032] In the description of the present application, it should be understood that the technical terms or scientific terms used in the present application should be the common meaning understood by technicians with general skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present application do not indicate any order, quantity or importance, but are only used to distinguish different components. "Including" or "comprising" and similar words mean that the elements or objects appearing in front of the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. When the number of a component or element is not particularly indicated in the following of the present application's disclosed embodiments, it means that the component or element can be one or more, or can be understood as at least one. "At least one" refers to one or more, and "multiple" refers to at least two.
[0033] The directions and positional relationships indicated by “center”, “longitudinal”, “lateral”, “up”, “down”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counterclockwise”, etc. used in the embodiments disclosed in this application are based on the directions or positional relationships shown in the accompanying drawings and are only for the convenience of describing this application and simplifying the description, and therefore should not be understood as limiting this application.
[0034] Ball grid array packaging technology has been widely used in the field of artificial intelligence chips. However, with the increase in chip size and the accumulation of warping during the welding process, bridging defects have become a problem that needs to be solved. Bridging can lead to poor electrical connection between the chip and the substrate, affecting the performance and reliability of the chip.
[0035] Chip on Wafer on Substrate (CoWoS) packaging is an advanced packaging technology that can achieve high-density line connections between multiple chips, thereby achieving high-speed data transmission. The CoWoS packaging structure includes a CoW module and a packaging substrate, and the CoW module can be installed on the packaging substrate through a welding process. However, as the size of the core particle or CoW module becomes larger and larger, when the CoW module is welded to the packaging substrate, due to the inconsistency of the thermal expansion coefficients between different materials in the CoW module, warping occurs at high temperatures, and bridging defects are prone to occur, thereby affecting the packaging yield.
[0036] For example, Figure 1 A schematic cross-sectional view of a package structure in which solder joint occurs is shown. Figure 1 The packaging structure includes a substrate 10, a chip module 20 and a plurality of connectors 30, wherein each connector 30 includes a first pad 301 disposed on the substrate 10, a second pad 302 disposed on the chip module 20 and a solder ball 303 between the two pads. In the process of installing the chip module 20 on the substrate 10, the chip module 20 is warped due to the high temperature conditions of the packaging process and the superimposed influence of the melting change of the solder balls in the connector, resulting in a smaller spacing between adjacent connectors, which may cause bridging. For example, after welding is completed, the solder balls in the two adjacent connectors 30 at M1 are connected together, and the solder balls in the two adjacent connectors 30 at M2 are connected together, resulting in poor electrical connection between the chip and the substrate, affecting the device performance and reliability of the packaging structure.
[0037] In view of the above problems, in an exemplary embodiment of the present application, a packaging structure is provided, which can avoid or reduce the risk of bridging, improve the packaging yield, and improve the device performance and reliability.
[0038] The packaging structure of the embodiment of the present application includes: a packaging substrate, a plurality of first connection structures and a chip structure; the first connection structure includes a first substrate pad, a first solder ball and a first conductive terminal, wherein the first substrate pad is arranged in a first welding area of the packaging substrate, the first conductive terminal is arranged on the surface of the chip structure close to the packaging substrate, the first solder ball is connected between the first substrate pad and the first conductive terminal, wherein the first solder ball has a core with a higher melting point than tin.
[0039] In the embodiment of the present application, a solder ball having a core with a melting point higher than that of tin is arranged between the packaging substrate and the chip structure, and the high melting point and supporting function of the core are utilized to reduce the lateral expansion of the solder ball during the welding process, thereby reducing the occurrence of tin bridging, which is beneficial to improving the reliability of the packaging structure and the device performance.
[0040] Figure 2A cross-sectional schematic diagram of the packaging structure disclosed in an embodiment of the present application is shown.
[0041] Reference Figure 2 In some embodiments, the packaging structure specifically includes:
[0042] A packaging substrate 1, a plurality of first connection structures 3 and a chip structure 2. The packaging substrate 1 has two relatively parallel surfaces along a first direction X1: a first surface S1 and a second surface S2, and the second direction X2 is perpendicular to the first direction X1. One end of the first connection structure 3 is connected to the first surface S1 of the packaging substrate 1, and the other end of the first connection structure 3 is connected to the surface of the chip structure 2 facing the packaging substrate 1. A first welding area R1 is provided on the first surface S1 of the packaging substrate 1, and the area of the first welding area R1 is less than or equal to the projected area of the chip structure 2 on the packaging substrate 1. Specifically, one end of the first connection structure 3 is welded in the first welding area R1 of the first surface S1 of the packaging substrate 1, and the other end of the first connection structure 3 is welded on the surface of the chip structure 2 facing the packaging substrate 1.
[0043] In some embodiments, the packaging substrate 1 is an organic substrate or a double-sided copper-clad organic substrate.
[0044] The first connection structure 3 connects the chip structure 2 with the package substrate 1, so that the chip structure 2 can transmit signals with external devices, realize electrical connection between the chip structure 2 and external devices, and enable the chip structure 2 to work normally. The first connection structure 3 is made of a material with good conductivity.
[0045] Continue to refer to Figure 2 As shown, the first connection structure 3 includes a first substrate pad 31, a first solder ball 33 and a first conductive terminal 32 connected in sequence; the first substrate pad 31 is distributed in the first welding area R1 of the package substrate 1, the first conductive terminal 32 is arranged on the surface of the chip structure 2 facing the package substrate 1, one end of the first solder ball 33 is connected to the first substrate pad 31, and the other end of the first solder ball 33 is connected to the first conductive terminal 32. The center of the first substrate pad 31 and the center of the first conductive terminal 32 are aligned in a direction perpendicular to the first surface S1 of the package substrate 1.
[0046] The first solder ball 33 connects the package substrate 1 and the chip structure 2 through the first substrate pad 31 and the first conductive terminal 32, so as to realize signal transmission and current flow between the chip structure 2 and the package substrate 1. The first solder ball 33 has a core with a higher melting point than tin. Compared with conventional tin balls, the first solder ball 33 can reduce the lateral expansion of the solder ball during the welding process by utilizing the supporting function of the core, thereby reducing the risk of solder bridging during the welding process.
[0047] Among them, the first substrate pad 31 is made of a material with good conductivity and corrosion resistance, such as copper, gold, etc. The first substrate pad 31 can be flexibly set to a circular, square, elliptical, rectangular or other shape.
[0048] The first conductive terminal 32 is made of a material with good conductivity and corrosion resistance, such as copper, gold, etc. The first conductive terminal 32 can be flexibly set to a circular, square, oval, rectangular, etc. shape.
[0049] It should be noted that the first substrate pad 31 and the first conductive terminal 32 can be set to the same shape or different shapes according to product requirements. For example, the first substrate pad 31 and the first conductive terminal 32 are both set to be circular; or the first substrate pad 31 is set to be circular, and the first conductive terminal 32 is set to be square.
[0050] The layout of the first substrate pads 31 on the package substrate 1 can be arranged at equal intervals between adjacent substrate pads, or can be arranged in a cross arrangement. At the same time, the layout of the first conductive terminals 32 on the surface of the chip structure is the same as the layout of the first substrate pads 31 on the package substrate 1. That is, when the first substrate pads 31 are arranged at equal intervals on the package substrate 1, the first conductive terminals 32 are also arranged at equal intervals on the chip structure; when the first substrate pads 31 are arranged at a cross arrangement on the package substrate 1, the first conductive terminals 32 are also arranged in a cross arrangement on the chip structure.
[0051] For example, refer to Figure 3 , which is a schematic top view of the surface of the package substrate 1. The first substrate pads 31 are distributed in the first welding area R1 on the surface of the package substrate 1. Exemplarily, the first substrate pads 31 are circular, and adjacent first substrate pads 31 are arranged at equal intervals. Among them, the two first substrate pads in the first row (L1) and the two first substrate pads in the second row (L2) are arranged in a rectangular shape.
[0052] For example, refer to Figure 4 , which is a schematic top view of the surface of the package substrate 1. The first substrate pads 31 are distributed in the first welding area R1 on the surface of the package substrate 1. Exemplarily, the first substrate pads 31 are circular, and the first substrate pads 31 in adjacent rows are arranged crosswise. Among them, the two first substrate pads in the first row (L1) and one first substrate pad in the second row (L2) are arranged in a triangle.
[0053] In some embodiments, the core of the first solder ball 33 is a copper ball core. Figure 5As shown, the first solder ball 33 is composed of an internal copper ball core 331 and an external tin layer 332, that is, the core is copper with a higher melting point than tin. The tin layer 332 of the first solder ball 33 is connected to the first substrate pad 31 and the first conductive terminal 32. It should be noted that the first solder ball 33 is ellipsoidal as a whole, and the internal copper ball core 331 is spherical, and the copper ball core 331 is close to one end of the first substrate pad 31. The first solder ball adopts a composite structure of "copper ball core-tin layer", which is intended to use the copper ball core to be much higher than the melting point of tin. In the subsequent processing, the external tin layer melts and forms an intermetallic compound with the conductive terminal at the substrate pad and the chip structure end to achieve electrical connection. The internal copper ball core can maintain rigidity, provide mechanical support, and effectively avoid the lateral expansion of the entire solder ball. The internal copper ball core can maintain the solder ball height and the spacing between adjacent solder balls during the subsequent processing, avoiding the risk of solder ball collapse and tin connection.
[0054] In some embodiments, reference Figure 6 As shown, the packaging structure also includes a plurality of second connection structures 4, one end of the second connection structure 4 is connected to the second welding area R2 of the first surface S1 of the packaging substrate 1, and the other end of the second connection structure 4 is connected to the surface of the chip structure 2 facing the packaging substrate 1. The first connection structure 3 is connected to the first welding area R1 of the packaging substrate 1, and the second connection structure 4 is connected to the second welding area R2 of the packaging substrate 1. It should be noted that the second welding area R2 does not overlap with the first welding area R1. The second welding area R2 can be arranged at the periphery of the first welding area R1, or it can be arranged inside the first welding area R1. The first connection structure 3 and the second connection structure 4 together serve as an intermediate connection member to connect the packaging substrate 1 and the chip structure 2. The distribution density of the second connection structure 4 in the second welding area R2 is less than the distribution density of the first connection structure 3 in the first welding area R1.
[0055] Continue to refer to Figure 6 As shown, the second connection structure 4 includes a second substrate pad 41, a second solder ball 43 and a second conductive terminal 42 connected in sequence. The second substrate pad 41 is distributed on the second welding area R2 of the package substrate 1, and the second conductive terminal 42 is arranged on the surface of the chip structure 2 facing the package substrate 1; one end of the second solder ball 43 is connected to the surface of the second substrate pad 41 away from the package substrate 1, and the other end is connected to the surface of the second conductive terminal 42 away from the chip structure 2. The second solder ball 43 connects the package substrate 1 and the chip structure 2 through the second substrate pad 41 and the second conductive terminal 42, so as to realize signal transmission and current flow between the chip structure 2 and the package substrate 1. The second solder ball 43 is a tin ball. In the second welding area R2, a conventional tin ball is selected. The welding process is relatively easy to control, the quality of the solder joint is stable and reliable, and the cost can be reduced at the same time.
[0056] Among them, the second substrate pad 41 is made of a material with good conductivity, corrosion resistance and weldability, such as copper, gold, etc., and the second conductive terminal 42 is made of a material with good conductivity, corrosion resistance and weldability, such as copper, gold, etc. The second substrate pad 41 and the second conductive terminal 42 can be made of the same material or different materials. The second substrate pad 41 can be set to a circular, square, elliptical, rectangular or other shape according to product requirements; the second conductive terminal 42 can also be set to a circular, square, elliptical, rectangular or other shape according to product requirements. It should be noted that the second substrate pad 41 and the second conductive terminal 42 can be set to the same shape or different shapes. For example, the second substrate pad 41 and the second conductive terminal 42 are both set to circular; or the second substrate pad 41 is set to circular and the second conductive terminal 42 is set to square; or the second substrate pad 41 is set to square and the second conductive terminal 42 is set to circular.
[0057] In some embodiments, reference Figure 7 , which is a schematic top view of the surface of the package substrate 1. A first welding area R1 is provided on the first surface S1 of the package substrate 1, and a second welding area R2 is provided at the periphery of the first welding area, and the second welding area R2 does not overlap with the first welding area R1. A first substrate pad 31 is connected in the first welding area R1, and a second substrate pad 41 is connected in the second welding area R2. The adjacent spacing between the second substrate pads 41 is greater than the adjacent spacing between the first substrate pads 31.
[0058] In view of the different density of connection structures required in different areas, connection structures containing solder balls with a core having a higher melting point and connection structures containing tin balls are set differently in different areas. In areas where fewer connection structures are required, that is, areas where the connection structures are sparsely distributed, tin balls are used; in areas where more connection structures are required, that is, areas where the connection structures are densely distributed, solder balls with a core having a higher melting point than tin are used, which can effectively alleviate the risk of bridging caused by contact between adjacent solder balls in high signal areas due to molten solder, while ensuring the reliability of the connection.
[0059] In some embodiments, continue to refer to Figure 5 As shown, the first solder ball 33 is ellipsoidal, and the copper ball core 331 inside is spherical, wherein the length of the major axis of the first solder ball 33 is The particle size of the internal copper core 331 is , the proportional relationship between the particle size of the copper ball core 331 and the length of the major axis of the first solder ball 33 satisfies: For example, the particle size of the inner copper core 331 is Can be , , or It should be noted that the above values are only for illustration purposes. The particle size of the copper ball core 331 is selected within the above range, which can provide good stability and support during the welding process and reduce the occurrence of bridging during the welding process.
[0060] In some embodiments, the particle size of the copper core is satisfy: For example, the particle size of the inner copper core 331 is ; The particle size of the internal copper core 331 is ; The particle size of the internal copper core 331 is ; or the particle size of the internal copper ball core 331 is The above values are only used as examples and are not intended to limit the sizes of the first solder ball and the copper ball core.
[0061] In some embodiments, the melting point of the tin alloy in the first solder ball is 150° C.-260° C.
[0062] In some embodiments, reference Figure 7 As shown, the distance between adjacent first substrate pads 31 in the first welding region R1 is , where the spacing satisfy: , and the diameter of the first substrate pad is greater than or equal to . The distance between adjacent first substrate pads is the distance between the center points of adjacent first substrate pads. In the first welding area R1 with a first connection structure having a higher density, a composite solder ball composed of a copper ball core and a tin layer is used. By utilizing the support function and high melting point characteristics of the internal copper ball core, the lateral expansion of the solder ball during the welding process can be reduced, thereby reducing the risk of continuous welding.
[0063] The distance between the adjacent second substrate pads 41 in the second welding region R2 is , where the spacing satisfy: The distance between adjacent second substrate pads 41 is the distance between the center points of adjacent second substrate pads. The second welding area R2 has a lower density second connection structure relative to the first welding area R1, and there is a larger spacing between adjacent second substrate pads. Using conventional solder balls as solder balls is more convenient to operate, the welding effect is more solid, and the cost is lower.
[0064] In some embodiments, reference Figure 8As shown, the packaging structure further includes a bottom filling layer 5 , which is disposed on a first surface S1 of the packaging substrate 1 close to the chip structure 2 . The bottom filling layer 5 is used to fill the space between the packaging substrate 1 and the chip structure 2 .
[0065] The bottom filling layer 5 is in the gap between the chip structure 2 and the packaging substrate 1, and can extend beyond the edge of the chip structure 2 on the surface of the packaging substrate 1. The bottom filling layer 5 can protect the solder balls between the chip structure 2 and the packaging substrate 1, and prevent the solder balls from failing due to external impact or temperature changes, thereby improving the reliability of the entire packaging structure. The bottom filling layer 5 can be set by a filling process, for example, the filling material can be applied between the chip structure 2 and the packaging substrate 1 by a dispensing process, and the gap between the chip structure and the packaging substrate is filled by the flow and capillary operation of the filling material. Afterwards, the filling material is cured to form a bottom filling layer.
[0066] In one embodiment, the bottom filling layer 5 is disposed on the first surface S1 of the package substrate 1, and fills the gap between the package substrate 1 and the chip structure 2 and the first connection structure 3. The bottom filling layer 5 extends beyond the edge of the chip structure 2 at the edge of the first surface S1 of the package substrate 1.
[0067] In some embodiments, reference Fig. 9 As shown, the package structure also includes a third conductive terminal 6, which is arranged on the side of the package substrate 1 away from the chip structure 2, and can be used to further connect the package structure to other package components, such as a printed circuit board. The third conductive terminal 6 can transmit the electrical signal generated by the chip structure 2 to other printed circuit boards, and can also transmit the electrical signal of other printed circuit boards to the chip structure 2, thereby realizing the signal interaction between the chip structure 2 and other printed circuit boards. At the same time, the third conductive terminal 6 can also play a certain heat dissipation role for the package structure, and conduct the heat generated by the chip structure to other parts of the package structure through the third conductive terminal, thereby achieving the heat dissipation effect.
[0068] In some embodiments, reference Fig.10 As shown, the package structure further includes a reinforcement structure 7, which is arranged at the periphery of the welding area of the surface of the package substrate 1 facing the chip structure 2. For example, the reinforcement structure 7 is arranged around the chip structure at the edge of the package substrate, and the reinforcement structure is attached to the package substrate through an adhesive layer. The reinforcement structure can control and reduce the warping of the package substrate and the overall package structure, and improve the performance of the package structure.
[0069] In some embodiments, reference Fig.11The chip structure 2 includes an adapter board 201, on which one or more chips 202 are arranged. A chip mounting area is arranged on the adapter board 201, and the area of the chip mounting area is less than or equal to the area of the adapter board 201. One or more chips 202 are connected to the adapter board 201 through a conductive connector 203. A filling layer 204 is arranged between the one or more chips 202 and the adapter board 201, and the filling layer 204 is in the chip mounting area to fill the gap between the chip 202 and the adapter board 201. The chip structure 2 also includes an encapsulation layer 205, which encapsulates the chip 202, the adapter board 201 and the filling layer 204. The edge of the encapsulation layer 205 is flush with the edge of the adapter board 201. The encapsulation layer 205 may include a molding compound, for example, an epoxy molding compound (EMC), and may be formed by a molding process.
[0070] In some embodiments, chip 202 is a core module composed of one chip or several chips. One chip or several chips can select the appropriate chip type according to product requirements, and each can be a system on chip (SoC), a digital signal processor (DSP) chip, a graphics processing unit (GPU), an application specific integrated circuit (ASIC) chip, a memory chip, a central processing unit (CPU), a tensor processor (TPU), a neural network processor (NPU), a deep learning processor (DPU), an accelerated processor (APU), a general-purpose graphics processor (GPGPU), etc. For example, when the chip is a core module composed of several chips, multiple chips may include chips of the same type or different types. It should be understood that the number of chips shown in the figure is only for illustration, and the present application is not limited to this.
[0071] The above description shows and describes the preferred embodiments of the present application. As mentioned above, it should be understood that the present application is not limited to the form disclosed herein, and should not be regarded as excluding other embodiments, but can be used in various other combinations, modifications and environments, and can be modified within the scope of the inventive concept of the present application through the above teachings or the technology or knowledge of the relevant field. The changes and modifications made by those skilled in the art do not depart from the spirit and scope of the present application, and should be within the scope of protection of the claims attached to the present application.
Claims
1. A packaging structure, characterized in that: include: A packaging substrate, a plurality of first connection structures and a chip structure; The first connection structure includes a first substrate pad, a first solder ball and a first conductive terminal, wherein the first substrate pad is arranged in a first welding area of the packaging substrate, the first conductive terminal is arranged on a surface of the chip structure facing the packaging substrate, the first solder ball is connected between the first substrate pad and the first conductive terminal, and the first solder ball has a core with a higher melting point than tin.
2. The packaging structure according to claim 1, characterized in that: The core of the first solder ball is a copper ball core.
3. The packaging structure according to claim 1, characterized in that: Also includes: a plurality of second connection structures; The second connection structure includes a second substrate pad, a second solder ball and a second conductive terminal, wherein the second substrate pad is arranged on a second welding area of the packaging substrate, the second conductive terminal is arranged on a surface of the chip structure facing the packaging substrate, the second solder ball is connected between the second substrate pad and the second conductive terminal, and the second solder ball is a tin ball.
4. The packaging structure according to claim 2, characterized in that: The first solder ball is ellipsoidal, and the length of the major axis of the first solder ball is The particle size of the copper core is ,satisfy .
5. The packaging structure according to claim 4, characterized in that: The particle size of the copper core satisfy: .
6. The packaging structure according to claim 4, characterized in that: The melting point of the tin alloy in the first solder ball is 150° C. to 260° C.
7. The packaging structure according to claim 3, characterized in that: The distance between adjacent first substrate pads on the first welding area is ,in ; The spacing between adjacent second substrate pads on the second welding area is ,in .
8. The packaging structure according to claim 1, characterized in that: It also includes a bottom filling layer, which is arranged on a surface of the packaging substrate close to the chip structure, and is used to fill a gap between the packaging substrate and the chip structure.
9. The packaging structure according to claim 8, characterized in that: Also includes: A third conductive terminal is disposed on a surface of the packaging substrate at a side away from the chip structure.
10. The packaging structure according to claim 9, characterized in that: Also includes: The reinforcing structure is arranged at the periphery of the welding area of the surface of the packaging substrate facing the chip structure.