Full-bridge packaging structure with multiple chips connected in parallel

Abstract

The utility model discloses a full-bridge packaging structure with multiple chips connected in parallel, which comprises a DBC substrate, the DBC substrate comprises a circuit layer formed by two groups of symmetrically arranged copper foil areas, and each copper foil area comprises a negative electrode DC-copper foil, a lower bridge AC copper foil and an upper bridge DC + copper foil; the N chips of the first part of the lower bridge are welded on the AC copper foil of one copper foil area, and the N chips of the second part of the lower bridge are welded on the AC copper foil of the other copper foil area; the N chips of the first part of the upper bridge are connected to the DC + copper foil of one copper foil area, and the N chips of the second part of the upper bridge are connected to the DC + copper foil of the other copper foil area; the N chips of the first part of the lower bridge are connected in parallel, the N chips of the second part of the lower bridge are connected in parallel, the N chips of the first part of the upper bridge are connected in parallel, the N chips of the second part of the upper bridge are connected in parallel, the N chips of the first part of the upper bridge are connected with the N chips of the first part of the lower bridge in series, and the N chips of the second part of the upper bridge are connected with the N chips of the second part of the lower bridge in series. And finally, full-bridge packaging is formed.

Description

Technical Field

[0001] The present application relates to the field of chip packaging technology, and in particular to a full-bridge packaging structure of multiple chips in parallel. Background Art

[0002] Currently, the commonly used full-bridge circuit is composed of multiple single chips (i.e. single tubes). During the chip packaging process, multiple single tubes are prone to poor circuit heat dissipation performance, resulting in a great risk of product failure and damage. Utility Model Content

[0003] The present application provides a full-bridge packaging structure with multiple chips connected in parallel, aiming to improve the problem of poor heat dissipation performance of the circuit.

[0004] In order to achieve the above technical effects, a technical solution adopted by the present application is to provide a multi-chip parallel full-bridge packaging structure, including:

[0005] DBC substrate, the DBC substrate is provided with a circuit layer formed by two sets of symmetrically arranged copper foil areas, a single copper foil area includes a negative DC- copper foil, an AC copper foil of the lower bridge and a DC+ copper foil of the upper bridge;

[0006] The first part of N chips of the lower bridge is welded on the AC copper foil of one copper foil area, and the second part of N chips of the lower bridge is welded on the AC copper foil of another copper foil area;

[0007] The first part of N chips on the upper bridge are connected to the DC+ copper foil of one copper foil area, and the second part of N chips on the upper bridge are connected to the DC+ copper foil of another copper foil area;

[0008] The first part of N chips in the lower bridge are connected in parallel, the second part of N chips in the lower bridge are connected in parallel, the first part of N chips in the upper bridge are connected in parallel, the second part of N chips in the upper bridge are connected in parallel, and the first part of N chips in the upper bridge and the first part of N chips in the lower bridge are connected in series, and the second part of N chips in the upper bridge and the second part of N chips in the lower bridge are connected in series to form a full-bridge package.

[0009] The first part of N chips on the lower bridge and the second part of N chips on the lower bridge are mirrored; and / or the first part of N chips on the upper bridge and the second part of N chips on the upper bridge are mirrored.

[0010] The DBC substrate has a first surface and a second surface that are arranged opposite to each other, and the circuit layer is arranged on the first surface; the DBC substrate also includes a lower copper foil, and the lower copper foil is arranged on the second surface.

[0011] The area of ​​the second surface is S1, and the area of ​​the lower copper foil is not less than 0.9S1.

[0012] Wherein, a plurality of via holes are opened on the lower copper foil.

[0013] The via holes are distributed in a ring shape near the edge of the lower copper foil; and / or the center distance between adjacent via holes is not less than 0.9 mm.

[0014] The DBC substrate has a first surface and a second surface which are arranged opposite to each other, and the circuit layer is arranged on the first surface; the area of ​​the first surface is S2, and the area of ​​the circuit layer is not less than 0.9S2.

[0015] The full-bridge package structure of multiple chips in parallel also includes wiring terminals; the wiring terminals include a DC+ power terminal, a DC- power terminal and an AC power terminal; wherein:

[0016] The DBC substrate is provided with a DC+ power terminal and a DC- power terminal in the area corresponding to each copper foil area, wherein the DC+ power terminal is electrically connected to the DC+ copper foil of the upper bridge of the corresponding copper foil area; and the DC- power terminal is electrically connected to the negative DC- copper foil of the corresponding copper foil area; and / or

[0017] An AC power terminal is respectively arranged in a region corresponding to each copper foil area on the DBC substrate, and the AC power terminal is respectively electrically connected to the AC copper foil of the corresponding copper foil area.

[0018] Each copper foil area further includes a gate copper foil and an auxiliary source copper foil; the connection terminal further includes a gate drive terminal and an auxiliary source drive terminal, wherein:

[0019] The first part of the N chips on the upper bridge has a gate copper foil electrically connected to the gate and an auxiliary source copper foil electrically connected to the auxiliary source, and the first part of the N chips on the upper bridge respectively have a gate drive terminal electrically connected to the gate copper foil and an auxiliary source drive terminal electrically connected to the auxiliary source copper foil; and / or

[0020] The second part of the N chips on the upper bridge has a gate copper foil electrically connected to the gate and an auxiliary source copper foil electrically connected to the auxiliary source, and the second part of the N chips on the upper bridge respectively has a gate drive terminal electrically connected to the gate copper foil and an auxiliary source drive terminal electrically connected to the auxiliary source copper foil; and / or

[0021] The first part of the N chips of the lower bridge has a gate copper foil electrically connected to the gate and an auxiliary source copper foil electrically connected to the auxiliary source, and the first part of the N chips of the lower bridge respectively have a gate drive terminal electrically connected to the gate copper foil and an auxiliary source drive terminal electrically connected to the auxiliary source copper foil; and / or

[0022] The second part of the N chips in the lower bridge have a gate copper foil electrically connected to the gate and an auxiliary source copper foil electrically connected to the auxiliary source. The first part of the N chips in the lower bridge respectively have a gate drive terminal electrically connected to the gate copper foil and an auxiliary source drive terminal electrically connected to the auxiliary source copper foil.

[0023] Among them, some of the wiring terminals are terminals of the first shape, and some of the wiring terminals are terminals of the second shape; wherein:

[0024] The connection terminal of the first shape terminal is at least partially a bendable structure; and / or

[0025] The diameter of the first shape terminal is smaller than the diameter of the second shape terminal; and / or

[0026] The length of the first shape terminal is not less than the length of the second shape terminal.

[0027] In the example of the present application, by using two groups of symmetrically arranged copper foil areas to form a circuit layer, the symmetry of the circuit can be improved, and then the current sharing performance and heat dissipation performance of the circuit can be improved; by integrating the first part of N chips on the upper bridge, the second part of N chips on the upper bridge, the first part of N chips on the lower bridge, and the second part of N chips on the lower bridge into one module, it can help to improve the integration performance of the circuit and reduce the space required for the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0029] Figure 1 It is a structural schematic diagram of an example of a DBC substrate of the present application;

[0030] Figure 2 is a top view of an example of a DBC substrate of the present application;

[0031] Figure 3 is a rear view of an example of a DBC substrate of the present application;

[0032] Figure 4 It is a front view of an example of a DBC substrate of the present application;

[0033] Figure 5 It is a schematic diagram of chip layout of an example of a full-bridge packaging structure of multiple chips in parallel in the present application;

[0034] Figure 6 It is a top view of the chip layout of an example of a full-bridge packaging structure of multiple chips in parallel in the present application;

[0035] Figure 7 This is a schematic structural diagram of an example of a driving and power terminal of a full-bridge package structure of multiple chips in parallel in the present application;

[0036] Figure 8 It is a top view of an example of a driving and power terminal of a full-bridge package structure of multiple chips in parallel in the present application;

[0037] Fig. 9 This is a circuit topology diagram of an example of a full-bridge packaging structure of multiple chips in parallel in the present application;

[0038] Fig.10 This is a schematic diagram of the structure of an example of a first shape terminal of the present application;

[0039] Fig.11 It is a structural diagram of an example of the second shape terminal of the present application.

[0040] in:

[0041] 1. DBC substrate;

[0042] 2. Ceramic substrate;

[0043] 3. Lower copper foil; 31. Via hole;

[0044] 4. Circuit layer; 4L, 4R, copper foil area; 41, DC+ copper foil; 42, DC- copper foil; 42L, first DC- copper foil; 42R second DC- copper foil; 43, AC copper foil; 43L, first AC copper foil; 43R second AC copper foil; 44, gate copper foil; 441L, first part of the gate copper foil of the upper bridge; 441R, second part of the gate copper foil of the upper bridge; 442L, first part of the gate copper foil of the lower bridge; 442R, second part of the gate copper foil of the lower bridge; 45, auxiliary source copper foil; 4 51L, auxiliary source copper foil of the first part of the upper bridge; 451R, auxiliary source copper foil of the second part of the upper bridge; 452L, auxiliary source copper foil of the first part of the lower bridge; 452R, auxiliary source copper foil of the second part of the lower bridge; 46, driving resistor copper foil; 461L, driving resistor copper foil of the first part of the upper bridge; 461R, driving resistor copper foil of the second part of the upper bridge; 462L, driving resistor copper foil of the first part of the lower bridge; 462R, driving resistor copper foil of the second part of the lower bridge; 47, NTC resistor copper foil; 48, solder resist;

[0045] 5. Bonding wire; 51L, gate bonding wire of the first part of the upper bridge; 51R, gate bonding wire of the second part of the upper bridge; 52L, gate bonding wire of the first part of the lower bridge; 52R, gate bonding wire of the second part of the lower bridge; 53L, auxiliary source bonding wire of the first part of the upper bridge; 53R, auxiliary source bonding wire of the second part of the upper bridge; 54L, auxiliary source bonding wire of the first part of the lower bridge; 54R, auxiliary source bonding wire of the second part of the lower bridge; 55L, source power bonding wire of the first part of the upper bridge; 55R, source power bonding wire of the second part of the upper bridge; 56L, source power bonding wire of the first part of the lower bridge; 56R, source power bonding wire of the second part of the lower bridge;

[0046] 6. Gate drive resistor; 61L, gate drive resistor of the first part of the upper bridge; 61R, gate drive resistor of the second part of the upper bridge; 62L, gate drive resistor of the first part of the lower bridge; 62R, gate drive resistor of the second part of the lower bridge;

[0047] 7. Wiring terminal; 71. DC+ power terminal; 72. DC- power terminal; 721. first DC- power terminal; 722. second DC- power terminal; 731. first gate drive terminal; 732. second gate drive terminal; 733. third gate drive terminal; 734. fourth gate drive terminal; 74. auxiliary source drive terminal; 741. first auxiliary source drive terminal; 742. second auxiliary source drive terminal; 743. third auxiliary source drive terminal; 744. fourth auxiliary source drive terminal; 75. AC power terminal; 751. first AC power terminal; 752. second AC power terminal; 76. NTC resistor drive terminal; 761. first NTC resistor drive terminal; 762. second NTC resistor drive terminal; T1. first shape terminal; T2. second shape terminal;

[0048] 8. Housing; 81. Copper bottom plate; 82. Epoxy resin; 83. Combination washer screw; 84. Protrusion; 85. NTC resistor;

[0049] 91. The first part of the chip of the upper bridge; 92. The second part of the chip of the upper bridge; 93. The first part of the chip of the lower bridge; 94. The second part of the chip of the lower bridge. DETAILED DESCRIPTION

[0050] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0051] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, which are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are used only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. It should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" in the description of this application should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this article can be understood according to specific circumstances.

[0052] In this application, the word "exemplary" is used to mean "used as an example, illustration, or description." Any embodiment described in this application as "exemplary" is not necessarily to be construed as being preferred or advantageous over other embodiments. The following description is given to enable any technician in the field to implement and use the present application. In the following description, details are listed for the purpose of explanation. It should be understood that a person of ordinary skill in the art can recognize that the present application can be implemented without using these specific details. In other instances, well-known structures and processes will not be elaborated in detail to avoid obscuring the description of the present application with unnecessary details. Therefore, the present application is not intended to be limited to the embodiments shown, but is consistent with the widest scope consistent with the principles and features disclosed in the present application.

[0053] See also Figures 1 to 6 The present application proposes an example of a full-bridge packaging structure of multiple chips in parallel, including a DBC substrate 1, wherein the DBC substrate 1 is provided with a circuit layer 4 formed by two groups of symmetrically arranged copper foil areas 4L and 4R, and a single copper foil area includes a negative DC- copper foil 42, an AC copper foil 43 of a lower bridge, and a DC+ copper foil 41 of an upper bridge.

[0054] The DBC substrate 1 may be a generally rectangular plate-shaped structure, the middle layer of the DBC substrate 1 may be a ceramic substrate 2, the ceramic substrate 2 may have a first surface and a second surface arranged opposite to each other, and the circuit layer 4 may be arranged on the first surface. In this example, the two groups of copper foil areas 4L and 4R may be arranged symmetrically in the length direction of the ceramic substrate 2, and the copper foil areas may be divided into the following: Figure 1 The copper foil area 4L and the copper foil area 4R in the . A single copper foil area includes a negative DC-copper foil 42, an AC copper foil 43 of the lower bridge, and a DC+copper foil 41 of the upper bridge, wherein the AC copper foil 43 of the lower bridge and the DC+copper foil 41 of the upper bridge can be arranged relative to each other, and the negative DC-copper foil 42 can be arranged between the AC copper foil 43 of the lower bridge and the DC+copper foil 41 of the upper bridge; in this example, the DC-copper foil 42 includes a first DC-copper foil 42L and a second DC-copper foil 42R, wherein one copper foil area 4L is the first DC-copper foil 42L, and the other copper foil area 4R is the second DC-copper foil 42R. The two groups of copper foil areas 4L and 4R are symmetrically arranged, which means that a symmetry axis is defined on the ceramic substrate 2, and the symmetry axis can be one of the midlines of the ceramic substrate 2, and the two groups of copper foil areas 4L and 4R are symmetrically arranged on both sides of the symmetry axis. In this example, by symmetrically arranging the two groups of copper foil areas 4L and 4R, on the one hand, it is convenient to integrate multiple chips on the DBC substrate 1 to improve the integration of the circuit; on the other hand, it is convenient to improve the current sharing and heat dissipation performance of the circuit.

[0055] Please refer to Figure 7 , Figure 8 as well as Fig. 9 In the example of the present application, the circuit layer 4 can be a plurality of independent conductor layers formed by etching, and the copper foil area can be treated for oxidation resistance by electroplating. The circuit layer 4 can constitute a circuit topology together with the power chip, the bonding wire 5, the terminal block, etc. In some examples, the ceramic substrate 2 can select ceramic materials such as aluminum nitride, zirconium oxide-doped aluminum oxide, silicon nitride, etc. with high thermal conductivity to improve the heat dissipation performance. In some examples, two groups of copper foil areas can be respectively provided with solder resist 48, and the solder resist 48 can be used to reduce the possibility of solder overflow when soldering on the chip, the resistor and the corresponding copper foil, which helps to reduce electrical short circuits during use.

[0056] The first part of N chips 93 of the lower bridge is connected to the AC copper foil 43 of one copper foil area 4L, and the second part of N chips 94 of the lower bridge is connected to the AC copper foil 43 of another copper foil area 4R.

[0057] In this example, the first part of the N chips 93 of the lower bridge can be symmetrically arranged with the second part of the N chips 94 of the lower bridge; wherein the N chips can be 2 or more, such as Figure 62 chips are shown in the figure. In some examples, the first part of N chips 93 of the lower bridge and the second part of N chips 94 of the lower bridge can all be MOSFET chips. In this example, the first part of N chips 93 of the lower bridge can be electrically connected to the AC copper foil 43 of one copper foil area 4L by ultrasonic welding or other welding methods, and the second part of N chips 94 of the lower bridge can be electrically connected to the AC copper foil 43 of another copper foil area 4R by ultrasonic welding or other welding methods. In some examples, the first part of N chips 93 of the lower bridge and the second part of N chips 94 of the lower bridge are mirrored to improve the current sharing and heat dissipation performance of the circuit.

[0058] The first part of N chips 91 of the upper bridge is connected to the DC+ copper foil 41 of one copper foil area 4L, and the second part of N chips 92 of the upper bridge is connected to the DC+ copper foil 41 of another copper foil area 4R.

[0059] In this example, the first part of the N chips 91 of the upper bridge can be symmetrically arranged with the second part of the N chips 92 of the upper bridge; wherein, the N chips can be 2 or more. In some examples, the first part of the N chips 91 of the upper bridge and the second part of the N chips 92 of the upper bridge can both be MOSFET chips. In this example, the first part of the N chips 91 of the upper bridge can be electrically connected to the AC copper foil 43 of one of the copper foil areas 4L by ultrasonic welding or other welding methods, and the second part of the N chips 92 of the upper bridge can be electrically connected to the AC copper foil 43 of another copper foil area 4R by ultrasonic welding or other welding methods. In some examples, the first part of the N chips 91 of the upper bridge and the second part of the N chips 92 of the upper bridge are mirrored to improve the current sharing and heat dissipation performance of the circuit.

[0060] The first part of the N chips 93 of the lower bridge is connected in parallel, the second part of the N chips 94 of the lower bridge is connected in parallel, the first part of the N chips 91 of the upper bridge is connected in parallel, the second part of the N chips 92 of the upper bridge is connected in parallel, and the first part of the N chips 91 of the upper bridge is connected in series with the first part of the N chips 93 of the lower bridge; the second part of the N chips 92 of the upper bridge is connected in series with the second part of the N chips 94 of the lower bridge, and finally a full-bridge package is formed; the number of external circuit pins can be reduced, and the DC+ power terminal 71, DC- power terminal 72 and AC terminal 7 pins can be relatively reduced, which can reduce the risk of failure on the one hand; on the other hand, the feasibility of the overall module can be improved, the processing cost can be reduced, and the reliability of the circuit can be improved; on the other hand, by reducing the number of terminals 7, the heat dissipation performance of the circuit can be further improved. In this example, a packaging module that is compatible with multiple chips in parallel, has high reliability, high integration and current sharing can be formed.

[0061] In some examples, the full-bridge package structure of multi-chip parallel connection also includes a housing 8, and the DBC substrate 1 and the chip are placed in the housing 8. Optionally, the housing 8 can be a PBT (polybutylene terephthalate) housing. In some examples, epoxy resin 82 is injected into the housing 8, and the epoxy resin 82 can be used to protect the internal components of the module from external contamination. In some examples, the full-bridge package structure of multi-chip parallel connection also includes a copper base plate 81, and the housing 8 can be installed on the copper base plate 81. The housing 8 and the copper base plate 81 can be fixed in position by a combination screw washer screw 83. The number of the combination screw washer screw 83 can be multiple, and at least one of the multiple combination screw washer screws 83 can be set at one end in the length direction of the housing 8, and another combination screw washer screw 83 can be set at the other end in the length direction of the housing 8. In some examples, a protrusion 84 is provided on the housing 8, and the protrusion 84 can be used to facilitate the connection and positioning of the external PCB.

[0062] In some examples, the full-bridge package structure of multi-chip parallel connection also includes an NTC resistor 85 (thermistor), which can be used to detect the temperature when the power module is working, and can generally be used to monitor the health of the power module. In some examples, NTC resistors 85 can be respectively set on the two groups of copper foil areas 4L and 4R, and the NTC resistors 85 on the two groups of copper foil areas 4L and 4R can be symmetrically arranged. In some examples, the full-bridge package structure of multi-chip parallel connection also includes an NTC resistor drive terminal 76, and the NTC resistor 85 can be electrically connected to the NTC resistor drive terminal 76. Optionally, the NTC resistor drive terminal 76 corresponds to the number of NTC resistors 85, and optionally, the NTC resistor drive terminal 76 includes a first NTC resistor drive terminal 761 and a second NTC resistor drive terminal 762, and the NTC resistors 85 of the two groups of copper foil areas 4L and 4R respectively have corresponding first NTC resistor drive terminals 761 and second NTC resistor drive terminals 762. In some examples, the copper foil area further includes an NTC resistor copper foil 47 . The NTC resistor copper foil 47 may correspond to the position of the NTC resistor 85 , and the NTC resistor driving terminal 76 may be electrically connected to the NTC resistor copper foil 47 .

[0063] In some examples, the packaging process includes the following steps:

[0064] S1: preparing a corresponding DBC substrate 1 according to the structure of the power module to be packaged, etching to form a circuit layer 4, and then performing a surface nickel plating treatment;

[0065] S2: soldering or sintering the power chip, the gate drive resistor 6 and the NTC resistor 85 to the corresponding copper foil positions using solder;

[0066] S3: electrically connecting the surface electrode of the power semiconductor chip to the corresponding copper foil of the copper foil layer through a wire bonding process;

[0067] S4: Using solder to perform secondary welding on the drive terminal, the power terminal and the copper bottom plate 81 at the same time;

[0068] S5: Fix the housing 8 on the copper bottom plate 81, inject the epoxy resin 82 into the housing 8, evacuate the housing 8, and then heat or leave it at room temperature to cure the epoxy resin 82.

[0069] In some examples, the DBC substrate 1 has a first surface and a second surface that are arranged opposite to each other, and the circuit layer 4 is arranged on the first surface; the DBC substrate 1 also includes a lower copper foil 3, and the lower copper foil 3 is arranged on the second surface.

[0070] In this example, the first surface and the second surface are two surfaces arranged opposite to each other. Assuming that the first surface is the upper surface, the second surface can be the lower surface of the DBC substrate 1. The lower copper foil 3 is arranged on the second surface. The lower copper foil 3 in the example of this application can be connected to the heat sink through a thermal interface material, which can play a role in heat conduction.

[0071] In some examples, the area of ​​the second surface is S1, and the area of ​​the lower copper foil 3 is not less than 0.9S1. In this example, the distance between the lower copper foil 3 and the ceramic substrate 2 only needs to meet the minimum insulation gap. By limiting the area of ​​the lower copper foil 3 to be not less than 90% of the area of ​​the second surface, the warping risk of the lower copper foil 3 can be reduced.

[0072] In some examples, a plurality of vias 31 are provided on the lower copper foil 3. The vias 31 can be used to release the thermal stress at the edge of the lower copper foil 3, reduce the stress concentration on the lower copper foil 3, and help improve the reliability of the packaging structure. In this example, the position, aperture and spacing between adjacent holes of the vias 31 can be determined according to the specific situation. In some examples, the vias 31 are distributed in an annular shape near the edge of the lower copper foil 3 to reduce the warping generated at the edge of the lower copper foil 3, which helps to improve the reliability of the lower copper foil 3. The vias 31 in this example are distributed in an annular shape, which means that a plurality of vias 31 can be distributed at intervals along the edge position of the lower copper foil 3, and the distribution trajectory of the plurality of vias 31 is generally annular. In some examples, the center distance between adjacent vias 31 is not less than 0.9 mm, so that the vias 31 have the effect of releasing stress while reducing the influence of the vias 31 on the structural strength of the lower copper foil 3.

[0073] In some examples, the area of ​​the first surface is S2, and the area of ​​the circuit layer 4 is not less than 0.9S2. In this example, the distance between the circuit layer 4 and the ceramic substrate 2 satisfies the minimum insulation gap. By limiting the area of ​​the circuit layer 4 to be not less than 90% of the area of ​​the first surface, the possibility of warping of the circuit layer 4 can be reduced.

[0074] In some examples, the full-bridge package structure of multi-chip parallel connection also includes a terminal 7; the terminal 7 includes a DC+ power terminal 71, a DC- power terminal 72 and an AC power terminal 75; the DC+ power terminal 71 and the DC- power terminal 72 in this example can be used to connect an external circuit respectively. The surface of the terminal 7 in this example can be nickel-plated or gold-plated to improve the resistance of the terminal 7 to moisture, mildew and salt spray to extend the service life. Optionally, the area corresponding to each copper foil area 4L and 4R on the DBC substrate 1 is provided with a DC+ power terminal 71 and a DC- power terminal 72, wherein the DC- power terminal 72 includes a first DC- power terminal 721 and a second DC- power terminal 722, one copper foil area 4L corresponds to the first DC- power terminal 721, and the other copper foil area 4R corresponds to the second DC- power terminal 722, and the DC+ power terminal 71 is electrically connected to the DC+ copper foil 41 of the upper bridge of the corresponding copper foil area 4L; the DC- power terminal 72 is electrically connected to the DC- copper foil 42 of the corresponding copper foil area. In this example, the positions of the DC+ power terminals 71 of the two groups of copper foil areas can be symmetrically arranged, and the positions of the DC- power terminals 72 of the two groups of copper foil areas 4L and 4R can be symmetrically arranged; optionally, the positions of the DC+ power terminals 71 of the two groups of copper foil areas 4L and 4R can be asymmetrically arranged, and the positions of the DC- power terminals 72 of the two groups of copper foil areas 4L and 4R can also be asymmetrically arranged to meet the creepage distance. The shapes and / or sizes of the DC+ power terminals 71 and the DC- power terminals 72 in this example can be consistent or inconsistent, and the shapes and / or sizes of the corresponding terminals of the two groups of copper foil areas 4L and 4R can be consistent or inconsistent.

[0075] Optionally, a driving resistor copper foil 46 is also provided on the circuit layer 4, and the driving resistor copper foil 46 may correspond to the chip. Optionally, the driving resistor copper foil 46 includes a first portion of the upper bridge driving resistor copper foil 461L, a second portion of the upper bridge driving resistor copper foil 461R, a first portion of the lower bridge driving resistor copper foil 462L, and a second portion of the lower bridge driving resistor copper foil 462R. The full-bridge package structure with multiple chips in parallel also includes a gate driving resistor 6, and the gate driving resistor 6 may correspond to the chip, and the gate driving resistor 6 may include a first portion of the upper bridge gate driving resistor 61L, a second portion of the upper bridge gate driving resistor 61R, a first portion of the lower bridge gate driving resistor 62L, and a second portion of the lower bridge gate driving resistor 62R. The AC copper foil 43 includes a first AC copper foil 43L and a second AC copper foil 43R, wherein the first AC copper foil 43L may be located in the copper foil area 4L, and the second AC copper foil 43R may be located in the copper foil area 4R.

[0076] Optionally, an AC power terminal 75 is provided in the area corresponding to each copper foil area 4L and 4R on the DBC substrate 1, and the AC power terminal 75 is electrically connected to the AC copper foil 43 of the corresponding copper foil area. In this example, the two groups of copper foil areas 4L and 4R are respectively provided with AC power terminals 75, and the AC power terminals 75 can be electrically connected to the AC copper foil 43 in the corresponding copper foil area by welding or other connection methods. Optionally, the AC power terminal 75 includes a first AC power terminal 751 provided in one of the copper foil areas 4L and a second AC power terminal 752 provided in the other copper foil area 4R. Optionally, the first AC power terminal 751 and the second AC power terminal 752 of the two groups of copper foil areas can be symmetrically arranged; optionally, the first AC power terminal 751 and the second AC power terminal 752 of the two groups of copper foil areas 4L and 4R can also be asymmetrically arranged to meet the creepage distance.

[0077] Optionally, each copper foil area also includes a gate copper foil 44 and an auxiliary source copper foil 45; the terminal 7 also includes a gate drive terminal 73 and an auxiliary source drive terminal 74. In this example, the gate copper foils 44 of the two groups of copper foil areas 4L and 4R can be symmetrically arranged, and optionally, the auxiliary source copper foils 45 of the two groups of copper foil areas 4L and 4R can be symmetrically arranged. The two groups of copper foil areas 4L and 4R are respectively provided with gate drive terminals 73 and auxiliary source drive terminals 74, wherein the gate drive terminals 73 of the two groups of copper foil areas 4L and 4R can be symmetrically arranged, and optionally, the gate drive terminals 73 of the two groups of copper foil areas 4L and 4R can be asymmetrically arranged to meet the creepage distance. Optionally, the auxiliary source copper foils 45 of the two groups of copper foil areas 4L and 4R can be symmetrically arranged, and optionally, the auxiliary source copper foils 45 of the two groups of copper foil areas 4L and 4R can also be asymmetrically arranged.

[0078] In some examples, the first part of N chips 91 of the upper bridge have a gate copper foil 44 electrically connected to the gate and an auxiliary source copper foil 45 electrically connected to the auxiliary source, and the first part of N chips 91 of the upper bridge respectively have a gate drive terminal 73 electrically connected to the gate copper foil 44 and an auxiliary source drive terminal 74 electrically connected to the auxiliary source copper foil 45. Optionally, the gate copper foil 44 includes a first part of the gate copper foil 441L of the upper bridge, a second part of the gate copper foil 441R of the upper bridge, a first part of the gate copper foil 442L of the lower bridge and a second part of the gate copper foil 442R of the lower bridge. The number of gate drive terminals 73 corresponds to the number of chips. In this example, taking the number of chips as 4 as an example, the number of gate drive terminals 73 can be four, namely, a first gate drive terminal 731, a second gate drive terminal 732, a third gate drive terminal 733 and a fourth gate drive terminal 734. The first gate drive terminal 731 can be used to connect the first part of the gate copper foil 441L of the upper bridge, the second gate drive terminal 732 can be used to connect the second part of the gate copper foil 441R of the upper bridge, the third gate drive terminal 733 can be used to connect the first part of the gate copper foil 442L of the lower bridge, and the fourth gate drive terminal 734 can be used to connect the second part of the gate copper foil 442R of the lower bridge. Optionally, the auxiliary source copper foil 45 includes an upper bridge first part auxiliary source copper foil 451L, an upper bridge second part auxiliary source copper foil 451R, a lower bridge first part auxiliary source copper foil 452L, and a lower bridge second part auxiliary source copper foil 452R. In this example, the auxiliary source driving terminal 74 corresponds to the chip. Taking the number of chips as four as an example, the number of auxiliary source driving terminals 74 can be four, namely, a first auxiliary source driving terminal 741, a second auxiliary source driving terminal 742, a third auxiliary source driving terminal 743, and a fourth auxiliary source driving terminal 744.

[0079] Optionally, the bonding wire 5 may include an upper bridge first portion gate bonding wire 51L, an upper bridge second portion gate bonding wire 51R, a lower bridge first portion gate bonding wire 52L, and a lower bridge second portion gate bonding wire 52R. Optionally, the bonding wire 5 may also include an upper bridge first portion auxiliary source bonding wire 53L, an upper bridge second portion auxiliary source bonding wire 53R, a lower bridge first portion auxiliary source bonding wire 54L, and a lower bridge second portion auxiliary source bonding wire 54R. Optionally, the bonding wire 5 may also include source power bonding wires, including an upper bridge first portion source power bonding wire 55L, an upper bridge second portion source power bonding wire 55R, a lower bridge first portion source power bonding wire 56L, and a lower bridge second portion source power bonding wire 56R.

[0080] The gates of the first part of the N chips 91 of the upper bridge in this example can be electrically connected to the corresponding first part of the gate copper foil 441L of the upper bridge through the first part of the gate bonding wire 51L of the upper bridge or other methods, and the auxiliary source of the first part of the N chips 91 of the upper bridge can be electrically connected to the first part of the auxiliary source copper foil 451L of the upper bridge through the first part of the auxiliary source bonding wire 53L of the upper bridge or other methods. The gate drive terminal 73 can be used to connect to an external circuit, and the auxiliary source drive terminal 74 can be used to connect to an external circuit. The shape and / or size of the gate drive terminal 73 in this example can be consistent with the shape and / or size of the auxiliary source drive terminal 74, or it can be inconsistent.

[0081] In some examples, the second part of the N chips 92 of the upper bridge has a gate copper foil 44 electrically connected to the gate thereof and an auxiliary source copper foil 45 electrically connected to the auxiliary source thereof, and the second part of the N chips 92 of the upper bridge respectively has a gate drive terminal 73 electrically connected to the gate copper foil 44 and an auxiliary source drive terminal 74 electrically connected to the auxiliary source copper foil 45; the gates of the second part of the N chips 92 of the upper bridge in this example can be electrically connected to the corresponding second part of the gate copper foil 441R of the upper bridge through the second part of the gate bonding wire 51R of the upper bridge or other methods, and the auxiliary source of the second part of the N chips 92 of the upper bridge can be electrically connected to the second part of the auxiliary source copper foil 451R of the upper bridge through the second part of the auxiliary source bonding wire 53R of the upper bridge or other methods. The shape and / or size of the gate drive terminal 73 in this example can be consistent with the shape and / or size of the auxiliary source drive terminal 74, or it can be inconsistent.

[0082] In some examples, the first part of the N chips 93 of the lower bridge has a gate copper foil 44 electrically connected to the gate thereof and an auxiliary source copper foil 45 electrically connected to the auxiliary source thereof, and the first part of the N chips 93 of the lower bridge respectively has a gate drive terminal 73 electrically connected to the gate copper foil 44 and an auxiliary source drive terminal 74 electrically connected to the auxiliary source copper foil 45; the gates of the first part of the N chips 93 of the lower bridge in this example can be electrically connected to the corresponding first part of the gate copper foil 442L of the lower bridge through the first part of the gate bonding wire 52L of the lower bridge or other methods, and the auxiliary source of the first part of the N chips 93 of the lower bridge can be electrically connected to the first part of the auxiliary source copper foil 452L of the lower bridge through the first part of the auxiliary source bonding wire 54L of the lower bridge or other methods. The shape and / or size of the gate drive terminal 73 in this example can be consistent with or inconsistent with the shape and / or size of the auxiliary source drive terminal 74.

[0083] In some examples, the second part of the N chips 94 of the lower bridge has a gate copper foil 44 electrically connected to the gate thereof and an auxiliary source copper foil 45 electrically connected to the auxiliary source thereof, and the second part of the N chips 94 of the lower bridge respectively has a gate drive terminal 73 electrically connected to the gate copper foil 44 and an auxiliary source drive terminal 74 electrically connected to the auxiliary source copper foil 45. The gates of the second part of the N chips 94 of the lower bridge in this example can be electrically connected to the corresponding second part of the gate copper foil 442R of the lower bridge through the second part of the gate bonding wire 52R of the lower bridge or other methods, and the auxiliary source of the second part of the N chips 94 of the lower bridge can be electrically connected to the second part of the auxiliary source copper foil 452R of the lower bridge through the second part of the auxiliary source copper foil 452R of the lower bridge or other methods. The shape and / or size of the gate drive terminal 73 in this example can be consistent with the shape and / or size of the auxiliary source drive terminal 74, or it can be inconsistent.

[0084] In some examples, a first part of N chips 91 of the upper bridge and a second part of N chips 92 of the upper bridge, where N is 2, are used as an example for explanation.

[0085] The drain electrodes of the two chips 91 in the first part of the upper bridge are respectively welded on the DC+ copper foil 41, and the DC+ copper foil 41 is connected to the external circuit through the DC+ power terminal 71. The gate electrodes of the two chips 91 in the first part of the upper bridge are respectively connected to the gate drive terminal 731 through the corresponding gate bonding wire 51L of the first part of the upper bridge, the gate drive resistor 61L of the first part of the upper bridge, and the gate copper foil 441L of the first part of the upper bridge; the auxiliary source electrodes of the two chips 91 in the first part of the upper bridge are respectively connected to the auxiliary source drive terminal 741 through the corresponding auxiliary source bonding wire 51L of the first part of the upper bridge and the auxiliary source copper foil 451L of the first part of the upper bridge; and finally connected to the external circuit through the gate drive terminal 731 and the auxiliary source terminal 741. The power source electrodes of the two chips 91 in the first part of the upper bridge are respectively connected to the external circuit through the corresponding source power bonding wire 55L of the first part of the upper bridge, the first AC copper foil 43L and the first AC power terminal 751. At this point, the two chips 91 of the first part of the upper bridge form a complete electrical connection with the external circuit. Similarly, the electrical connection method between the two chips 92 of the second part of the upper bridge and the external circuit is almost the same as that of the two chips 91 of the first part of the upper bridge, which will not be repeated here.

[0086] The drain electrodes of the two chips 93 in the first part of the lower bridge are soldered on the first AC copper foil 43L, and the first AC copper foil 43L is connected to the external circuit through the first AC power terminal 751. The gate electrodes of the two chips 93 in the first part of the lower bridge are respectively connected to the third gate drive terminal 733 through the gate bonding wire 52L of the first part of the lower bridge, the gate drive resistor 62L of the first part of the lower bridge, and the gate copper foil 442L of the first part of the lower bridge; the auxiliary source electrodes of the two chips 93 in the first part of the lower bridge are respectively connected to the third auxiliary source drive terminal 743 through the corresponding auxiliary source bonding wire 54L of the first part of the lower bridge and the auxiliary source copper foil 452L of the first part of the lower bridge; and finally connected to the external circuit by driving the third gate terminal 733 and the third auxiliary source terminal 743. The power source electrodes of the two chips 93 in the first part of the lower bridge are respectively connected to the external circuit through the source power bonding wire 56L of the first part of the lower bridge, the first DC-copper foil 42L and the first DC-power terminal 721. At this point, the two chips 93 of the first part of the lower bridge form a complete electrical connection with the external circuit. Similarly, the electrical connection method between the two chips 94 of the second part of the lower bridge and the external circuit is almost the same as that of the two chips 93 of the first part of the lower bridge, which will not be repeated here.

[0087] The bonding wire material in the example of this application can be selected from aluminum bonding wire, copper bonding wire or copper tape, etc. The drive circuit adopts a Kelvin structure, which can reduce the negative feedback effect of the common source parasitic inductance on the drive circuit, and help to increase the switching speed. In the related art, a single-tube package with a Kelvin connection requires at least 4 pins, and 8 chips have a total of 32 pins; the wiring pins in this application are only 20, which not only reduces 12 pins, but also adds NTC temperature monitoring.

[0088] See also Fig.10 and Fig.11 In some examples, some of the wiring terminals are first-shaped terminals T2, and some of the wiring terminals are second-shaped terminals T1; in this example, the first-shaped terminals T2 and the second-shaped terminals T1 have different shapes, and the different shapes may include at least one of length, diameter, and cross-sectional shape. In this example, by using the first-shaped terminals T2 and the second-shaped terminals T1 to match, the wiring terminals of a specific shape can be selected as needed to improve the vibration resistance of the overall structure, which helps to improve the strength of the overall structure.

[0089] In some examples, the connection terminal of the first shape terminal T2 is at least partially a bendable structure; the bendable structure means that at least part of the first shape terminal T2 can be bent, so that the first shape terminal T2 can at least partially form a curved shape. Optionally, the first shape terminal T2 in this example can be partially wavy, and the corresponding part of the wavy structure can have greater bending performance, so that the first shape terminal T2 can be deformed when subjected to force, thereby improving the vibration resistance of the first shape terminal T2.

[0090] In some examples, the diameter of the wiring terminal of the first shape terminal T2 is smaller than the diameter of the wiring terminal of the second shape terminal T1; in this example, the diameter of the first shape terminal T2 is smaller than the second shape terminal T1. As the diameter decreases, the deformability of the first shape terminal T2 can be relatively improved, thereby improving the vibration resistance of the first shape terminal T2.

[0091] In some examples, the length of the connection terminal of the first shape terminal T2 is not less than the length of the connection terminal of the second shape terminal T1. In this example, the length of the first shape terminal T2 is relatively larger, and as the length increases, the deformability of the first shape terminal T2 also increases relatively.

[0092] The above are only implementation methods of the present application, and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A full-bridge packaging structure with multiple chips in parallel, characterized in that: include: DBC substrate, the DBC substrate includes a circuit layer formed by two groups of symmetrically arranged copper foil areas, each of which includes a negative DC- copper foil, an AC copper foil of a lower bridge, and a DC+ copper foil of an upper bridge; The first part of N chips of the lower bridge is welded on the AC copper foil of one copper foil area, and the second part of N chips of the lower bridge is welded on the AC copper foil of another copper foil area; The first part of N chips on the upper bridge are connected to the DC+ copper foil of one copper foil area, and the second part of N chips on the upper bridge are connected to the DC+ copper foil of another copper foil area; The first part of N chips in the lower bridge are connected in parallel, the second part of N chips in the lower bridge are connected in parallel, the first part of N chips in the upper bridge are connected in parallel, the second part of N chips in the upper bridge are connected in parallel, and the first part of N chips in the upper bridge and the first part of N chips in the lower bridge are connected in series, and the second part of N chips in the upper bridge and the second part of N chips in the lower bridge are connected in series to form a full-bridge package.

2. The multi-chip parallel full-bridge packaging structure according to claim 1, characterized in that: The first part of N chips of the lower bridge and the second part of N chips of the lower bridge are mirrored; and / or, the first part of N chips of the upper bridge and the second part of N chips of the upper bridge are mirrored.

3. The multi-chip parallel full-bridge packaging structure according to claim 1, characterized in that: The DBC substrate has a first surface and a second surface that are arranged opposite to each other, and the circuit layer is arranged on the first surface; the DBC substrate also includes a lower copper foil, and the lower copper foil is arranged on the second surface.

4. The multi-chip parallel full-bridge packaging structure as claimed in claim 3, characterized in that: The area of ​​the second surface is S1, and the area of ​​the lower copper foil is not less than 0.9S1.

5. The multi-chip parallel full-bridge packaging structure as claimed in claim 3, characterized in that: The lower copper foil is provided with a plurality of via holes.

6. The multi-chip parallel full-bridge packaging structure according to claim 5, characterized in that: The via holes are distributed in a ring shape close to the edge of the lower copper foil; and / or the center distance between adjacent via holes is not less than 0.9 mm.

7. The multi-chip parallel full-bridge packaging structure according to claim 1, characterized in that: The DBC substrate has a first surface and a second surface that are arranged opposite to each other, and the circuit layer is arranged on the first surface; the area of ​​the first surface is S2, and the area of ​​the circuit layer is not less than 0.9S2.

8. The multi-chip parallel full-bridge packaging structure according to any one of claims 1 to 7, characterized in that: The multi-chip parallel full-bridge packaging structure also includes wiring terminals; the wiring terminals include a DC+ power terminal, a DC- power terminal and an AC power terminal; wherein: The DC+ power terminal and the DC- power terminal are respectively provided in the area corresponding to each copper foil area on the DBC substrate, wherein the DC+ power terminal is electrically connected to the DC+ copper foil of the upper bridge of the corresponding copper foil area; and the DC- power terminal is electrically connected to the negative DC- copper foil of the corresponding copper foil area; and / or An AC power terminal is provided in a region corresponding to each of the copper foil areas on the DBC substrate, and the AC power terminal is electrically connected to the AC copper foil corresponding to the copper foil area.

9. The multi-chip parallel full-bridge packaging structure according to claim 8, characterized in that: Each of the copper foil areas further includes a gate copper foil and an auxiliary source copper foil; the connection terminals further include a gate drive terminal and an auxiliary source drive terminal, wherein: The first part of the N chips of the upper bridge has the gate copper foil electrically connected to the gate and the auxiliary source copper foil electrically connected to the auxiliary source, and the first part of the N chips of the upper bridge respectively have a gate drive terminal electrically connected to the gate copper foil and an auxiliary source drive terminal electrically connected to the auxiliary source copper foil; and / or The second part of the N chips of the upper bridge has the gate copper foil electrically connected to the gate and the auxiliary source copper foil electrically connected to the auxiliary source, and the second part of the N chips of the upper bridge respectively has a gate drive terminal electrically connected to the gate copper foil and an auxiliary source drive terminal electrically connected to the auxiliary source copper foil; and / or The first part of the N chips of the lower bridge has the gate copper foil electrically connected to the gate and the auxiliary source copper foil electrically connected to the auxiliary source, and the first part of the N chips of the lower bridge respectively have a gate drive terminal electrically connected to the gate copper foil and an auxiliary source drive terminal electrically connected to the auxiliary source copper foil; and / or The second part of the N chips of the lower bridge have the gate copper foil electrically connected to the gate and the auxiliary source copper foil electrically connected to the auxiliary source, and the first part of the N chips of the lower bridge respectively have a gate drive terminal electrically connected to the gate copper foil and an auxiliary source drive terminal electrically connected to the auxiliary source copper foil.

10. The multi-chip parallel full-bridge packaging structure according to claim 9, characterized in that: Some of the connection terminals are terminals of the first shape, and some of the connection terminals are terminals of the second shape; wherein: At least part of the connection terminal of the first shape terminal is a bendable structure; and / or The diameter of the first shape terminal is smaller than the diameter of the second shape terminal; and / or The length of the first shape terminal is not less than the length of the second shape terminal.

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