Silicon carbide MOS device
By designing an N-type heavily doped silicon carbide substrate and an N-type epitaxial layer in a silicon carbide MOS device, and setting trenches and gate columns including wide sub-posts and narrow sub-posts in the P-type well region, the problem of slow device response speed is solved and the switching capability of the device is significantly improved.
Patent Information
- Application Number
- CN202421660882.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-12
- Publication Date
- 2025-06-06
- Estimated Expiration
- 2034-07-12
AI Technical Summary
The existing silicon carbide MOS devices have slow response speed, resulting in insufficient switching capabilities and are difficult to meet the demand for efficient and fast switching of power electronic devices.
A silicon carbide MOS device is designed. By introducing an N-type heavily doped silicon carbide substrate and an N-type epitaxial layer into the device, and a trench is provided in the P-type well region. The gate columns including wide sub-posts and narrow sub-posts are provided in the trench. The side surfaces of the gate columns cover the silicon dioxide layer and the P-type heavily doped region respectively, reducing the gate capacitance of the device.
By reducing the gate capacitance of the device, the response speed of the MOS device is significantly improved, thereby improving the switching capability of the device.
Smart Images
Figure CN222954305U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductor devices, in particular to a silicon carbide MOS device. Background Art
[0002] Metal-oxide-semiconductor (MOS) power devices made of silicon carbide materials can switch quickly while withstanding high voltages. In recent years, due to the development of power electronics technology, silicon carbide MOS devices have had a profound impact on the efficiency and miniaturization of power electronic equipment. The response speed of existing silicon carbide MOS devices needs to be improved, and how to improve the switching capability of the device has become the direction of efforts of technicians in this field. Utility Model Content
[0003] The utility model aims to provide a silicon carbide MOS device, which reduces the gate capacitance of the device, increases the response speed of the MOS device, and thus improves the switching capability of the device.
[0004] To achieve the above object, the technical solution adopted by the utility model is: a silicon carbide MOS device, comprising: an N-type heavily doped silicon carbide substrate and an N-type epitaxial layer located on the N-type heavily doped silicon carbide substrate, wherein the surface of the N-type heavily doped silicon carbide substrate opposite to the N-type epitaxial layer has a lower metal electrode layer;
[0005] The upper part of the N-type epitaxial layer has a P-type well region, a trench located in the P-type well region extends into the N-type epitaxial layer, an N-type heavily doped source region is located in the upper part of the P-type well region and around the trench, a gate column is located in the trench, the gate column includes a wide sub-column located at the upper part and a narrow sub-column located below the wide sub-column, a silicon dioxide layer is provided between the side surface of the wide sub-column of the gate column and the upper inner wall of the trench, a P-type heavily doped region is provided between the side surface of the narrow sub-column of the gate column and the lower inner wall of the trench, and the upper surface of the P-type heavily doped region is located below the lower surface of the P-type well region;
[0006] An insulating dielectric layer is located above the trench and covers the gate column, and an upper metal electrode layer is located above the insulating dielectric layer and the N-type heavily doped source region and contacts the upper surfaces of the insulating dielectric layer and the N-type heavily doped source region.
[0007] The further improved scheme in the above technical scheme is as follows:
[0008] 1. In the above scheme, the height ratio of the P-type well region to the trench is 1:2-3.
[0009] 2. In the above solution, the insulating dielectric layer extends in the plane direction to above the inner edge of the N-type heavily doped source region.
[0010] 3. In the above scheme, the height ratio of the wide sub-column to the narrow sub-column is 10:2~4.
[0011] 4. In the above scheme, the width ratio of the P-type heavily doped region to the narrow sub-column is 1:1.5~3.
[0012] 5. In the above solution, the bottom of the gate column in the trench is located below the P-type well region, and the gate column extends to the middle of the N-type epitaxial layer.
[0013] Due to the application of the above technical solution, the utility model has the following advantages compared with the prior art:
[0014] The utility model discloses a silicon carbide MOS device, wherein a gate column is provided in a groove, wherein the gate column comprises a wide sub-column located at an upper portion and a narrow sub-column located below the wide sub-column, wherein a silicon dioxide layer is provided between a side surface of the wide sub-column of the gate column and an upper inner wall of the groove, wherein a P-type heavily doped region is provided between a side surface of the narrow sub-column of the gate column and a lower inner wall of the groove, wherein an upper surface of the P-type heavily doped region is provided below a lower surface of a P-type well region, thereby reducing a gate capacitance of the device, improving a response speed of the MOS device, and thereby improving a switching capability of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Attached Figure 1 It is a schematic diagram of the structure of the silicon carbide MOS device of the utility model.
[0016] In the above figures: 1. N-type heavily doped silicon carbide substrate; 2. N-type epitaxial layer; 3. Lower metal electrode layer; 4. P-type well region; 5. Trench; 6. Gate column; 61. Wide sub-column; 62. Narrow sub-column; 7. Silicon dioxide layer; 8. N-type heavily doped source region; 9. Insulating dielectric layer; 10. Upper metal electrode layer; 11. P-type heavily doped region. DETAILED DESCRIPTION
[0017] The present invention can be further understood through the specific embodiments given below, but they are not intended to limit the present invention.
[0018] Embodiment 1: A silicon carbide MOS device, comprising: an N-type heavily doped silicon carbide substrate 1 and an N-type epitaxial layer 2 located on the N-type heavily doped silicon carbide substrate 1, wherein the surface of the N-type heavily doped silicon carbide substrate 1 opposite to the N-type epitaxial layer 2 has a lower metal electrode layer 3;
[0019] The upper part of the N-type epitaxial layer 2 has a P-type well region 4, a trench 5 located in the P-type well region 4 extends into the N-type epitaxial layer 2, an N-type heavily doped source region 8 is provided in the upper part of the P-type well region 4 and around the trench 5, a gate column 6 is provided in the trench 5, the gate column 6 includes a wide sub-column 61 located at the upper part and a narrow sub-column 62 located below the wide sub-column 61, a silicon dioxide layer 7 is provided between the side surface of the wide sub-column 61 of the gate column 6 and the upper inner wall of the trench 5, a P-type heavily doped region 11 is provided between the side surface of the narrow sub-column 62 of the gate column 6 and the lower inner wall of the trench 5, and the upper surface of the P-type heavily doped region 11 is located below the lower surface of the P-type well region 4;
[0020] An insulating dielectric layer 9 is located above the trench 5 and covers the gate pillar 6 , and an upper metal electrode layer 10 is located above the insulating dielectric layer 9 and the N-type heavily doped source region 8 and contacts the upper surfaces of the insulating dielectric layer 9 and the N-type heavily doped source region 8 .
[0021] The height ratio of the P-type well region 4 to the trench 5 is 1:2.8, and the height ratio of the wide sub-column 61 to the narrow sub-column 62 is 10:3.
[0022] The width ratio of the P-type heavily doped region 11 to the narrow sub-column 62 is 1:2.
[0023] The bottom of the gate column 6 in the trench 5 is located below the P-type well region 4 , and the gate column 6 extends to the middle of the N-type epitaxial layer 2 .
[0024] Embodiment 2: A silicon carbide MOS device, comprising: an N-type heavily doped silicon carbide substrate 1 and an N-type epitaxial layer 2 located on the N-type heavily doped silicon carbide substrate 1, wherein the surface of the N-type heavily doped silicon carbide substrate 1 opposite to the N-type epitaxial layer 2 has a lower metal electrode layer 3;
[0025] The upper part of the N-type epitaxial layer 2 has a P-type well region 4, a trench 5 located in the P-type well region 4 extends into the N-type epitaxial layer 2, an N-type heavily doped source region 8 is provided in the upper part of the P-type well region 4 and around the trench 5, a gate column 6 is provided in the trench 5, the gate column 6 includes a wide sub-column 61 located at the upper part and a narrow sub-column 62 located below the wide sub-column 61, a silicon dioxide layer 7 is provided between the side surface of the wide sub-column 61 of the gate column 6 and the upper inner wall of the trench 5, a P-type heavily doped region 11 is provided between the side surface of the narrow sub-column 62 of the gate column 6 and the lower inner wall of the trench 5, and the upper surface of the P-type heavily doped region 11 is located below the lower surface of the P-type well region 4;
[0026] An insulating dielectric layer 9 is located above the trench 5 and covers the gate pillar 6 , and an upper metal electrode layer 10 is located above the insulating dielectric layer 9 and the N-type heavily doped source region 8 and contacts the upper surfaces of the insulating dielectric layer 9 and the N-type heavily doped source region 8 .
[0027] The height ratio of the P-type well region 4 to the trench 5 is 1:2.2.
[0028] The insulating dielectric layer 9 extends in the plane direction to above the inner edge of the N-type heavily doped source region 8 .
[0029] The height ratio of the wide sub-column 61 to the narrow sub-column 62 is 10:3.5, and the width ratio of the P-type heavily doped region 11 to the narrow sub-column 62 is 1:2.8.
[0030] When the above-mentioned silicon carbide MOS device is used, a gate column 6 is provided in the groove 5, and the gate column 6 includes a wide sub-column 61 located at the top and a narrow sub-column 62 located below the wide sub-column 61. A silicon dioxide layer 7 is provided between the side surface of the wide sub-column 61 of the gate column 6 and the upper inner wall of the groove 5. A P-type heavily doped region 11 is provided between the side surface of the narrow sub-column 62 of the gate column 6 and the lower inner wall of the groove 5. The upper surface of the P-type heavily doped region 11 is located below the lower surface of the P-type well region 4, which reduces the gate capacitance of the device, improves the response speed of the MOS device, and thus improves the switching capability of the device.
[0031] The above embodiments are only for illustrating the technical concept and features of the utility model, and their purpose is to enable people familiar with the technology to understand the content of the utility model and implement it accordingly, and they cannot be used to limit the protection scope of the utility model. Any equivalent changes or modifications made according to the spirit of the utility model should be included in the protection scope of the utility model.
Claims
1. A silicon carbide MOS device, characterized in that: include: An N-type heavily doped silicon carbide substrate (1) and an N-type epitaxial layer (2) located on the N-type heavily doped silicon carbide substrate (1), wherein the surface of the N-type heavily doped silicon carbide substrate (1) opposite to the N-type epitaxial layer (2) has a lower metal electrode layer (3); The upper part of the N-type epitaxial layer (2) has a P-type well region (4), a trench (5) located in the P-type well region (4) extends into the N-type epitaxial layer (2), the upper part of the P-type well region (4) and located around the trench (5) has an N-type heavily doped source region (8), the trench (5) has a gate column (6), the gate column (6) comprises a wide sub-column (61) located at the upper part and a narrow sub-column (62) located below the wide sub-column (61), a silicon dioxide layer (7) is provided between the side surface of the wide sub-column (61) of the gate column (6) and the upper inner wall of the trench (5), a P-type heavily doped region (11) is provided between the side surface of the narrow sub-column (62) of the gate column (6) and the lower inner wall of the trench (5), the upper surface of the P-type heavily doped region (11) is located below the lower surface of the P-type well region (4); An insulating dielectric layer (9) is located above the trench (5) and covers the gate column (6); an upper metal electrode layer (10) is located above the insulating dielectric layer (9) and the N-type heavily doped source region (8) and is in contact with the upper surfaces of the insulating dielectric layer (9) and the N-type heavily doped source region (8).
2. The silicon carbide MOS device according to claim 1, characterized in that: The height ratio between the P-type well region (4) and the trench (5) is 1:2-3.
3. The silicon carbide MOS device according to claim 1, characterized in that: The insulating dielectric layer (9) extends in a planar direction to above the inner edge of the N-type heavily doped source region (8).
4. The silicon carbide MOS device according to claim 1, characterized in that: The height ratio of the wide sub-column (61) to the narrow sub-column (62) is 10:2-4.
5. The silicon carbide MOS device according to claim 1, characterized in that: The width ratio of the P-type heavily doped region (11) to the narrow sub-column (62) is 1:1.5-3.
6. The silicon carbide MOS device according to claim 1, characterized in that: The bottom of the gate column (6) in the trench (5) is located below the P-type well region (4), and the gate column (6) extends to the middle of the N-type epitaxial layer (2).