Silicon carbide semiconductor device

Abstract

The utility model discloses a silicon carbide semiconductor device which comprises an N-type heavily doped silicon carbide substrate and an N-type lightly doped epitaxial layer located on the N-type heavily doped silicon carbide substrate, and the N-type lightly doped epitaxial layer comprises at least two device unit cells. A lower metal electrode layer is arranged on the surface, opposite to the N-type lightly-doped epitaxial layer, of the N-type heavily-doped silicon carbide substrate; the P-type well region between the adjacent device unit cells is internally provided with a second groove, the second groove is filled with an N-type heavily doped part, two sides of the N-type heavily doped part are respectively provided with a first N-type injection part and a second N-type injection part, and the depth of the first N-type injection part and the depth of the second N-type injection part are both lower than that of the second groove. According to the silicon carbide semiconductor device, the doping concentration of the lightly doped N-type drift region can be improved, and the on resistance is reduced when the silicon carbide semiconductor device is turned off under the condition that the withstand voltage is increased.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductor devices, in particular to a silicon carbide semiconductor device. Background Art

[0002] Silicon carbide (SiC) metal oxide semiconductor field effect transistor (MOSFET) is a unipolar voltage control device with majority carrier conduction, which has the advantages of fast switching speed, good high-frequency performance, and high reverse voltage. Therefore, it has been increasingly used in high-performance switching power supplies, motor control, smart grids, electric vehicles, and rail transportation. Existing silicon carbide MOS devices have a large leakage current in the off state, which leads to increased power loss. How to solve the above technical problems has become the technical direction of the technical personnel in this field. Utility Model Content

[0003] The utility model aims to provide a silicon carbide semiconductor device, which is beneficial to suppressing the leakage current between the source and drain of the MOS device in the off state, thereby reducing the static loss of the MOS device and improving the reliability of the device.

[0004] To achieve the above-mentioned object, the technical solution adopted by the utility model is: a silicon carbide semiconductor device, comprising: an N-type heavily doped silicon carbide substrate and an N-type lightly doped epitaxial layer located on the N-type heavily doped silicon carbide substrate, the N-type lightly doped epitaxial layer comprising at least two device cells, and the surface of the N-type heavily doped silicon carbide substrate opposite to the N-type lightly doped epitaxial layer having a lower metal electrode layer;

[0005] The device unit cell further comprises: a P-type well region located on the upper part of the N-type lightly doped epitaxial layer and a first trench located in the P-type well region, the first trench extending into the N-type lightly doped epitaxial layer, an N-type heavily doped source region located in the upper part of the P-type well region and around the first trench, and a gate column in the first trench;

[0006] An insulating dielectric layer is located above the first trench and covers the gate pillar, and an upper metal electrode layer is located above the insulating dielectric layer and the N-type heavily doped source region and contacts the upper surfaces of the insulating dielectric layer and the N-type heavily doped source region;

[0007] A second trench is provided in the P-type well region between adjacent device cells, and an N-type heavily doped portion is filled in the second trench. A first N-type injection portion and a second N-type injection portion are respectively provided on both sides of the N-type heavily doped portion, and the depths of the first N-type injection portion and the second N-type injection portion are both lower than the depth of the second trench.

[0008] The further improved scheme in the above technical scheme is as follows:

[0009] 1. In the above solution, the first N-type injection portion and the second N-type injection portion are located in the P-type well region.

[0010] 2. In the above solution, the height ratio of the first N-type injection part and the second N-type injection part to the P-type well region is 10:12-15.

[0011] 3. In the above solution, the insulating dielectric layer extends in the plane direction to above the inner edge of the N-type heavily doped source region.

[0012] Due to the application of the above technical solution, the utility model has the following advantages compared with the prior art:

[0013] The utility model discloses a trench-type high-power MOSFET device, which comprises at least two device cells on an N-type lightly doped epitaxial layer, a second trench is provided in a P-type well region between adjacent device cells, the second trench is filled with an N-type heavily doped portion, and a first N-type injection portion and a second N-type injection portion are respectively provided on both sides of the N-type heavily doped portion, the depths of the first N-type injection portion and the second N-type injection portion are both lower than the depth of the second trench, which is beneficial to suppressing the leakage current between the source and the drain of the MOS device in a closed state, thereby reducing the static loss of the MOS device and improving the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Attached Figure 1 It is a schematic structural diagram of the silicon carbide semiconductor device of the utility model.

[0015] In the above figures: 1. N-type heavily doped silicon carbide substrate; 2. N-type lightly doped epitaxial layer; 3. Lower metal electrode layer; 4. P-type well region; 5. Groove; 6. Gate column; 7. Silicon dioxide layer; 8. N-type heavily doped source region; 9. Insulating dielectric layer; 10. Upper metal electrode layer; 11. First N-type injection part; 12. Device unit cell; 13. Second trench; 14. N-type heavily doped part; 15. Second N-type injection part. DETAILED DESCRIPTION

[0016] The present invention can be further understood through the specific embodiments given below, but they are not intended to limit the present invention.

[0017] Embodiment 1: A silicon carbide semiconductor device, comprising: an N-type heavily doped silicon carbide substrate 1 and an N-type lightly doped epitaxial layer 2 located on the N-type heavily doped silicon carbide substrate 1, the N-type lightly doped epitaxial layer 2 comprising at least two device cells 12, and a lower metal electrode layer 3 is provided on the surface of the N-type heavily doped silicon carbide substrate 1 opposite to the N-type lightly doped epitaxial layer 2;

[0018] The device unit cell 12 further comprises: a P-type well region 4 located on the upper part of the N-type lightly doped epitaxial layer 2 and a first trench 5 located in the P-type well region 4, the first trench 5 extending into the N-type lightly doped epitaxial layer 2, an N-type heavily doped source region 8 located in the upper part of the P-type well region 4 and around the first trench 5, and a gate column 6 in the first trench 5;

[0019] An insulating dielectric layer 9 is located above the first trench 5 and covers the gate pillar 6, and an upper metal electrode layer 10 is located above the insulating dielectric layer 9 and the N-type heavily doped source region 8 and contacts the upper surfaces of the insulating dielectric layer 9 and the N-type heavily doped source region 8;

[0020] A second trench 13 is provided in the P-type well region 4 between adjacent device cells 12, and the second trench 13 is filled with an N-type heavily doped portion 14. A first N-type injection portion 11 and a second N-type injection portion 15 are respectively provided on both sides of the N-type heavily doped portion 14, and the depths of the first N-type injection portion 11 and the second N-type injection portion 15 are both lower than the depth of the second trench 13.

[0021] The first N-type implantation portion 11 and the second N-type implantation portion 15 are located in the P-type well region 4 .

[0022] The height ratio of the first N-type implantation portion 11 and the second N-type implantation portion 15 to the P-type well region 4 is 10:12-15.

[0023] The insulating dielectric layer 9 extends in the plane direction to above the inner edge of the N-type heavily doped source region 8 .

[0024] Embodiment 2: A silicon carbide semiconductor device, comprising: an N-type heavily doped silicon carbide substrate 1 and an N-type lightly doped epitaxial layer 2 located on the N-type heavily doped silicon carbide substrate 1, the N-type lightly doped epitaxial layer 2 comprising at least two device cells 12, and a lower metal electrode layer 3 is provided on a surface of the N-type heavily doped silicon carbide substrate 1 opposite to the N-type lightly doped epitaxial layer 2;

[0025] The device unit cell 12 further comprises: a P-type well region 4 located on the upper part of the N-type lightly doped epitaxial layer 2 and a first trench 5 located in the P-type well region 4, the first trench 5 extending into the N-type lightly doped epitaxial layer 2, an N-type heavily doped source region 8 located in the upper part of the P-type well region 4 and around the first trench 5, and a gate column 6 in the first trench 5;

[0026] An insulating dielectric layer 9 is located above the first trench 5 and covers the gate pillar 6, and an upper metal electrode layer 10 is located above the insulating dielectric layer 9 and the N-type heavily doped source region 8 and contacts the upper surfaces of the insulating dielectric layer 9 and the N-type heavily doped source region 8;

[0027] A second trench 13 is provided in the P-type well region 4 between adjacent device cells 12, and the second trench 13 is filled with an N-type heavily doped portion 14. A first N-type injection portion 11 and a second N-type injection portion 15 are respectively provided on both sides of the N-type heavily doped portion 14, and the depths of the first N-type injection portion 11 and the second N-type injection portion 15 are both lower than the depth of the second trench 13.

[0028] The first N-type implantation portion 11 and the second N-type implantation portion 15 are located in the P-type well region 4 .

[0029] The height ratio of the first N-type implantation portion 11 and the second N-type implantation portion 15 to the P-type well region 4 is 10:12-15.

[0030] The insulating dielectric layer 9 extends in the plane direction to above the inner edge of the N-type heavily doped source region 8 .

[0031] When the above-mentioned silicon carbide semiconductor device is used, a second groove is provided in the P-type well region between adjacent device cells, and an N-type heavily doped portion is filled in the second groove. A first N-type injection portion and a second N-type injection portion are respectively provided on both sides of the N-type heavily doped portion. The depths of the first N-type injection portion and the second N-type injection portion are both lower than the depth of the second groove, which is beneficial to suppressing the leakage current between the source and the drain of the MOS device in the off state, thereby reducing the static loss of the MOS device and improving the reliability of the device.

[0032] The above embodiments are only for illustrating the technical concept and features of the utility model, and their purpose is to enable people familiar with the technology to understand the content of the utility model and implement it accordingly, and they cannot be used to limit the protection scope of the utility model. Any equivalent changes or modifications made according to the spirit of the utility model should be included in the protection scope of the utility model.

Claims

1. A silicon carbide semiconductor device, characterized in that: include: An N-type heavily doped silicon carbide substrate (1) and an N-type lightly doped epitaxial layer (2) located on the N-type heavily doped silicon carbide substrate (1), wherein the N-type lightly doped epitaxial layer (2) comprises at least two device cells (12), and the surface of the N-type heavily doped silicon carbide substrate (1) opposite to the N-type lightly doped epitaxial layer (2) has a lower metal electrode layer (3); The device unit cell (12) further comprises: a P-type well region (4) located on the upper part of the N-type lightly doped epitaxial layer (2) and a first trench (5) located in the P-type well region (4), the first trench (5) extending into the N-type lightly doped epitaxial layer (2), an N-type heavily doped source region (8) located in the upper part of the P-type well region (4) and around the first trench (5), and a gate column (6) in the first trench (5); An insulating dielectric layer (9) is located above the first trench (5) and covers the gate column (6); an upper metal electrode layer (10) is located above the insulating dielectric layer (9) and the N-type heavily doped source region (8) and is in contact with the upper surfaces of the insulating dielectric layer (9) and the N-type heavily doped source region (8); A second trench (13) is provided in the P-type well region (4) between adjacent device cells (12); an N-type heavily doped portion (14) is filled in the second trench (13); and a first N-type injection portion (11) and a second N-type injection portion (15) are provided on both sides of the N-type heavily doped portion (14); the depths of the first N-type injection portion (11) and the second N-type injection portion (15) are both lower than the depth of the second trench (13).

2. The silicon carbide semiconductor device according to claim 1, characterized in that: The first N-type injection portion (11) and the second N-type injection portion (15) are located in the P-type well region (4).

3. The silicon carbide semiconductor device according to claim 2, characterized in that: The height ratio of the first N-type injection portion (11) and the second N-type injection portion (15) to the P-type well region (4) is 10:12-15.

4. The silicon carbide semiconductor device according to claim 1, wherein: The insulating dielectric layer (9) extends in a planar direction to above the inner edge of the N-type heavily doped source region (8).

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