High-density integrated filtering device and electronic device

Abstract

The utility model discloses a high-density integrated filtering device and an electronic device. The filtering device comprises a first substrate, first to fifth capacitive units, first to third inductive units, first and second common ports, first and second potential ends, and first and second input and output ports. The first capacitive unit is arranged on a coupling path between the first common port and the first input and output port, the second capacitive unit is arranged on a coupling path between the first common port and the second common port, and the third inductive unit and the third capacitive unit are arranged on a coupling path between the first common port and the first potential end. The first inductive unit is coupled with the third capacitive unit; the fourth capacitive unit and the fifth capacitive unit are arranged on a coupling path between the second common port and the second potential end, the second inductive unit is coupled with the fifth capacitive unit, and the second common port is coupled with the second input and output port. According to the utility model, the out-of-band rejection performance of the device is improved, and the device has the advantages of miniaturization and high frequency selection characteristic.

Description

Technical Field

[0001] The embodiments of the present utility model relate to the technical field of filters, and in particular, to a high-density integrated filtering device and an electronic device. Background Art

[0002] The demand for communication terminals that can support multiple modes and cover multiple frequency bands in modern communication technology is increasing day by day. Among these communication terminals, the radio frequency filter is a crucial component, and its function is to allow specific frequency signals to pass through and effectively filter out unwanted signals. With the continuous evolution of communication standards, the interval between the frequency bands used by different communication channels is getting smaller and smaller, so a band-pass filter with more stringent out-of-band rejection performance is required.

[0003] The design of the circuit topology of the filter directly affects the size, integration, and frequency selection ability of the filter. In order to achieve more excellent frequency selection performance, the method of increasing the filter order is usually adopted. However, this method will inevitably significantly increase the number of filter components and the overall structural complexity. Especially in the lumped parameter-based design, increasing the order will directly lead to an increase in inductance components, thereby further increasing the size of the filter. This poses a severe challenge to the miniaturization and high-integration design of filters in high-density radio frequency integrated circuit systems. Summary of the Utility Model

[0004] Aiming at the above problems, the purpose of the present utility model is to provide a high-density integrated filtering device and an electronic device with miniaturization and high roll-off. The high-density integrated filtering device proposed by the present utility model realizes the multi-transmission zero frequency response characteristic with a limited number of resonators through the reasonable configuration of capacitive units and inductive units, improves the out-of-band rejection performance of the high-density integrated filtering device, and has the advantages of miniaturization and high frequency selection characteristics.

[0005] According to one aspect of the present utility model, a high-density integrated filtering device is provided, comprising: a first substrate, a first capacitive unit, a second capacitive unit, a third capacitive unit, a fourth capacitive unit, a fifth capacitive unit, a first inductive unit, a second inductive unit, a third inductive unit, a first common port, a second common port, a first potential terminal, a second potential terminal, a first input / output port, and a second input / output port. The first capacitive unit is disposed on the coupling path between the first common port and the first input / output port, the second capacitive unit is disposed on the coupling path between the first common port and the second common port, the third capacitive unit is disposed on the coupling path between the first common port and the first potential terminal, the first inductive unit is coupled to the third capacitive unit, the third inductive unit is disposed on the coupling path between the first common port and the first potential terminal, and the third inductive unit is coupled to the third capacitive unit. The fourth capacitive unit and the fifth capacitive unit are disposed on the coupling path between the second common port and the second potential terminal, the fourth capacitive unit is coupled to the fifth capacitive unit, the second inductive unit is coupled to the fifth capacitive unit, and the second common port is coupled to the second input / output port. The first capacitive unit is coupled to the second capacitive unit through the first common port, the second capacitive unit is coupled to the third capacitive unit through the first common port, the second capacitive unit is coupled to the fourth capacitive unit through the second common port, and the fourth capacitive unit is coupled to the second input / output port through the second common port. The first substrate includes one or more dielectric layers disposed along the stacking direction, and at least a part of the first to fifth capacitive units and / or the first to third inductive units is formed inside or on the surface of the first substrate. The first to eighth capacitive units are formed by coupling metallized electrodes.

[0006] Optionally, it further includes a sixth capacitive unit, which is disposed on the coupling path between the second common port and the second input / output port, and the sixth capacitive unit is coupled to the fourth capacitive unit through the second common port. In this case, it is beneficial to adjust the impedance matching between the high-density integrated filtering device and the outside.

[0007] Optionally, it further includes a seventh capacitive unit, which is disposed on the coupling path between the first capacitive unit and the first input / output port. In this case, it is beneficial to adjust the impedance matching between the high-density integrated filtering device and the outside.

[0008] Optionally, it further includes a fourth inductive unit, which is disposed on the coupling path between the first capacitive unit and the first input / output port, and the fourth inductive unit is coupled in parallel with the seventh capacitive unit. In this case, it is beneficial to further increase the out-of-band rejection performance of the high-density integrated filtering device.

[0009] Optionally, it further includes a fifth inductive unit, which is arranged on the coupling path between the second common port and the second potential terminal, and the fifth inductive unit is coupled with the fifth capacitive unit. In this case, it is beneficial to further improve the out-of-band rejection performance of the high-density integrated filtering device.

[0010] Optionally, it further includes an eighth capacitive unit, which is arranged on the coupling path between the first common port and the first potential terminal, and the eighth capacitive unit is coupled with the third capacitive unit. In this case, it is beneficial to improve the flexibility of circuit impedance matching.

[0011] Optionally, it further includes a ninth capacitive unit and a third common port. The third common port is arranged on the coupling path between the first input / output port and the first capacitive unit. The ninth capacitive unit is arranged on the coupling path between the third common port and the third inductive unit. The eighth capacitive unit is arranged on the coupling path between the third inductive unit and the first common port. The eighth capacitive unit is coupled with the third capacitive unit through the third inductive unit. In this case, it is beneficial to further improve the out-of-band selectivity performance of the filtering device.

[0012] Optionally, it further includes a sixth inductive unit, which is arranged on the coupling path between the first common port and the second common port, and the sixth inductive unit is coupled in parallel with the second capacitive unit. In this case, it is beneficial to further improve the out-of-band rejection performance of the high-density integrated filtering device.

[0013] Optionally, it further includes a third potential terminal, and the first inductive unit is arranged on the coupling path between the first common port and the third potential terminal.

[0014] Optionally, it further includes a fourth potential terminal, and the second inductive unit is arranged on the coupling path between the second common port and the fourth potential terminal.

[0015] Optionally, it further includes a tenth capacitive unit and a fifth potential terminal. The tenth capacitive unit is arranged on the coupling path between the third common port and the fifth potential terminal. The tenth capacitive unit is coupled with the ninth capacitive unit and the first capacitive unit through the third common port. At least part of the tenth capacitive unit is formed inside or on the surface of the first substrate.

[0016] Optionally, it further includes a seventh inductive unit, which is arranged on the coupling path between the third common port and the fifth potential terminal, and the seventh inductive unit is coupled with the tenth capacitive unit. In this case, it is beneficial to improve the out-of-band rejection performance of the high-density integrated filtering device.

[0017] Optionally, it further includes an eleventh capacitive unit and a sixth potential terminal. The eleventh capacitive unit is disposed on the coupling path between the first input / output port and the sixth potential terminal, and at least part of the eleventh capacitive unit is formed inside or on the surface of the first substrate. In this case, it is convenient to adjust the external impedance of the first input / output port, which is beneficial to improving the flexibility of circuit impedance matching and also beneficial to enhancing the out-of-band rejection performance of the high-density integrated filtering device.

[0018] Optionally, it further includes an eighth inductive unit. The eighth inductive unit is disposed on the coupling path between the first common port and the first input / output port and is coupled in parallel with the first capacitive unit.

[0019] Optionally, the material of the first substrate includes any one of silicon, gallium arsenide, silicon carbide, gallium nitride, gallium oxide, diamond, indium phosphide, glass, sapphire, aluminum oxide, aluminum nitride, silicon nitride, silicon oxide, and polyimide.

[0020] Optionally, it further includes a second substrate formed by laminating one or more dielectric layers in the lamination direction. The first substrate and the second substrate are sequentially arranged in the lamination direction, the first substrate is fixed to the second substrate, and the capacitive unit and / or the inductive unit are at least partially formed inside or on the surface of the second substrate. The first substrate and the second substrate are electromagnetically coupled via one or more connectors between them. The connectors include at least one of metal bumps, copper pillars, solder balls, gold wires, and solder bumps. In this case, the three-dimensional layout space of the structure is expanded, which is beneficial to reducing the planar size required for the high-density integrated filtering device.

[0021] Optionally, the inductive unit is formed by a metal trace, and the metal trace is formed in a shape extending in the form of a broken line, an arc, a spiral, or a combination thereof.

[0022] Optionally, the inductive unit includes a plurality of metal traces formed in different dielectric layers and a plurality of metallized conduction pillars interconnecting them, and the conduction pillars extend in the lamination direction. In this case, it is beneficial to reduce the planar size of the inductive unit and improve the miniaturization performance of the high-density integrated filtering device.

[0023] Optionally, the projection of the metal trace on the plane perpendicular to the lamination direction is formed to surround a point with the point as the center.

[0024] Optionally, the metal traces are formed in different dielectric layers and are substantially aligned in the lamination direction, and the projection of the inductive unit on the plane perpendicular to the lamination direction forms a closed figure. In this case, it is beneficial to reduce the planar size occupied by the metal traces and improve the miniaturization performance of the high-density integrated filtering device.

[0025] Optionally, the number of turns of each metal trace does not exceed one turn.

[0026] Optionally, the first potential terminal and the second potential terminal are at the same potential.

[0027] Optionally, the first to eighth capacitive units are configured to be arranged along a first direction.

[0028] Optionally, the projections of the first to eighth capacitive units on a plane perpendicular to the stacking direction extend along the first direction.

[0029] Optionally, the first to third inductive units are arranged on the same side of the first to eighth capacitive units. In this case, it is beneficial to improve the space utilization rate of the layout.

[0030] Optionally, the first inductive unit, the second inductive unit, and the third inductive unit are arranged along the first direction.

[0031] Optionally, the projections of the first inductive unit, the second inductive unit, and the third inductive unit on a plane perpendicular to the first direction at least partially overlap. In this case, it is beneficial to improve the space utilization rate of the layout.

[0032] Optionally, at least part of the structures of the first to third inductive units are formed on the surfaces or inside of the first substrate and the second substrate simultaneously. In this case, it is beneficial to increase the flexibility of the layout.

[0033] According to another aspect of the present invention, there is provided an electronic device including the high-density integrated filtering device according to any embodiment of the present invention.

[0034] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. Description of the Drawings

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0036] Figure 1 is a circuit schematic diagram of a high-density integrated filtering device provided by an embodiment of the present invention;

[0037] Figure 2 is a circuit schematic diagram of a high-density integrated filtering device provided by another embodiment of the present invention;

[0038] Figure 3 It is a circuit schematic diagram of a high-density integrated filtering device provided by another embodiment of the present utility model;

[0039] Figure 4 It is a circuit schematic diagram of a high-density integrated filtering device provided by another embodiment of the present utility model;

[0040] Figure 5 It is a circuit schematic diagram provided by another embodiment of the present utility model;

[0041] Figure 6 It is a circuit schematic diagram of a high-density integrated filtering device provided by another embodiment of the present utility model;

[0042] Figure 7 It is a circuit schematic diagram of a high-density integrated filtering device provided by another embodiment of the present utility model;

[0043] Figure 8 It is a circuit schematic diagram of a high-density integrated filtering device provided by another embodiment of the present utility model;

[0044] Figure 9 It is a circuit schematic diagram of a high-density integrated filtering device provided by another embodiment of the present utility model;

[0045] Figure 10 It is a circuit schematic diagram of a high-density integrated filtering device provided by another embodiment of the present utility model;

[0046] Figure 11 It is a circuit schematic diagram of a high-density integrated filtering device provided by another embodiment of the present utility model;

[0047] Figure 12 It is a structural schematic diagram of the capacitive unit included in the high-density integrated filtering device 104C;

[0048] Figure 13 is Figure 12 a top view of the structure shown;

[0049] Figure 14 It shows a projection schematic diagram of a capacitive unit of a modified example;

[0050] Figure 15 It is a projection schematic diagram of the first to ninth capacitive units provided by the embodiment of the present utility model on a plane perpendicular to the stacking direction;

[0051] Figure 16 It is a structural schematic diagram of the inductive unit included in the high-density integrated filtering device 104C;

[0052] Figure 17 is Figure 16 a top view of the structure shown;

[0053] Figure 18 shows a schematic diagram of the overall structure of the high-density integrated filtering device 104C provided by an embodiment of the present invention;

[0054] Figure 19 is a graph of the insertion loss and return loss characteristics of the high-density integrated filtering device 104C provided by an embodiment of the present invention;

[0055] Figure 20 is a side view of a high-density integrated filtering device provided by an embodiment of the present invention;

[0056] Figure 21 shows a schematic diagram of the structures of various electronic devices that can be integrated with the high-density integrated filtering device of any of the foregoing embodiments and their variants. Detailed implementation manners

[0057] To facilitate understanding of the present invention, the present invention will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present invention more thorough and comprehensive.

[0058] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present invention belongs. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0059] It should be understood that when an element or layer is referred to as "on", "connected to" another element or layer, it can be directly on or connected to the other element or layer, or there may be intervening elements or layers. It should be understood that although the terms first, second, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present invention, the first module, component, region, layer, or part discussed below may be referred to as the second module, component, region, layer, or part; for example, the first direction may be referred to as the second direction, and similarly, the second direction may be referred to as the first direction; the first direction and the second direction are different directions.

[0060] Spatial relationship terms such as "disposed on", "located above", etc. can be used herein to describe the relationship of one element or feature shown in the figure with other elements or features. It should be understood that, in addition to the orientations shown in the figure, spatial relationship terms also include different orientations of the device during use and operation. For example, if the device in the attached drawing is flipped, the element or feature described as "disposed on", "located above" will be oriented "below" other elements or features. Therefore, the exemplary terms "disposed on" and "located above" can include both upper and lower orientations. In addition, the device may also include additional orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are accordingly interpreted.

[0061] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that when the terms "comprise" and / or "include" are used in this specification, the presence of the stated features, integers, steps, operations, elements and / or components can be determined, but one or more other features, integers, steps, operations, elements, components and / or groups are not excluded from being present or added. At the same time, as used herein, the term "and / or" includes any and all combinations of the related listed items.

[0062] Embodiments of the present invention are described herein with reference to schematic illustrations of ideal embodiments (and intermediate structures) of the present invention, and such variations in the shown shapes due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the present invention should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing techniques. The regions shown in the figures are substantially schematic, their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the present invention.

[0063] Embodiments of the present invention provide a high-density integrated filtering device. Figure 1 is a circuit schematic diagram of a high-density integrated filtering device provided by an embodiment of the present invention, refer to Figure 1, the high-density integrated filtering device 100 includes a first capacitive unit C1, a second capacitive unit C2, a third capacitive unit C3, a fourth capacitive unit C4, a fifth capacitive unit C5, a first inductive unit L1, a second inductive unit L2, a third inductive unit L3, a first common port P1, a second common port P2, a first potential terminal D1, a second potential terminal D2, a first input / output port S1, and a second input / output port S2. The first capacitive unit C1 is arranged on the coupling path between the first common port P1 and the first input / output port S1. The second capacitive unit C2 is arranged on the coupling path between the first common port P1 and the second common port P2. The third capacitive unit C3 is arranged on the coupling path between the first common port P1 and the first potential terminal D1. The first inductive unit L1 is coupled in parallel with the third capacitive unit C3. The third inductive unit L3 is arranged on the coupling path between the first common port P1 and the first potential terminal D1. The third inductive unit L3 is coupled with the third capacitive unit C3. The fourth capacitive unit C4 and the fifth capacitive unit C5 are arranged on the coupling path between the second common port P2 and the second potential terminal D2. The fourth capacitive unit C4 is coupled with the fifth capacitive unit C5. The second inductive unit L2 is coupled in parallel with the fifth capacitive unit C5. The second common port P2 is coupled with the second input / output port S2. The first capacitive unit C1 is coupled with the second capacitive unit C2 through the first common port P1. The second capacitive unit C2 is coupled with the third capacitive unit C3 through the first common port P1. The second capacitive unit C2 is coupled with the fourth capacitive unit C4 through the second common port P2. The fourth capacitive unit C4 is coupled with the second input / output port S2 through the second common port P2. The first substrate 10 includes one or more dielectric layers arranged along the stacking direction Z. The first to fifth capacitive units C1-C5 and / or the first to third inductive units L1-L3 are at least partially formed inside or on the surface of the first substrate 10. The first to eighth capacitive units C1-C5 are formed by metallized electrodes coupled together. The first capacitive unit C1, the second capacitive unit C2, the third capacitive unit C3, the fourth capacitive unit C4, and the fifth capacitive unit C5 exhibit capacitive reactance within the operating frequency band of the high-density integrated filtering device 100. The first inductive unit L1, the second inductive unit L2, and the third inductive unit L3 exhibit inductive reactance within the operating frequency band of the high-density integrated filtering device 100. The first potential terminal D1 and the second potential terminal D2 are at the same potential and are at the same potential as the reference ground. By designing to reduce the number of inductors in the circuit and decrease the equivalent inductance value, the space occupied by the physical implementation of the inductive unit can be effectively reduced, which is beneficial to the miniaturization of the filter. In the present invention, through the configuration of the first to fifth capacitive units C1-C5, the frequency response performance of multiple out-of-band transmission zeros is achieved only with three inductive units. Based on a limited resonator structure, the filtering frequency response characteristic of multiple transmission zeros is realized, and the out-of-band rejection performance of the filtering device is improved.Therefore, the high-density integrated filtering device disclosed by the present utility model has the advantages of miniaturization and high-frequency selection characteristics. Secondly, the required equivalent inductance values of the first inductive unit L1, the second inductive unit L2, and the third inductive unit L3 are smaller than those of the conventional elliptic function topology, reducing the occupied area of the physical structure corresponding to the required equivalent inductance value of the resonant unit, thereby further realizing the miniaturization of the filter. Therefore, the high-density integrated filtering device disclosed by the present utility model has outstanding miniaturization ability. Reference. Figure 1 The third inductive unit L3 can also be arranged between the third capacitive unit C3 and the first common port P1.

[0064] Furthermore, the high-density integrated filtering device 101 of another embodiment includes a sixth capacitive unit C6. Refer to Figure 2 The sixth capacitive unit C6 is arranged on the coupling path between the second common port P2 and the second input / output port S2. The sixth capacitive unit C6 is coupled to the fourth capacitive unit C4 through the second common port P2. The sixth capacitive unit C6 exhibits capacitive reactance within the operating frequency band of the high-density integrated filtering device 101. In this case, it is beneficial to adjust the impedance matching between the high-density integrated filtering device and the outside.

[0065] The high-density integrated filtering device 102 of another embodiment includes a seventh capacitive unit C7. Refer to Figure 3 , The seventh capacitive unit C7 is arranged on the coupling path between the first capacitive unit C1 and the first input / output port P1. The seventh capacitive unit C7 exhibits capacitive reactance within the operating frequency band of the high-density integrated filtering device 102. In this case, by arranging the seventh capacitive unit C7, it is beneficial to adjust the impedance matching between the high-density integrated filtering device and the outside.

[0066] Furthermore, refer to Figure 4 , A fourth inductive unit L4 can also be arranged on the coupling path between the first capacitive unit C1 and the first input / output port S1 of the high-density integrated filtering device 102A. The fourth inductive unit L4 is coupled in parallel with the seventh capacitive unit C7. In this case, it is beneficial to improve the out-of-band rejection performance of the high-density integrated filtering device.

[0067] Furthermore, the high-density integrated filtering device 103 of another embodiment includes a fifth inductive unit L5. Refer to Figure 5 , The fifth inductive unit L5 is arranged on the coupling path between the second common port P2 and the second potential terminal D2. The fifth inductive unit L5 is coupled to the fifth capacitive unit C5. In this case, it is beneficial to further increase the out-of-band rejection performance of the high-density integrated filtering device.

[0068] Furthermore, the high-density integrated filtering device 104 of another embodiment includes an eighth capacitive unit C8. Refer toFigure 6 , the eighth capacitive unit C8 is disposed on the coupling path between the first common port P1 and the first potential terminal D1, and the eighth capacitive unit C8 is coupled to the third capacitive unit C3. The eighth capacitive unit C8 exhibits capacitive reactance within the operating frequency band of the high-density integrated filtering device 104. In this case, it is beneficial to improve the flexibility of circuit impedance matching.

[0069] In another variant, referring to Figure 7 , a circuit schematic diagram of the high-density integrated filtering device 104A is shown. In this variant, the third inductive unit L3 is disposed between the third capacitive unit C3 and the first common port P1, the third common port P3 is disposed on the coupling path between the first input / output port S1 and the first capacitive unit C1, the ninth capacitive unit C9 is disposed on the coupling path between the third common port P3 and the third inductive unit L3, and the eighth capacitive unit C8 is disposed on the coupling path between the third inductive unit L3 and the first common port P1. The eighth capacitive unit C8 is coupled to the third capacitive unit C3 through the third inductive unit L3. In this case, it is beneficial to further improve the out-of-band selectivity performance of the filtering device.

[0070] Furthermore, referring to Figure 8 , a sixth inductive unit L6 is disposed on the coupling path between the first common port P1 and the second common port P2 of the high-density integrated filtering device 104B, and the sixth inductive unit L6 is coupled in parallel with the second capacitive unit C2, which is beneficial to further increase the out-of-band rejection degree of the filtering device. The high-density integrated filtering device 104B further includes a third potential terminal D3 and a fourth potential terminal D4. The first inductive unit L1 is disposed on the coupling path between the first common port P1 and the third potential terminal D3, and the first inductive unit L1 is coupled to the third capacitive unit C3. The second inductive unit is disposed on the coupling path between the second common port P2 and the fourth potential terminal D4.

[0071] In addition, as Figure 9 shows, in the high-density integrated filtering device 104C, the third inductive unit L3 is disposed on the coupling path between the third capacitive unit C3 and the first potential terminal D1, and the second inductive unit L2 is disposed on the coupling path between the second common port P2 and the fourth potential terminal D4.

[0072] In another embodiment of the present invention, referring to Figure 10, the high-density integrated filtering device 105 includes a first capacitive unit C1, a second capacitive unit C2, a third capacitive unit C3, a fourth capacitive unit C4, a fifth capacitive unit C5, a first inductive unit L1, a second inductive unit L2, a third inductive unit L3, a first common port P1, a second common port P2, a third common port P3, a first potential terminal D1, a second potential terminal D2, a fifth potential terminal D5, a first input / output port S1, a second input / output port S2, an eighth capacitive unit C8, a ninth capacitive unit C9, a tenth capacitive unit C10, and a fifth potential terminal D5. The first capacitive unit C1 is disposed on the coupling path between the first common port P1 and the first input / output port S1. The second capacitive unit C2 is disposed on the coupling path between the first common port P1 and the second common port P2. The third capacitive unit C3 is disposed on the coupling path between the first common port P1 and the first potential terminal D1. The first inductive unit L1 is coupled in parallel with the third capacitive unit C3. The third inductive unit L3 is disposed on the coupling path between the first common port P1 and the first potential terminal D1. The third inductive unit L3 is coupled with the third capacitive unit C3. The fourth capacitive unit C4 and the fifth capacitive unit C5 are disposed on the coupling path between the second common port P2 and the second potential terminal D2. The fourth capacitive unit C4 is coupled with the fifth capacitive unit C5. The second inductive unit L2 is coupled in parallel with the fifth capacitive unit C5. The second common port P2 is coupled with the second input / output port S2. The first capacitive unit C1 is coupled with the second capacitive unit C2 through the first common port P1. The second capacitive unit C2 is coupled with the third capacitive unit C3 through the first common port P1. The second capacitive unit C2 is coupled with the fourth capacitive unit C4 through the second common port P2. The fourth capacitive unit C4 is coupled with the second input / output port S2 through the second common port P2. The third common port P3 is disposed on the coupling path between the first input / output port S1 and the first capacitive unit C1. The ninth capacitive unit C9 is disposed on the coupling path between the third common port P3 and the third inductive unit L3. The eighth capacitive unit C8 is disposed on the coupling path between the third inductive unit L3 and the first common port P1. The tenth capacitive unit C10 is disposed on the coupling path between the third common port P3 and the fifth potential terminal D5. The tenth capacitive unit C10 is coupled with the ninth capacitive unit C9 and the first capacitive unit C1 through the third common port P3. The tenth capacitive unit C10 is at least partially formed inside or on the surface of the first substrate 10. The first to tenth capacitive units C1-C10 exhibit capacitive reactance within the operating frequency band of the high-density integrated filtering device 105.

[0073] In addition, a seventh inductive unit L7 can be added on the basis of the high-density integrated filtering device 105. The seventh inductive unit L7 is arranged on the coupling path between the third common port P3 and the fifth potential terminal D5. The seventh inductive unit L7 can be serially coupled or parallely coupled with the tenth capacitive unit C10. In this case, it is beneficial to further increase the out-of-band rejection degree of the filtering device.

[0074] Similarly, a sixth potential terminal D6 and an eleventh capacitive unit C11 can be added on the basis of the high-density integrated filtering device 105, as Figure 11 shown. The eleventh capacitive unit C11 is arranged on the coupling path between the first input / output port S1 and the sixth potential terminal D6. Further, an eighth inductive unit L8 can be arranged on the coupling path between the first input / output port S1 and the sixth potential terminal D6. The eighth inductive unit L8 is serially coupled or parallely coupled with the eleventh capacitive unit C11. The eleventh capacitive unit C11 exhibits capacitive reactance within the operating frequency band of the high-density integrated filtering device. In this case, it is beneficial to further increase the out-of-band rejection degree of the filtering device.

[0075] Figure 12 It is a schematic structural diagram of the capacitive unit included in the high-density integrated filtering device 104C. Refer to Figure 12, the first direction x, the second direction y, and the stacking direction z are perpendicular to each other pairwise. The first substrate 10 is formed by stacking dielectric layers along the stacking direction z, where the dielectric layer can be formed by any one or more of silicon, gallium arsenide, silicon carbide, gallium nitride, gallium oxide, diamond, indium phosphide, glass, sapphire, aluminum oxide, aluminum nitride, silicon nitride, silicon oxide, polyimide, or a combination thereof. The first capacitive unit C1 includes electrodes E1 and E3. Electrode E3 is formed above electrode E1. Electrodes E1 and E3 face each other and partially overlap in the projection on the plane perpendicular to the stacking direction z. Electrodes E1 and E3 are coupled through the dielectric layer therebetween to form the first capacitive unit C1. Electrode E1 is used to couple with the first input / output terminal S1. Electrode E2 is coupled to electrode E1 through a conductor. Electrode E2 is formed above electrode E4. Electrodes E2 and E4 face each other and partially overlap in the projection on the plane perpendicular to the stacking direction z. Electrodes E2 and E4 are coupled through the dielectric layer therebetween to form the ninth capacitive unit C9. Electrodes E3 and E4 face each other and partially overlap in the projection on the plane perpendicular to the stacking direction z. Electrodes E3 and E4 are coupled through the dielectric layer therebetween to form the eighth capacitive unit C8. Electrode E5 is formed above electrode E4. Electrodes E5 and E4 face each other and partially overlap in the projection on the plane perpendicular to the stacking direction z. Electrodes E5 and E4 are coupled through the dielectric layer therebetween to form the third capacitive unit C3. Electrode E3 extends along the first direction x, faces electrode E6, and partially overlaps in the projection on the plane perpendicular to the stacking direction z. Electrodes E3 and E6 are coupled through the dielectric layer therebetween to form the second capacitive unit C2. The fifth capacitive unit C5 includes electrodes E6 and E7. Electrode E7 is formed above electrode E6. Electrodes E6 and E7 face each other and partially overlap in the projection on the plane perpendicular to the stacking direction z. Electrodes E6 and E7 are coupled through the dielectric layer therebetween to form the fifth capacitive unit C5. The fourth capacitive unit C4 includes electrodes E7 and E8. Electrode E7 is formed above electrode E8. Electrodes E7 and E8 face each other and partially overlap in the projection on the plane perpendicular to the stacking direction z. Electrodes E7 and E8 are coupled through the dielectric layer therebetween to form the fourth capacitive unit C4. Electrode E8 is used to couple with the second input / output terminal S2. Electrodes E1 - E8 can be formed by one or more metallized materials such as Ag, Au, Cu, etc.

[0076] Figure 13 is Figure 12 a top view of the structure shown, referring to Figure 13 and combining Figure 12 , the first to ninth capacitive units C1 - C9 are arranged to be arranged along the first direction x. The projection Y0 on the plane perpendicular to the stacking direction z extends along the first direction x, and the overall shape is similar to a "one" shape. In this case, it is beneficial to reduce the size of the physical structure in the second direction y and improve the miniaturization performance.

[0077] Figure 14 The projection schematic diagram of a capacitive unit showing a variant embodiment is presented. The projections of the first to ninth capacitive units C1 - C9 on a plane perpendicular to the stacking direction z include a first projection part Y1, a second projection part Y2, and a third projection part Y3. The first projection part Y1 and the third projection part Y2 extend along the first direction x, and the second projection part Y3 extends along the second direction y. The first projection part Y1, the second projection part Y2, and the third projection part Y3 are connected end to end in sequence, and the whole is similar to a "Z" shape. In this case, the ninth capacitive unit C9 coupled to the first input / output terminal S1 and the fourth capacitive unit C4 coupled to the second input / output terminal S2 are diagonally distributed, and the first input / output terminal S1 and the second input / output terminal S2 can be spaced apart by a certain distance in the second direction y, which is beneficial to increasing the diversity of the layout.

[0078] Refer to Figure 15 As shown, the first to ninth capacitive units C1 - C9 can also be arranged such that their projections on a plane perpendicular to the stacking direction z include a fourth projection part Y4 and a fifth projection part Y5. The fourth projection part Y4 extends along the first direction x, and the fifth projection part Y5 extends from the middle of the fourth projection part Y4 along the second direction y, and the whole is similar to a "T" shape. In this case, the first capacitive unit C1 coupled to the first input / output terminal S1 and the fourth capacitive unit C4 coupled to the second input / output terminal S2 can be arranged on the same straight line in the first direction x.

[0079] Figure 16 It is the structural schematic diagram of the inductive unit included in the high - density integrated filtering device 104C. Refer to Figure 16, where the first direction x, the second direction y, and the stacking direction z are perpendicular to each other pairwise. The first inductive unit L1 includes metal traces G1, metal traces G2, and metal conduction posts therebetween. The metal traces G1 and G2 are formed on different dielectric layers of the first substrate 10 and are formed in a shape extending around a point in a spiral form. The metallized conduction posts extend along the stacking direction z in the first substrate 10, and the metal traces G1 and G2 are electrically interconnected through the conduction posts. The number of turns of the metal traces G1 and G2 does not exceed one turn. The second inductive unit L2 includes metal traces G3, metal traces G4, and metal conduction posts therebetween. The metal traces G3 and G4 are formed on different dielectric layers of the first substrate 10 and are formed in a shape extending around a point in a spiral form. The metallized conduction posts extend along the stacking direction z in the first substrate 10, and the metal traces G3 and G4 are electrically interconnected through the conduction posts. The number of turns of the metal traces G3 and G4 does not exceed one turn. The third inductive unit L3 includes metal traces G5, metal traces G6, and metal conduction posts therebetween. The metal traces G5 and G6 are formed on different dielectric layers of the first substrate 10 and are formed in a shape extending around a point in a spiral form. The metallized conduction posts extend along the stacking direction z in the first substrate 10, and the metal traces G5 and G6 are electrically interconnected through the conduction posts. The number of turns of the metal traces G5 and G6 does not exceed one turn. The sixth inductive unit L6 includes metal traces G7, metal traces G8, and metal conduction posts therebetween. The metal traces G7 and G8 are formed on different dielectric layers of the first substrate 10 and are formed in a shape extending around a point in a spiral form. The metallized conduction posts extend along the stacking direction z in the first substrate 10, and the metal traces G7 and G8 are electrically interconnected through the conduction posts. The number of turns of the metal traces G7 and G8 does not exceed one turn. The metal trace G2 is connected to the first potential terminal D1, and the metal trace G4 is connected to the second potential terminal D2. Taking Port1 and Port2 as ports formed on the first inductive unit L1 or the second inductive unit L2 or the third inductive unit L3 or the sixth inductive unit L6, the relationship between the voltage and current between Port1 and Port2 can be represented by the admittance matrix [Y]'. The imaginary part of Y11 in the admittance matrix [Y]' is less than zero, and the first inductive unit L1, the second inductive unit L2, the third inductive unit L3, and the sixth inductive unit L6 exhibit inductive reactance in the operating frequency band. In other embodiments or variations, the metal traces G1 - G8 can also be formed as extending from a point by a straight line, a broken line, an arc, a spiral, or a combination thereof. In other embodiments or variations, the metal traces G1 - G8 can also be formed on the surface of the first substrate 10.

[0080] The first inductive unit L1, the second inductive unit L2, the third inductive unit L3, and the sixth inductive unit L6 are arranged along the first direction x. The projections of the first inductive unit L1, the second inductive unit L2, and the third inductive unit L3 on the plane perpendicular to the first direction x at least partially overlap each other.

[0081] Figure 17 Is Figure 16 The top view of the structure shown, the metal traces G1 and G2 formed in different dielectric layers are substantially vertically aligned, and the inductive unit L1 encloses a closed figure in the projection on the plane perpendicular to the stacking direction z. The metal traces G3 and G4 are substantially vertically aligned, and the inductive unit L2 encloses a closed figure in the projection on the plane perpendicular to the stacking direction z. The metal traces G5 and G6 are substantially vertically aligned, and the inductive unit L3 encloses a closed figure in the projection on the plane perpendicular to the stacking direction z. The metal traces G7 and G8 are substantially vertically aligned, and the inductive unit L6 encloses a closed figure in the projection on the plane perpendicular to the stacking direction z. The first inductive unit L1, the second inductive unit L2, the third inductive unit L3, and the sixth inductive unit L6 are formed on the same side of the first to ninth capacitive units C1 - C9.

[0082] Figure 18 The schematic diagram of the overall structure of the high - density integrated filtering device 104C provided by the embodiment of the present invention is shown. Refer to Figure 18 , the third inductive unit L3 is coupled to the first potential terminal D1 through the metal trace G6. The fifth capacitive unit C5 is coupled to the second potential terminal D2 through the electrode E6. The second inductive unit L2 is coupled to the fourth potential terminal D4 through the metal trace G4. Figure 19 Is the insertion loss and return loss characteristic diagram of the high - density integrated filtering device 104C provided by the embodiment of the present invention. Four different transmission zeros are generated outside the passband of the high - density integrated filtering device 104C, with two transmission zeros on the left side of the passband and two transmission zeros on the right side of the passband, showing high out - of - band noise suppression characteristics and excellent frequency - selection performance.

[0083] On the basis of the above - mentioned embodiments, in another embodiment of the present invention, a second substrate 11 is further included. Refer to Figure 20, the high-density integrated filter device 104 includes a first substrate 10 and a second substrate 11. The second substrate 11 is formed by laminating dielectric layers in the stacking direction z, where the dielectric layer can be formed of any one or more of silicon, gallium arsenide, silicon carbide, gallium nitride, gallium oxide, diamond, indium phosphide, glass, sapphire, alumina, aluminum nitride, silicon nitride, silicon oxide, polyimide, or a combination thereof. The first substrate 10 and the second substrate 11 are sequentially arranged in the stacking direction z. The first substrate 10 is fixed to the second substrate 11 and uses a plurality of copper pillars as connectors, so that the first substrate 10 and the second substrate 11 are electromagnetically coupled. The first inductive unit L1 includes a metal trace G10, a metal trace G11, and a metal trace G12. Among them, the metal trace G11 is formed on the surface of the first substrate 10, the metal trace G10 is formed inside the first substrate 10, and the metal trace G12 is formed on the surface of the second substrate 11. The metal trace G12 and the metal trace G11 are conductively interconnected through a copper pillar. In addition, the first substrate 10 and the second substrate 11 can also be interconnected by metal bumps, solder balls, gold wires, or solder bumps.

[0084] The embodiment of the present utility model also provides an electronic device, including the high-density integrated filter device described in any of the above embodiments.

[0085] Figure 21 The structural schematic diagrams of various electronic devices that can be integrated with the high-density integrated filter device of any of the foregoing embodiments and their variants are shown. For example, a mobile phone 20, a laptop computer 21, and a fixed-position terminal 22 may include the high-density integrated filter device as described herein. Figure 21 The devices are only exemplary, and other electronic devices may also include any of the high-density integrated filter devices described herein, including but not limited to: music players, video players, entertainment units, global positioning system-enabled devices, navigation devices, communication devices, mobile devices, mobile phones, smart phones, personal digital assistants, fixed-position terminals, tablet computers, wearable devices, servers, routers, Internet of Things devices, laptop computers, or any combination thereof.

[0086] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered to be within the scope described in this specification.

[0087] The above-described embodiments merely represent several implementation manners of the present utility model. The description thereof is relatively specific and detailed, but it should not be construed as a limitation to the scope of the patented application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present utility model, several variations and improvements can still be made, and these all fall within the protection scope of the present utility model. Therefore, the protection scope of the patent of the present utility model shall be subject to the appended claims.

Claims

1. A high-density integrated filtering device, characterized in that: Include: A first substrate, a first capacitive unit, a second capacitive unit, a third capacitive unit, a fourth capacitive unit, a fifth capacitive unit, a first inductive unit, a second inductive unit, a third inductive unit, a first common port, a second common port, a first potential terminal, a second potential terminal, a first input-output port, and a second input-output port; The first capacitive unit is configured on a coupling path between the first common port and the first input-output port, the second capacitive unit is configured on a coupling path between the first common port and the second common port, the third capacitive unit is configured on a coupling path between the first common port and the first potential end, the first inductive unit is coupled with the third capacitive unit, the third inductive unit is configured on a coupling path between the first common port and the first potential end, the third inductive unit is coupled with the third capacitive unit, the fourth capacitive unit and the fifth capacitive unit are configured on a coupling path between the second common port and the second potential end, the fourth capacitive unit is coupled with the fifth capacitive unit, the second inductive unit is coupled with the fifth capacitive unit, and the second common port is coupled with the second input-output port; The first capacitive unit is coupled to the second capacitive unit through the first common port, the second capacitive unit is coupled to the third capacitive unit through the first common port, the second capacitive unit is coupled to the fourth capacitive unit through the second common port, and the fourth capacitive unit is coupled to the second input-output port through the second common port; the first substrate comprises one or more dielectric layers arranged along a stacking direction, the first to fifth capacitive units and / or the first to third inductive units are at least partially formed inside or on the surface of the first substrate, and the first to fifth capacitive units are formed by coupling of metallized electrodes.

2. The high-density integrated filtering device according to claim 1, characterized in that: The device further comprises a sixth capacitive unit, which is arranged on a coupling path between the second common port and the second input-output port, and is coupled to the fourth capacitive unit through the second common port.

3. The high-density integrated filtering device according to claim 1, characterized in that: It also includes a seventh capacitive unit, which is configured on a coupling path between the first capacitive unit and the first input-output port.

4. The high-density integrated filtering device according to claim 3, characterized in that: The device further comprises a fourth inductive unit, which is arranged on a coupling path between the first capacitive unit and the first input / output port, and is coupled in parallel with the seventh capacitive unit.

5. The high-density integrated filtering device according to claim 1, characterized in that: The device further comprises a fifth inductive unit, which is arranged on a coupling path between the second common port and the second potential end, and is coupled to the fifth capacitive unit.

6. The high-density integrated filtering device according to claim 1, characterized in that: It also includes an eighth capacitive unit, which is configured on a coupling path between the first common port and the first potential end, and is coupled to the third capacitive unit.

7. The high-density integrated filter device according to claim 6, characterized in that: The invention also includes a ninth capacitive unit and a third common port, wherein the third common port is configured on a coupling path between the first input / output port and the first capacitive unit, the ninth capacitive unit is configured on a coupling path between the third common port and the third inductive unit, the eighth capacitive unit is configured on a coupling path between the third inductive unit and the first common port, and the eighth capacitive unit is coupled to the third capacitive unit through the third inductive unit.

8. The high-density integrated filter device according to claim 7, characterized in that: The device further comprises a sixth inductive unit, wherein the sixth inductive unit is arranged on a coupling path between the first common port and the second common port, and the sixth inductive unit is coupled in parallel with the second capacitive unit.

9. The high-density integrated filter device according to claim 8, characterized in that: A third potential end is also included, and the first inductive unit is configured on a coupling path between the first common port and the third potential end.

10. The high-density integrated filter device according to claim 8, characterized in that: A fourth potential end is also included, and the second inductive unit is configured on a coupling path between the second common port and the fourth potential end.

11. The high-density integrated filter device according to claim 7, characterized in that: It also includes a tenth capacitive unit and a fifth potential end, wherein the tenth capacitive unit is configured on a coupling path between the third common port and the fifth potential end, the tenth capacitive unit is coupled with the ninth capacitive unit and the first capacitive unit through the third common port, and the tenth capacitive unit is at least partially formed inside or on the surface of the first substrate.

12. The high-density integrated filter device according to claim 11, characterized in that: The device further comprises a seventh inductive unit, wherein the seventh inductive unit is arranged on a coupling path between the third common port and the fifth potential end, and the seventh inductive unit is coupled to the tenth capacitive unit.

13. The high-density integrated filter device according to claim 11, characterized in that: It also includes an eleventh capacitive unit and a sixth potential end, wherein the eleventh capacitive unit is arranged on a coupling path between the first input / output port and the sixth potential end, and the eleventh capacitive unit is at least partially formed inside or on the surface of the first substrate.

14. The high-density integrated filter device according to claim 1, characterized in that: An eighth inductive unit is also included. The eighth inductive unit is configured on a coupling path between the first common port and the first input / output port and is coupled in parallel with the first capacitive unit.

15. The high-density integrated filter device according to any one of claims 1 to 14, characterized in that: The material of the first substrate is any one of silicon, gallium arsenide, silicon carbide, gallium nitride, gallium oxide, diamond, indium phosphide, glass, sapphire, aluminum oxide, aluminum nitride, silicon nitride, silicon oxide and polyimide.

16. The high-density integrated filter device according to claim 15, characterized in that: It also includes a second substrate formed by stacking one or more dielectric layers along the stacking direction, the first substrate and the second substrate are arranged in sequence in the stacking direction, the first substrate is fixed to the second substrate, the capacitive unit and / or the inductive unit are at least partially formed inside or on the surface of the second substrate, the first substrate and the second substrate are electromagnetically coupled via one or more connectors therebetween, and the connectors include at least one of metal bumps, copper pillars, tin balls, gold wires and solder bumps.

17. The high-density integrated filter device according to claim 15, characterized in that: The inductive unit is formed of a metal trace formed into a shape extending in the form of a zigzag line, an arc line, a spiral line, or a combination thereof.

18. The high-density integrated filter device according to claim 17, characterized in that: The inductive unit includes a plurality of the metal traces formed in different dielectric layers and a plurality of metallized via pillars interconnecting the metal traces, wherein the via pillars extend along the stacking direction.

19. The high-density integrated filter device according to claim 17, characterized in that: The projection of the metal trace on the plane perpendicular to the stacking direction is formed to be centered at one point and to be arranged around the point.

20. The high-density integrated filter device according to claim 17, characterized in that: The metal traces are formed on different dielectric layers and are substantially aligned along the stacking direction, and the projection of the inductive unit on a plane perpendicular to the stacking direction forms a closed figure.

21. The high-density integrated filter device according to claim 17, characterized in that: Each of the metal traces has no more than one turn.

22. The high-density integrated filter device according to claim 15, characterized in that: The first potential end and the second potential end are at the same potential.

23. The high-density integrated filtering device according to claim 15, characterized in that: The first to eighth capacitive units are configured to be arranged along a first direction.

24. The high-density integrated filtering device according to claim 23, characterized in that: Projections of the first to eighth capacitive units on a plane perpendicular to the stacking direction extend along the first direction.

25. The high-density integrated filtering device according to claim 23, characterized in that: The first to third inductive units are arranged on the same side of the first to eighth capacitive units.

26. The high-density integrated filter device according to claim 15, characterized in that: The first inductive unit, the second inductive unit and the third inductive unit are arranged along a first direction.

27. The high-density integrated filtering device according to claim 26, characterized in that: A projection of the first perceptual unit on a plane perpendicular to a first direction, a projection of the second perceptual unit on a plane perpendicular to the first direction, and a projection of the third perceptual unit on a plane perpendicular to the first direction at least partially overlap.

28. The high-density integrated filtering device according to claim 16, characterized in that: At least a portion of the structures of the first to third inductive units are simultaneously formed on the surface or inside of the first substrate and the second substrate.

29. An electronic device, characterized in that: A high-density integrated filtering device comprising any one of claims 1 to 28.

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