Silicon carbide field effect transistor
By designing the P-type well region and trench structure in the silicon carbide field effect transistor, and setting a second trench and an N-type injection part in the N-type heavily doped source region, the problem of large leakage current in the off-state of the silicon carbide MOS device is solved, and the effect of reducing static losses and improving device reliability is achieved.
Patent Information
- Application Number
- CN202421524639.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-28
- Publication Date
- 2025-06-10
- Estimated Expiration
- 2034-06-28
AI Technical Summary
The existing silicon carbide MOS devices have a large leakage current in the off state, resulting in an increase in power loss.
A silicon carbide field effect transistor is designed, including an N-type heavily doped silicon carbide substrate and an N-type epitaxial layer, having a P-type well region and a trench structure, and a second trench and an N-type injection portion are provided in the N-type heavily doped source region to reduce the leakage current between the source and drains.
It effectively suppresses the leakage current between the source and drains of the MOS device in the off state, reduces static losses, and improves the reliability of the device.
Smart Images
Figure CN222967304U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductor devices, in particular to a silicon carbide field effect transistor. Background Art
[0002] Silicon carbide (SiC) metal oxide semiconductor field effect transistor (MOSFET) is a unipolar voltage control device with majority carrier conduction, which has the advantages of fast switching speed, good high-frequency performance, and high reverse voltage. Therefore, it has been increasingly applied in high-performance switching power supplies, motor control, smart grids, electric vehicles, and rail transit fields. In existing silicon carbide MOS devices, the leakage current is relatively large in the off state, resulting in an increase in power loss. How to solve the above technical problems has become the technical direction for those skilled in the art to strive for. Summary of the Utility Model
[0003] The purpose of the utility model is to provide a silicon carbide field effect transistor, which is beneficial to suppressing the leakage current between the source and drain of the MOS device in the off state, thereby reducing the static loss of the MOS device and improving the reliability of the device.
[0004] To achieve the above purpose, the technical scheme adopted by the utility model is: a silicon carbide field effect transistor, which is characterized in that it includes: an N-type heavily doped silicon carbide substrate and an N-type epitaxial layer located on the N-type heavily doped silicon carbide substrate, and a lower metal electrode layer is provided on the surface of the N-type heavily doped silicon carbide substrate opposite to the N-type epitaxial layer;
[0005] An upper part of the N-type epitaxial layer has a P-type well region, a trench located in the P-type well region extends into the N-type epitaxial layer, an N-type heavily doped source region is provided in the upper part of the P-type well region and around the trench, and a gate column is provided in the trench;
[0006] A second trench is provided on a side of the N-type heavily doped source region opposite to the trench, an N-type heavily doped portion is filled in the second trench, an N-type implantation portion is provided between the second trench and the N-type heavily doped source region, the N-type heavily doped portion, the N-type implantation portion, and the N-type heavily doped source region are distributed at intervals, the lower end of the second trench is located in the N-type epitaxial layer, and the N-type implantation portion is located in the middle of the P-type well region;
[0007] An insulating dielectric layer is located above the trench and covers the gate column, and an upper metal electrode layer is located above the insulating dielectric layer and the N-type heavily doped source region and is in contact with the upper surfaces of the insulating dielectric layer and the N-type heavily doped source region respectively.
[0008] The further improved scheme in the above technical scheme is as follows:
[0009] 1. In the above solution, the depth of the N-type implantation region is greater than the depth of the N-type heavily doped source region.
[0010] 2. In the above solution, the height ratio of the P-type well region to the trench is 1:2 - 3.
[0011] 3. In the above solution, the bottom of the gate pillar in the trench is located below the P-type well region, and this gate pillar extends to the middle of the N-type epitaxial layer.
[0012] 4. In the above solution, the upper end of the N-type implantation region is in contact with the insulating dielectric layer.
[0013] Due to the application of the above technical solution, the present utility model has the following advantages compared with the prior art:
[0014] The silicon carbide field effect transistor of the present utility model has a second trench on the side of the N-type heavily doped source region opposite to the trench. An N-type heavily doped region is filled in this second trench. There is an N-type implantation region between the second trench and the N-type heavily doped source region. The N-type heavily doped region, the N-type implantation region, and the N-type heavily doped source region are spaced apart. The lower end of the second trench is located in the N-type epitaxial layer. The N-type implantation region is located in the middle of the P-type well region, which is beneficial to suppressing the leakage current between the source and drain of the MOS device in the off state, thereby reducing the static loss of the MOS device and improving the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Attached Figure 1 is a schematic structural diagram of the silicon carbide field effect transistor of the present utility model.
[0016] In the above drawings: 1. N-type heavily doped silicon carbide substrate; 2. N-type epitaxial layer; 3. Lower metal electrode layer; 4. P-type well region; 5. Trench; 6. Gate pillar; 7. Silicon dioxide layer; 8. N-type heavily doped source region; 9. Insulating dielectric layer; 10. Upper metal electrode layer; 11. N-type implantation region; 12. N-type heavily doped region; 13. Second trench. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0017] The present patent can be further clearly understood through the following specific embodiments given, but they do not limit the present patent.
[0018] Embodiment 1: A silicon carbide field effect transistor, comprising: an N-type heavily doped silicon carbide substrate 1 and an N-type epitaxial layer 2 located on the N-type heavily doped silicon carbide substrate 1. The surface of the N-type heavily doped silicon carbide substrate 1 opposite to the N-type epitaxial layer 2 has a lower metal electrode layer 3;
[0019] The upper part of the N-type epitaxial layer 2 has a P-type well region 4. A trench 5 located within the P-type well region 4 extends into the N-type epitaxial layer 2. The upper part of the P-type well region 4 and around the trench 5 has an N-type heavily doped source region 8. Inside the trench 5, there is a gate pillar 6;
[0020] On the side of the N-type heavily doped source region 8 opposite to the trench 5, there is a second trench 13. This second trench 13 is filled with an N-type heavily doped portion 12. Between the second trench 13 and the N-type heavily doped source region 8, there is an N-type implantation portion 11. The N-type heavily doped portion 12, the N-type implantation portion 11, and the N-type heavily doped source region 8 are spaced apart. The lower end of the second trench 13 is located within the N-type epitaxial layer 2, and the N-type implantation portion 11 is located in the middle of the P-type well region 4;
[0021] An insulating dielectric layer 9 is located above the trench 5 and covers the gate pillar 6. An upper metal electrode layer 10 is located above the insulating dielectric layer 9 and the N-type heavily doped source region 8 and is in contact with the upper surfaces of the insulating dielectric layer 9 and the N-type heavily doped source region 8 respectively.
[0022] The height ratio of the above-mentioned P-type well region 4 to the trench 5 is 1:2.2.
[0023] The bottom of the gate pillar 6 inside the above-mentioned trench 5 is located below the P-type well region 4, and this gate pillar 6 extends to the middle of the N-type epitaxial layer 2.
[0024] The upper end of the above-mentioned N-type implantation portion 11 is in contact with the insulating dielectric layer 9, and the upper end of the above-mentioned N-type heavily doped portion 12 is in contact with the insulating dielectric layer 9.
[0025] Embodiment 2: A silicon carbide field effect transistor, comprising: an N-type heavily doped silicon carbide substrate 1 and an N-type epitaxial layer 2 located on the N-type heavily doped silicon carbide substrate 1. The surface of the N-type heavily doped silicon carbide substrate 1 opposite to the N-type epitaxial layer 2 has a lower metal electrode layer 3;
[0026] The upper part of the N-type epitaxial layer 2 has a P-type well region 4. A trench 5 located within the P-type well region 4 extends into the N-type epitaxial layer 2. The upper part of the P-type well region 4 and around the trench 5 has an N-type heavily doped source region 8. Inside the trench 5, there is a gate pillar 6;
[0027] On the side of the N-type heavily doped source region 8 opposite to the trench 5, there is a second trench 13. This second trench 13 is filled with an N-type heavily doped portion 12. Between the second trench 13 and the N-type heavily doped source region 8, there is an N-type implantation portion 11. The N-type heavily doped portion 12, the N-type implantation portion 11, and the N-type heavily doped source region 8 are spaced apart. The lower end of the second trench 13 is located within the N-type epitaxial layer 2, and the N-type implantation portion 11 is located in the middle of the P-type well region 4;
[0028] An insulating dielectric layer 9 is located above the trench 5 and covers the gate post 6. An upper metal electrode layer 10 is located above the insulating dielectric layer 9 and the N-type heavily doped source region 8 and is in contact with the upper surfaces of the insulating dielectric layer 9 and the N-type heavily doped source region 8 respectively.
[0029] The depth of the above-mentioned N-type implantation part 11 is greater than the depth of the N-type heavily doped source region 8.
[0030] The height ratio of the above-mentioned P-type well region 4 to the trench 5 is 1:2.7.
[0031] The upper end of the above-mentioned N-type heavily doped part 12 is in contact with the insulating dielectric layer 9.
[0032] When the above-mentioned silicon carbide field effect transistor is adopted, a second trench is provided on the side of the N-type heavily doped source region opposite to the trench. An N-type heavily doped part is filled in this second trench. An N-type implantation part is provided between the second trench and the N-type heavily doped source region. The N-type heavily doped part, the N-type implantation part, and the N-type heavily doped source region are spaced apart. The lower end of the second trench is located in the N-type epitaxial layer. The N-type implantation part is located in the middle of the P-type well region, which is beneficial to suppressing the leakage current between the source and the drain of the MOS device in the off state, thereby reducing the static loss of the MOS device and improving the reliability of the device.
[0033] The above embodiments are only used to illustrate the technical concept and characteristics of the present invention. The purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly, and it cannot be used to limit the protection scope of the present invention. All equivalent changes or modifications made according to the spirit of the present invention should be covered within the protection scope of the present invention.
Claims
1. A silicon carbide field effect transistor, characterized in that: include: An N-type heavily doped silicon carbide substrate (1) and an N-type epitaxial layer (2) located on the N-type heavily doped silicon carbide substrate (1), wherein the surface of the N-type heavily doped silicon carbide substrate (1) opposite to the N-type epitaxial layer (2) has a lower metal electrode layer (3); The upper part of the N-type epitaxial layer (2) has a P-type well region (4), a trench (5) located in the P-type well region (4) extends into the N-type epitaxial layer (2), an N-type heavily doped source region (8) is located in the upper part of the P-type well region (4) and around the trench (5), and a gate column (6) is provided in the trench (5); A second trench (13) is provided on a side of the N-type heavily doped source region (8) opposite to the trench (5); an N-type heavily doped portion (12) is filled in the second trench (13); an N-type injection portion (11) is provided between the second trench (13) and the N-type heavily doped source region (8); the N-type heavily doped portion (12), the N-type injection portion (11), and the N-type heavily doped source region (8) are distributed at intervals; the lower end of the second trench (13) is located in the N-type epitaxial layer (2); and the N-type injection portion (11) is located in the middle of the P-type well region (4); An insulating dielectric layer (9) is located above the trench (5) and covers the gate column (6); an upper metal electrode layer (10) is located above the insulating dielectric layer (9) and the N-type heavily doped source region (8) and is in contact with the upper surfaces of the insulating dielectric layer (9) and the N-type heavily doped source region (8).
2. The silicon carbide field effect transistor according to claim 1, characterized in that: The depth of the N-type implantation portion (11) is greater than the depth of the N-type heavily doped source region (8).
3. The silicon carbide field effect transistor according to claim 1, characterized in that: The height ratio between the P-type well region (4) and the trench (5) is 1:2-3.
4. The silicon carbide field effect transistor according to claim 1, characterized in that: The bottom of the gate column (6) in the trench (5) is located below the P-type well region (4), and the gate column (6) extends to the middle of the N-type epitaxial layer (2).
5. The silicon carbide field effect transistor according to claim 1, characterized in that: The upper end of the N-type injection portion (11) is in contact with the insulating dielectric layer (9).