Semiconductor device structure

Abstract

Various embodiments of the present disclosure provide a semiconductor device structure. In one embodiment, a semiconductor device structure includes a first source / drain feature and a second source / drain feature, a plurality of semiconductor layers vertically stacked and disposed between the first source / drain feature and the second source / drain feature, a gate electrode layer surrounding a portion of each semiconductor layer, and an interface layer, the interface layer is disposed between the gate electrode layer and one of the semiconductor layers, where the topmost semiconductor layer of the semiconductor layers has a first length, and the interface layer has a second length greater than the first length.

Description

Technical Field

[0001] Embodiments of the present utility model relate to a semiconductor device structure, and more particularly to a semiconductor device having a nanostructured transistor. Background Art

[0002] The semiconductor integrated circuits (IC) industry has experienced exponential growth. Advancements in integrated circuit materials and design in modern technology have produced several generations of integrated circuits, each generation having smaller and more complex circuits compared to the previous generation. During the development of integrated circuits, the functional density (i.e., the number of interconnect devices per unit chip area) generally increases while the geometry size (i.e., the smallest element (or line) that can be produced using the process) decreases. This miniaturization process generally provides benefits by increasing production efficiency and reducing related costs. However, this miniaturization has brought new challenges. For example, transistors using nanostructured channels have been proposed to improve carrier mobility and drive current in the device. Inner spacers are typically provided between the metal gate and the source / drain (S / D) structure to protect the source / drain structure during subsequent gate replacement processes. Although the formation of the inner spacers generally meets its intended purpose, the source / drain structure may still be damaged due to the leakage of the etchant during the gate replacement process. Summary of the Utility Model

[0003] The purpose of the embodiments of the present utility model is to provide a semiconductor device structure to solve at least one of the above problems.

[0004] Embodiments of the present utility model provide a semiconductor device structure, including a first source / drain component and a second source / drain component; a plurality of semiconductor layers vertically stacked and disposed between the first source / drain component and the second source / drain component; a gate electrode layer surrounding a part of each semiconductor layer; and an interface layer disposed between one of the gate electrode layer and the semiconductor layer, wherein the topmost semiconductor layer of the semiconductor layers has a first length, and the interface layer has a second length greater than the first length.

[0005] According to one embodiment of the present utility model, it further includes: a blocking structure in contact with a sidewall of each semiconductor layer.

[0006] According to one embodiment of the present utility model, it further includes: a gate spacer in contact with the interface layer and the blocking structure.

[0007] According to one embodiment of the present invention, a part of the blocking structure contacts the first source / drain component or the second source / drain component.

[0008] According to one embodiment of the present invention, the blocking structure extends above an interface defined by the interface layer and the gate spacer.

[0009] An embodiment of the present invention provides a semiconductor device structure, including a plurality of semiconductor layers stacked vertically and parallelly; a gate electrode layer completely surrounding a part of each semiconductor layer; an interface layer disposed between the gate electrode layer and the topmost semiconductor layer of the semiconductor layers; a gate spacer adjacent to the gate electrode layer and in contact with the interface layer; and a blocking structure in contact with the sidewalls of each semiconductor layer, wherein the blocking structure covers the interface defined by the interface layer and the gate spacer.

[0010] According to one embodiment of the present invention, the interface layer in contact with the topmost semiconductor layer has a first length, and the topmost semiconductor layer of the plurality of semiconductor layers has a second length less than the first length.

[0011] According to one embodiment of the present invention, the blocking structure has a diamond shape in a cross-sectional view.

[0012] According to one embodiment of the present invention, the blocking structure is a faceted structure having a plane from the {111} plane family, {100} plane family, {311} plane family, or {911} plane family.

[0013] According to one embodiment of the present invention, the top surface of the gate electrode layer is lower than the top surface of the gate spacer. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The embodiments of the present invention can be best understood from the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to the standard practice in the industry, various features are not drawn to scale and are only for illustration purposes. In fact, the sizes of various elements can be arbitrarily enlarged or reduced to clearly show the features of the embodiments of the present invention.

[0015] Figure 1 、 Figure 2 、 Figure 3 、 Figure 4 AND Figure 5 are perspective schematic views showing various stages of manufacturing a semiconductor device structure according to some embodiments.

[0016] Figure 6A 、 Figure 7A 、 Figure 8A 、 Figure 9A 、Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A and Figure 19A are cross-sectional side views taken along section line A-A showing various stages of fabricating a semiconductor device structure Figure 5 according to some embodiments.

[0017] Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B and Figure 19B are cross-sectional side views taken along section line B-B showing various stages of fabricating a semiconductor device structure Figure 5 according to some embodiments.

[0018] Figure 6C , Figure 14C , Figure 15C , Figure 16C , Figure 17C , Figure 18C and Figure 19C are cross-sectional side views taken along section line C-C showing various stages of fabricating a semiconductor device structure Figure 5 according to some embodiments.

[0019] Figure 6D , Figure 14D , Figure 15D , Figure 16D , Figure 17D , Figure 18D and Figure 19D are cross-sectional side views taken along section line D-D showing various stages of fabricating a semiconductor device structure Figure 5 according to some embodiments.

[0020] Figure 7A-1 is an enlarged view showing part A of a semiconductor device structure Figure 7A according to some embodiments.

[0021] Figure 12A-1 is an enlarged view showing part B of a semiconductor device structure Figure 12A according to some embodiments.

[0022] Figure 14A-1 is a schematic enlarged view of part C of a semiconductor device structure according to some embodiments, showing Figure 14A

[0023] Figure 14B-1 is a schematic enlarged view of part D of a semiconductor device structure according to some embodiments, showing Figure 14B Figure 14E is a schematic top view of a part of a semiconductor device structure taken along section E-E according to some embodiments, showing Figure 14A

[0024] Figure 14F is a schematic top view of a part of a semiconductor device structure taken along section F-F according to some embodiments, showing Figure 14A

[0025] Figure 18A-1 is a schematic enlarged view of part E of a semiconductor device structure according to some embodiments, showing Figure 18A

[0026] Figure 18A-2 is a schematic enlarged view of part F of a semiconductor device structure according to some embodiments, showing Figure 18A-1

[0027] Figure 18E is a schematic top view of a part of a semiconductor device structure taken along section E-E according to some embodiments, showing Figure 18A

[0028] Figure 18F is a schematic top view of a part of a semiconductor device structure taken along section F-F according to some embodiments, showing Figure 18A

[0029] The reference numerals are as follows:

[0030] 100: Semiconductor device structure

[0031] 101: Substrate

[0032] 103: First device region

[0033] 104: Semiconductor layer stack

[0034] 105: Second device region

[0035] 106: First semiconductor layer

[0036] 106s: Sidewall

[0037] 107: N-type well

[0038] 108: Second semiconductor layer

[0039] 108s: Sidewall

[0040] 109: P-type well

[0041] 110: Mask structure

[0042] 110a: Cushion layer

[0043] 110b: Hard mask

[0044] 112: Fin structure

[0045] 114: Trench

[0046] 116: Well portion

[0047] 117: Coating layer

[0048] 118: Insulating material

[0049] 119: Liner

[0050] 120: Insulating region

[0051] 121: Dielectric material

[0052] 123: Trench

[0053] 125: Dielectric material

[0054] 127: Dielectric component

[0055] 130: Sacrificial gate structure

[0056] 131: Concave hole

[0057] 132: Sacrificial gate dielectric layer

[0058] 133: Imaginary line

[0059] 134: Sacrificial gate electrode layer

[0060] 135: Interface

[0061] 136: Mask layer

[0062] 137: Hard mask layer

[0063] 138: Gate spacer

[0064] 138s: Sidewall

[0065] 139: Photoresist layer

[0066] 141: Barrier structure

[0067] 141a: Facet

[0068] 141b: Facet

[0069] 144: Inner spacer

[0070] 144-1: First part

[0071] 144-2: Second part

[0072] 144a: Dielectric layer

[0073] 146: S / D component

[0074] 146a: First epitaxial layer

[0075] 146b: Second epitaxial layer

[0076] 147: S / D component

[0077] 147a: First epitaxial layer

[0078] 147b: Second epitaxial layer

[0079] 147c: Third epitaxial layer

[0080] 148: Epitaxial layer

[0081] 162: Contact etch stop layer

[0082] 164: Interlayer dielectric layer

[0083] 166: Opening

[0084] 167: Interface

[0085] 173: Self-aligned contact layer

[0086] 178: Interface layer

[0087] 180: Gate interface layer

[0088] 182a: Gate electrode layer

[0089] 182b: Gate electrode layer

[0090] 184: Silicide layer

[0091] 186: Source / drain contact

[0092] 190: Replacement gate structure

[0093] A-A: Cross-section

[0094] B-B: Cross-section

[0095] C-C: Cross-section

[0096] D-D: Cross-section

[0097] D1: Distance

[0098] D2: Distance

[0099] D3: Distance

[0100] D4: Distance

[0101] D5: Distance

[0102] D6: Distance

[0103] D7: Thickness

[0104] D8: Length

[0105] D9: Length

[0106] E - E: Section

[0107] F - F: Section

[0108] T1: Thickness

[0109] T2: Thickness

[0110] T3: Thickness

[0111] T4: Thickness

[0112] W1: Width

[0113] W2: Width

[0114] X: Direction

[0115] Y: Direction

[0116] Z: Direction Detailed implementation manners

[0117] The following discloses and provides many embodiments or examples for implementing different elements of the provided subject matter. Specific examples of each element and its configuration are described below to simplify the description of the embodiments of the present utility model. Of course, these are only examples and are not intended to limit the embodiments of the present utility model. For example, if it is mentioned in the description that the first element is formed on the second element, it may include embodiments where the first and second elements are in direct contact, and may also include embodiments where additional elements are formed between the first and second elements such that they are not in direct contact. In addition, the embodiments of the present utility model may repeat reference to numerical values and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity, and is not intended to represent the relationship between different embodiments and / or configurations discussed.

[0118] Furthermore, relative spatial terms may be used, such as "under", "below", "lower", "above", "upper", etc., to facilitate the description of the relationship between one or more components or features and another component or feature in the drawings. Relative spatial terms are intended to encompass different orientations of the device in use or operation, as well as the orientations described in the drawings. When the device is turned to a different orientation (rotated 90 degrees or otherwise), the relative spatial adjectives used therein will be interpreted according to the turned orientation.

[0119] Although the embodiments of the present disclosure discuss nanoscale channel field effect transistors (FETs), some aspects of the embodiments of the present disclosure can be used in other processes and / or other devices, such as planar FETs, fin field effect transistors (Fin-FETs), Horizontal Gate All around (HGAA) FETs, Vertical Gate All Around (VGAA) FETs, and other suitable devices. Those skilled in the art of the present utility model will readily understand that other modifications can be made within the scope contemplated by the present disclosure. In the case of adopting a Gate All Around (GAA) transistor structure, the GAA transistor structure can be patterned by any suitable method. For example, one or more photolithography processes (including double patterning or multiple patterning processes) can be used to pattern the structure. Generally, double patterning or multiple patterning processes combine photolithography processes with self-alignment processes to create patterns with, for example, a smaller pitch than that obtained using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. A spacer is formed adjacent to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacer or mandrel can then be used as a mask to pattern the GAA structure.

[0120] Figures 1 to 19D An exemplary process for manufacturing a semiconductor device structure 100 is shown in accordance with an embodiment of the present disclosure. It should be understood that additional operations may be provided before, during, and after the process of the illustrated embodiment, and some of the operations described below may be replaced or eliminated for additional embodiments of the method. The order of the operations / processes is not limited and may be interchanged. Figures 1 to 19D The order of operations / processes is not limited and may be interchanged.

[0121] Figures 1 to 5 A perspective schematic diagram showing the various stages of manufacturing a semiconductor device structure 100 is shown in accordance with some embodiments. Refer to Figure 1, the semiconductor device structure 100 is shown to include a substrate 101, and dopants have been implanted into the substrate 101 to form wells. The substrate 101 can be a semiconductor substrate. The substrate 101 can include crystalline semiconductor materials such as, but not limited to, silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), aluminum indium arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimonide phosphide (GaSbP), gallium arsenide antimonide (GaAsSb), indium phosphide (InP), or a combination of the above. In one embodiment, the substrate 101 is formed of silicon. The substrate 101 can be doped or undoped. The substrate 101 can be a bulk semiconductor substrate such as a bulk silicon substrate as a wafer, a silicon-on-insulator (SOI) substrate, a multi-layer or gradient substrate, etc.

[0122] The substrate 101 includes a first device region 103 for forming N-type devices (such as n-type metal-oxide-semiconductor (NMOS) devices (e.g., N-type fully-depleted surround gate transistors)), and a second device region 105 for forming P-type devices (such as p-type metal-oxide-semiconductor (PMOS) devices (e.g., P-type fully-depleted surround gate transistors)). Wells can be formed within the substrate 101 with N-type dopants and P-type dopants to separate the first device region 103 and the second device region 105. To form the desired wells, depending on the devices to be formed, N-type dopants and P-type dopants are implanted into the substrate 101. For example, N-type dopants such as phosphorus or arsenic can be implanted to form N-type wells, and P-type dopants such as boron can be implanted to form P-type wells. The N-type wells and P-type wells can be formed using one or more implantation techniques such as diffusion implantation, ion implantation (e.g., plasma doping, beam line implantation doping), selective implantation, deep well implantation and similar techniques, or a combination of the above. Masking techniques can also be utilized to cover some regions of the substrate 101 (e.g., the second device region 105), while exposing other regions (e.g., the first device region 103) during the first well implantation (e.g., N-type well) process. Once the first well implantation process is completed, the mask is removed to expose the previously covered regions (e.g., the second device region 105), and another mask can be placed over the previously exposed regions (e.g., the first device region 103) during the second well implantation (e.g., P-type well) process. In Figure 1In one embodiment shown, substrate 101 includes an N-type well 107 and a P-type well 109. Although the first device region 103 is shown adjacent to the second device region 105, it should be understood that the first device region 103 may be disposed at different regions of the substrate 101 along direction X or direction Y to be away from the second device region 105, and the first device region 103 and the second device region 105 belong to a continuous substrate (e.g., substrate 101).

[0123] Figure 1 Also shown is a semiconductor layer stack 104 formed over the substrate 101 at the first device region 103 and the second device region 105. The semiconductor layer stack 104 includes semiconductor layers formed of different materials to facilitate the formation of nanostructure channels in multi-gate devices, such as nanostructure FETs. In some embodiments, the semiconductor layer stack 104 includes a first semiconductor layer 106 and a second semiconductor layer 108. In some embodiments, the semiconductor layer stack 104 includes alternating first semiconductor layers 106 and second semiconductor layers 108, and the first semiconductor layer 106 and the second semiconductor layer 108 are disposed parallel to each other. The first semiconductor layer 106 and the second semiconductor layer 108 are formed of semiconductor materials having different etch selectivities and / or oxidation rates. For example, the first semiconductor layer 106 may be formed of Si, while the second semiconductor layer 108 may be formed of SiGe. In some examples, the first semiconductor layer 106 may be formed of SiGe, while the second semiconductor layer 108 may be formed of Si. In some embodiments, the first semiconductor layer 106 may be formed of SiGe having a first Ge concentration range, while the second semiconductor layer 108 may be formed of SiGe having a second Ge concentration range that is lower than or greater than the first Ge concentration range. Alternatively, in some embodiments, either the first semiconductor layer 106 or the second semiconductor layer 108 may be or include other materials, such as Ge, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or any combination of the foregoing.

[0124] The thicknesses of the first semiconductor layer 106 and the second semiconductor layer 108 can be varied according to application and / or device performance considerations. In some embodiments, each of the first semiconductor layer 106 and the second semiconductor layer 108 has a thickness T1, T2 in the range of about 2 nm to about 30 nm, respectively. In other embodiments, each of the first semiconductor layer 106 and the second semiconductor layer 108 has a thickness T1, T2 in the range of about 10 nm to about 20 nm. The thickness T1 of the first semiconductor layer 106 can be equal to, less than, or greater than the thickness T2 of the second semiconductor layer 108. The second semiconductor layer 108 can ultimately be removed and used to define the vertical distance between adjacent channels of the semiconductor device structure 100.

[0125] The first semiconductor layer 106 or a portion thereof can form a nanostructured channel of the semiconductor device structure 100 in a subsequent manufacturing stage. The term "nanostructured" is used in this disclosure to refer to any material portion having nanoscale, or even microscale, dimensions and having an elongated shape, regardless of the cross-sectional shape of the portion. Thus, this term refers to elongated material portions having circular and substantially circular cross-sections, as well as strip or rod-shaped material portions including, for example, cylindrical or substantially rectangular cross-sections. The nanostructured channels of the semiconductor device structure 100 can be surrounded by gate electrodes. The semiconductor device structure 100 can include nanostructured transistors. The nanostructured transistors can be referred to as nanowire transistors, nanosheet transistors, gate-all-around (GAA) transistors, multi-bridge channel (MBC) transistors, or any transistor having a gate electrode surrounding the channel. The use of the first semiconductor layer 106 to define the channels of the semiconductor device structure 100 is discussed further below.

[0126] The first semiconductor layer 106 and the second semiconductor layer 108 are formed by any suitable deposition process, such as epitaxy. For example, the epitaxial growth of the layers of the semiconductor layer stack 104 can be carried out by vapor-phase epitaxy (VPE), molecular beam epitaxy (MBE) process, metalorganic chemical vapor deposition (MOCVD) process, and / or other suitable growth processes, such as chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer CVD (ALCVD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), combinations of the above, or similar growth processes. Although Figure 1 shows three first semiconductor layers 106 and three second semiconductor layers 108 in an alternating configuration, any number of first semiconductor layers 106 and second semiconductor layers 108 can be formed in the semiconductor layer stack 104, depending on the predetermined number of nanostructured channels of each FET. For example, the number of first semiconductor layers 106 (i.e., the number of channels) can range from 2 to 8.

[0127] In Figure 2In [description], the fin structure 112 is formed by the semiconductor layer stack 104, and an insulating material 118 is formed in the trench 114 between the fin structures 112. Each fin structure 112 includes a part of the first semiconductor layer 106, a part of the second semiconductor layer 108, a part of the N-type well 107, a part of the P-type well 109, and a part of the mask structure 110. Before forming the fin structure 112, the mask structure 110 is formed above the semiconductor layer stack 104. The mask structure 110 may include a pad layer 110a and a hard mask 110b. The pad layer 110a may be an oxygen-containing layer. The hard mask 110b may be a nitrogen-containing layer. The fin structure 112 can be fabricated using suitable processes including photolithography and etching processes. In some embodiments, the photolithography process may include forming a photoresist layer (not shown) above the mask structure 110, exposing a pattern to the photoresist layer, performing a post-exposure bake process, and developing the photoresist layer to form a patterned photoresist layer. Then, the patterned photoresist layer can be used to protect the regions of the substrate 101 and the film layers formed thereon, while the etching process forms trenches 114 in the unprotected regions that pass through the mask structure 110, the semiconductor layer stack 104, and into the N-type well 107 and P-type well 109 of the substrate 101, thereby forming the extended fin structure 112. The width W1 of the fin structure 112 at the first device region 103 in the direction Y may range from about 3 nm to about 44 nm. The width W2 of the fin structure 112 at the second device region 105 in the direction Y may be equal to, less than, or greater than the width W1. Dry etching (e.g., reactive ion etching; RIE), wet etching, and / or a combination of the above can be used to etch the trenches 114. Although Figure 2 two fin structures 112 are shown, the number of fin structures is not limited to two.

[0128] After forming the fin structure 112, an insulating material 118 is formed in the trench 114 between the fin structures 112. The insulating material 118 fills the trench 114 between adjacent fin structures 112 until the fin structures 112 are embedded in the insulating material 118. Then, a planarization operation such as a chemical mechanical polishing (CMP) process and / or an etch-back process is performed to expose the top of the fin structures 112. The insulating material 118 can be formed of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), a low dielectric constant dielectric material, or any suitable dielectric material. The insulating material 118 can be formed by any suitable method, such as LPCVD, plasma enhanced CVD (PECVD), or flowable CVD (FCVD). Then, the insulating material 118 is etched to form the isolation region 120. The recessed portion of the insulating material 118 exposes multiple portions of the fin structures 112. The isolation region 120 can be formed using a suitable process, such as a dry etching process, a wet etching process, or a combination of the above. The top surface of the insulating material 118 can be flush with or lower than the surface where the second semiconductor layer 108 contacts the N-type well 107 and the P-type well 109.

[0129] In Figure 3 it, a cladding layer 117 is formed over the exposed portions of the fin structures 112. The cladding layer 117 contacts the semiconductor layer stack 104. In some embodiments, the cladding layer 117 and the second semiconductor layer 108 comprise the same material. For example, the cladding layer 117 and the second semiconductor layer 108 can be or comprise SiGe. Subsequently, the cladding layer 117 and the second semiconductor layer 108 are removed to create space for the subsequently formed gate electrode layer. A liner 119 is formed on the top surfaces of the cladding layer 117 and the insulating material 118. The liner 119 can comprise a material having a dielectric constant value (k value) lower than 7, such as SiO 2 , SiN, SiCN, SiOC, or SiOCN. The liner 119 can be formed by a conformal process such as an ALD process. Then, a dielectric material 121 is formed in the trench 114 ( Figure 2) within and on liner 119. The dielectric material 121 can be an oxygen-containing material formed by FCVD, such as an oxide. The oxygen-containing material can have a k value less than about 7, for example, less than about 3. A planarization process, such as a CMP process, can be performed to remove multiple portions of liner 119 and dielectric material 121 formed above fin structure 112. After the planarization process, multiple portions of cladding layer 117 disposed on hard mask 110b are exposed.

[0130] Next, liner 119 and dielectric material 121 are etched to the level of the topmost first semiconductor layer 106. For example, in some embodiments, after the etching process, the top surfaces of liner 119 and dielectric material 121 can be flush with the top surface of the topmost first semiconductor layer 106. The etching process can be a selective etching process that substantially does not affect the semiconductor material of cladding layer 117. Due to the execution of the etching process, trenches 123 are formed between fin structures 112 ( Figure 2 ).

[0131] In Figure 4 , dielectric material 125 is formed within trenches 123 ( Figure 3 ) and on dielectric material 121 and liner 119. Dielectric material 125 can include SiO 2 , SiN, SiC, SiCN, SiON, SiOCN, AlO, AlN, AlON, ZrO, ZrN, ZrAlO, HfO, or other suitable dielectric materials. In some embodiments, dielectric material 125 includes a high-k dielectric material (e.g., a material with a k value greater than 7). Dielectric material 125 can be formed by any suitable process, such as CVD, PECVD, FCVD, or ALD processes. A planarization process, such as a CMP process, is performed until hard mask 110b of mask structure 110 is exposed. The planarization process removes multiple portions of dielectric material 125 disposed above mask structure 110 and cladding layer 117. Liner 119, dielectric material 121, and dielectric material 125 can be collectively referred to as dielectric component 127 or hybrid fins. Dielectric component 127 is used to separate subsequently formed source / drain (S / D) epitaxial components and adjacent gate electrode layers.

[0132] In Figure 5Therein, an etched cladding layer 117 is formed and the mask structure 110 is removed. The recessing of the cladding layer 117 can be performed by any suitable process, such as dry etching, wet etching, or a combination of the above. The etching process can be controlled such that the remaining cladding layer 117 is substantially at the same level as the top surface of the topmost first semiconductor layer 106 in the semiconductor layer stack 104. The etching process can be a selective etching process that substantially does not affect the dielectric material 125. The removal of the mask structure 110 can be performed by any suitable process, such as dry etching, wet etching, or a combination of the above.

[0133] After that, one or more sacrificial gate structures 130 are formed over the semiconductor device structure 100. The sacrificial gate structures 130 are formed over a portion of the fin structures 112. Each sacrificial gate structure 130 can include a sacrificial gate dielectric layer 132, a sacrificial gate electrode layer 134, and a mask layer 136. The sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136 can be formed by sequentially depositing blanket layers of the sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136, followed by patterning and etching processes. For example, the patterning process includes a photolithography process (e.g., optical lithography or electron beam lithography), which can further include photoresist coating (e.g., spin-on coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques, and / or a combination of the above. In some embodiments, the etching process can include dry etching (e.g., RIE), wet etching, other etching methods, and / or a combination of the above.

[0134] By patterning the sacrificial gate structures 130, the semiconductor layer stack 104 of the fin structures 112 is partially exposed on both sides of the sacrificial gate structures 130. The portions of the fin structures 112 covered by the sacrificial gate electrode layers 134 of the sacrificial gate structures 130 are used as the channel regions of the semiconductor device structure 100. The fin structures 112 partially exposed on both sides of the sacrificial gate structures 130 define the source / drain (S / D) regions of the semiconductor device structure 100. Although Figure 5 two sacrificial gate structures 130 are shown, in some embodiments, three or more sacrificial gate structures 130 can be arranged along the direction X.

[0135] Figure 5Also shown is the formation of gate spacers 138 on the sidewalls of the sacrificial gate structure 130. The gate spacers 138 can be formed by first depositing a conformal layer, which is then etch-back to form the gate spacers 138 on the sidewalls. For example, a layer of spacer material can be conformally deposited on the exposed surfaces of the semiconductor device structure 100 by an ALD process or any suitable conformal deposition technique. Subsequently, anisotropic etching is performed on the spacer material layer using, for example, RIE. During the anisotropic etching process, most of the spacer material layer is removed from the horizontal surfaces (such as the top of the fin structure 112, the cladding layer 117, and the dielectric material 125), while the gate spacers 138 are left on the vertical surfaces (such as the sidewalls of the sacrificial gate structure 130). The gate spacers 138 can be formed of a dielectric material, such as SiO 2 、Si 3 N 4 、SiC, SiON, SiCN, SiOCN, carbon-doped oxides, nitrogen-doped oxides, porous oxides, gaps, and / or combinations thereof.

[0136] It should be understood that the cladding layer 117 and the dielectric component 127 (i.e., the hybrid fin) are optional and may not be necessary. In some embodiments where the cladding layer 117 and the dielectric component 127 are absent, portions of the sacrificial gate structure 130 and the gate spacers 138 are formed on the fin structure 112 and the insulating material 118, and gaps are formed between the exposed portions of the fin structure 112.

[0137] Figures 6A to 19A is a cross-sectional side view schematic diagram taken along section A-A of various stages of manufacturing a semiconductor device structure according to some embodiments. Figure 5 is a cross-sectional side view schematic diagram taken along section B-B of various stages of manufacturing a semiconductor device structure according to some embodiments. Figures 6B to 19B is a cross-sectional side view schematic diagram taken along section C-C of various stages of manufacturing a semiconductor device structure according to some embodiments. Figure 5 is a cross-sectional side view schematic diagram taken along section D-D of various stages of manufacturing a semiconductor device structure according to some embodiments. Sections A-A and B-B are located on the fin structure 112 ( Figure 6C and Figures 14C to 19C is a cross-sectional side view schematic diagram taken along section C-C of various stages of manufacturing a semiconductor device structure according to some embodiments. Figure 5 is a cross-sectional side view schematic diagram taken along section D-D of various stages of manufacturing a semiconductor device structure according to some embodiments. Sections A-A and B-B are located on the fin structure 112 ( Figure 6D and Figures 14D to 19D is a cross-sectional side view schematic diagram taken along section D-D of various stages of manufacturing a semiconductor device structure according to some embodiments. Sections A-A and B-B are located on the fin structure 112 ( Figure 5 ). Sections A-A and B-B are located on the fin structure 112 ( Figure 4)In the plane along the direction X. The cross-section C-C is located in a plane perpendicular to the cross-section A-A and is located in the sacrificial gate structure 130. The cross-section D-D is located in a plane perpendicular to the cross-section A-A and is located in the S / D component 146 along the direction Y( Figure 14A and Figure 14B ).

[0138] In Figures 6A to 6D , the exposed portions of the fin structure 112, the exposed portions of the cladding layer 117, and the exposed portions of the dielectric material 125 that are not covered by the sacrificial gate structure 130 and the gate spacer 138 at the first device region 103 and the second device region 105 are selectively etched by one or more suitable etching processes, such as dry etching, wet etching, or a combination of the above. Multiple portions of the fin structure 112, the exposed portions of the cladding layer 117, the exposed portions of the dielectric material 125, and a portion of the N-type well 107 and the P-type well 109 are removed to expose the sidewalls of the fin structure 112( Figure 4 ). In some embodiments, the exposed portions of the fin structure 112 are etched to the bottom surface where the second semiconductor layer 108 contacts the N-type well 107 and the P-type well 109 of the substrate 101, respectively, or to a level slightly below the bottom surface. Thus, the sidewalls of the bottommost second semiconductor layer 108 of each fin structure 112 are completely exposed. In some embodiments, the removal process includes two etching processes, where the first etching process is performed to remove the exposed portions of the semiconductor layer stack 104, the cladding layer 117, and the dielectric material 125 of the fin structure 112 and to expose multiple portions of the N-type well 107 and the P-type well 109, and the second etching process is performed to remove the exposed portions of the N-type well 107 and the P-type well 109. Removing portions of the N-type well 107 and the P-type well 109 results in the formation of grooves 157 and 159 in the top portions of the bulk silicon regions (e.g., the N-type well 107 and the P-type well 109), while the top of the bulk silicon region under the sacrificial gate structure 130 is covered and not removed. As a result of removing portions of the N-type well 107 and the P-type well 109, the top surfaces of the exposed N-type well 107 and the P-type well 109 are at levels that are lower by a distance D1 and a distance D2, respectively, than the interface defined between the bottommost second semiconductor layer 108 and the N-type well 107 and the P-type well 109. In some embodiments, the distances D1 and D2 range from about 5 nm to about 30 nm.

[0139] In some embodiments, the removal process is performed such that the well (e.g., the N-type well) exposed in the second device region 105 is etched deeper than the exposed well (e.g., the P-type well). Since the channel mobility of PMOS devices (e.g., P-type fully wrapped gates) is closely related to the size of the source / drain (S / D) components, removing a larger amount of the exposed well may result in a subsequent S / D component 147( Figure 14B) is formed to have a larger volume, and thus has a higher strain effect on the ion improvement of the PMOS device. In this case, the distance D2 can be larger than the distance D1 by, for example, about 3 nm to about 15 nm.

[0140] In Figure 7A and Figure 7B , the edge portions of each second semiconductor layer 108 of the semiconductor layer stack 104 are horizontally removed along the direction X. During the removal of the second semiconductor layer 108, multiple portions of the first semiconductor layer 106 are also horizontally removed. Alternatively, a first etching process can be performed to remove a portion of both the first semiconductor layer 106 and the second semiconductor layer 108, and a second etching process can be performed to further remove a portion of the first semiconductor layer 106, so that the interface 135 defined by the gate spacer 138 and the sacrificial gate electrode layer 134 (or the sacrificial gate dielectric layer 132) is exposed, as Figure 7A-1 shown. In some embodiments, a single extended etching process can be performed to remove multiple portions of both the first semiconductor layer 106 and the second semiconductor layer 108 until the interface 135 is exposed.

[0141] Figure 7A-1 is, according to some embodiments, an enlarged schematic view of part A of the semiconductor device structure shown in Figure 7A . It can be seen that the second semiconductor layer 108 can be removed a lateral distance D3, and the lateral distance D3 is measured from the edge of the second semiconductor layer 108 (e.g., the sidewall 108s) to an imaginary line 133 extending downward from the sidewall 138s of the gate spacer 138, while the first semiconductor layer 106 can be removed a lateral distance D4, and the lateral distance D4 is measured from the edge of the first semiconductor layer 106 (e.g., the sidewall 106s) to the imaginary line 133 extending downward from the sidewall of the gate spacer 138. In various embodiments, the distance D4 is greater than the distance D3. In other words, the etch amount of the second semiconductor layer 108 is greater than the etch amount of the first semiconductor layer 106. The removal of the edge portions of the second semiconductor layer 108 forms cavities 131.

[0142] Multiple portions of the first semiconductor layer 106 and the second semiconductor layer 108 can be removed by a selective wet etching process or other suitable removal processes. In the case where the second semiconductor layer 108 is formed of SiGe and the first semiconductor layer 106 is formed of silicon, the second semiconductor layer 108 can be selectively etched using an etchant such as, but not limited to, an HF:HNO 3 solution, ammonium hydroxide (NH 4 OH), and H 2 O 2Solution, tetramethylammonium hydroxide (TMAH) solution, ethylenediamine pyrocatechol (EDP), potassium hydroxide (KOH) solution, or HF:H 2 O 2 :CH 3 COOH. Since the first semiconductor layer 106 and the second semiconductor layer 108 are formed of different materials having different etch selectivities, the etchant can etch the second semiconductor layer 108 at a rate greater than that of etching the first semiconductor layer 106, thereby generating an etch profile as shown in Figure 7A and Figure 7B . The etchant can also be configured and / or operated at different etch times to facilitate etching of a greater amount of SiGe than silicon.

[0143] See Figure 7A-1 , the first semiconductor layer 106 is etched such that the sidewall 106s of the first semiconductor layer 106 is recessed by a distance D5 from the interface 135 defined by the gate spacer 138 and the sacrificial gate electrode layer 134 (or the sacrificial gate dielectric layer 132). In various embodiments, the distance D5 is less than the distance D4. The presence of the distance D5 ensures that the subsequent blocking structure 141 ( Figure 14A-1 ) extends above the interface 135 ( Figure 14A-1 ) and completely covers the interface 135 ( Figure 14A-1 ), otherwise the interface 135 may become a leakage path for the etchant used during the removal of the sacrificial gate structure 130. The second semiconductor layer 108 is etched such that the sidewall 108s of the second semiconductor layer 108 is recessed by a distance D6 from the interface 135. In various embodiments, the distance D6 is greater than the distance D5. The difference between the distance D5 and the distance D6 defines the width of the inner spacer 144 ( Figure 9A and Figure 9B ).

[0144] In Figure 8A and Figure 8B , the dielectric layer 144a is conformally formed on the exposed surfaces of the sacrificial gate structure 130, the first semiconductor layer 106, the second semiconductor layer 108, and the exposed portions of the N-type well 107 and the P-type well 109 of the substrate 101. The dielectric layer 144a fills the recessed holes 131 ( Figure 7A and Figure 7B ) formed due to the removal of the edge portions of the second semiconductor layer 108. The dielectric layer 144a can be formed of a dielectric material. Suitable materials for the dielectric layer 144a can include but are not limited to SiO 2 , Si 3 N 4, SiC, SiCP, SiON, SiOC, SiCN, SiOCN, and / or other suitable materials. Other materials may also be used, such as low dielectric constant materials with a k value less than about 3.5. The dielectric layer 144a can be formed by a conformal deposition process (such as ALD). The thickness T3 of the dielectric layer 144a adjacent to the first semiconductor layer 106 (as well as the N-type well 107 and P-type well 109 of the substrate 101) can range from about 1 nm to about 4 nm, while the thickness T4 of the dielectric layer 144a adjacent to the second semiconductor layer 108 can range from about 2 nm to about 10 nm. In some embodiments, the dielectric layer 144a is a single-layer structure. In some embodiments, the dielectric layer 144a is a multi-layer structure using the materials discussed in this disclosure.

[0145] In Figure 9A and Figure 9B , multiple portions of the dielectric layer 144a are removed, and multiple portions of the dielectric layer 144a remain in the recesses 131 ( Figure 7A and Figure 7B ) between adjacent first semiconductor layers 106 to form the inner spacers 144. In some embodiments, the dielectric layer 144a adjacent to the sacrificial gate structure 130, the first semiconductor layer 106, and the N-type well 107 and P-type well 109 of the substrate 101 is removed. The removal process can be performed until the first semiconductor layer 106 is exposed. For example, the duration of the removal process can be controlled so that the dielectric layer 144a, the sacrificial gate dielectric layer 132, and the first semiconductor layer 106 on the exposed surface of the gate spacer 138 are removed. In some embodiments, the removal process is performed until at least the interface 135 ( Figure 7A-1 ) is completely exposed. The removal process can be any suitable etching process, such as dry etching, wet etching, or a combination of the above. The etching process can use an etchant that selectively removes the dielectric layer 144a without substantially removing the gate spacer 138, the first semiconductor layer 106, and the second semiconductor layer 108. The removal of multiple portions of the dielectric layer 144a can be performed by anisotropic etching. During the anisotropic etching process, the dielectric layer 144a within the recesses 131 is protected by the first semiconductor layer 106. The remaining second semiconductor layer 108 covers between the inner spacers 144 along the direction X.

[0146] In Figure 10A and Figure 10BIn [description], after removing multiple portions of the dielectric layer 144a, an epitaxial layer 148 is formed on the exposed surface (e.g., the well portion 116) of the substrate 101 to facilitate the subsequent epitaxial growth of the S / D components 146. Thus, the epitaxial layer 148 can be regarded as a part of the S / D components 146. In some embodiments, a portion of the epitaxial layer 148 can be further formed on the exposed surface of the first semiconductor layer 106. The epitaxial layer 148 can be an undoped semiconductor layer. The epitaxial layer 148 can be formed of other materials capable of providing a structural transition and / or a diffusion barrier. For example, the epitaxial layer 148 can include one or more of Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP, depending on the material selection in the S / D components 146 and subsequent film layers. In one embodiment, the epitaxial layer 148 is an undoped silicon layer and can be formed using selective epitaxial growth (SEG), ALD, MBE, or any suitable growth process.

[0147] In Figure 11A and Figure 11B In [description], a hard mask layer 137 is deposited on the exposed surface of the semiconductor device 100, and a photoresist layer 139 is formed on the hard mask layer 137. The hard mask layer 137 can be a conforming layer disposed on the exposed surfaces of the sacrificial gate structure 130, the first semiconductor layer 106, the inner spacer 144, and the epitaxial layer 148. The photoresist layer 139 can be deposited on the hard mask layer 137 until the sacrificial gate structure 130 is embedded within the photoresist layer 139. The hard mask layer 137 will be patterned for subsequent process regions of one type of device, such as an N-type device in the first device region 103 or a P-type device in the second device region 105. In some embodiments, the hard mask layer 137 is an oxide, such as aluminum oxide (AlO x ). Other suitable materials capable of withstanding the process conditions of subsequent epitaxial source / drain formation and having an etching selectivity for the subsequently formed self-aligned mask can be used for the hard mask layer 137.

[0148] In Figure 12A and Figure 12BTherein, a lithography process is performed to pattern the photoresist layer 139 and expose a process region for one type of device, such as an N-type device region or a P-type device region. The first device region 103 remains protected by the hard mask layer 137 and the photoresist layer 139. In an exemplary embodiment, the photoresist layer 139 of the second device region 105 is patterned to expose the region above the N-type well 107, where P-type devices will be formed. The photoresist layer 139 can be removed by any suitable process, such as a wet strip process. After the lithography process, an etching process is performed to remove portions of the hard mask layer 137 located in the second device region 105. The etching process for removing portions of the hard mask layer 137 can include a wet etching process, exposing a process region for one type of device, such as a P-type device region. Then, a blocking structure 141 doped with a P-type dopant (e.g., boron) is formed on the exposed surfaces of the first semiconductor layer 106 and the epitaxial layer 148.

[0149] The blocking structure 141 serves as an etch stop layer to prevent etchant chemicals (used during subsequent removal of the second semiconductor layer 108) from leaking through the interface 135 ( Figure 12A-1 ) and into the S / D components 146. If the interface 135 is not blocked, the etching process for removing the second semiconductor layer 108 may also remove the subsequently formed S / D components 146 ( Figure 13A ), resulting in damage to the S / D components 146. In some cases, the S / D components 146 can even be completely removed by the etching process. The use of the blocking structure 141 ensures that the interface 135 is blocked, which in turn minimizes damage to the S / D components 146 during removal of the second semiconductor layer 108. Thus, the integrity of the S / D components 146 is retained.

[0150] The blocking structure 141 can grow vertically and horizontally to form facets, which can correspond to the crystal planes of the material of the first semiconductor layer 106. Facets can be formed because the growth rates on different surface planes are different. For example, during the growth of the blocking structure 141, the growth rate on the (111) plane of the first semiconductor layer 106 (e.g., silicon) can be lower than the growth rates on other planes (such as the (110) and (100) planes of the first semiconductor layer 106). Thus, facets are formed due to the difference in growth rates of different planes. The facets of the blocking structure 141 can include planes from the {111} plane family, {100} plane family, {311} plane family, {911} plane family.

[0151] In one embodiment, the blocking structure 141 can have a rhombus-like shape. In some embodiments, the blocking structure 141 can have a circular surface. Figure 12A-1 is shown according to some embodimentsFigure 12A An enlarged schematic view of part B of the semiconductor device structure. As can be seen from Figure 12A-1 it, the blocking structure 141 contacts the sidewall 106s of the first semiconductor layer 106, the sacrificial gate dielectric layer 132, and the gate spacer 138. Specifically, the blocking structure 141 extends across and covers the interface 135 defined by the gate spacer 138 and the sacrificial gate dielectric layer 132 (or the sacrificial gate electrode layer 134).

[0152] In some embodiments, the blocking structure 141 is formed of a doped semiconductor or a doped semiconductor compound, such as doped silicon, doped germanium, doped silicon germanium, or the like. In various embodiments, the dopant can be selected from group III elements, such as boron. Thus, the blocking structure 141 can comprise or can be a boron-doped semiconductor material or a compound containing boron and a semiconductor material. For example, the blocking structure 141 can be boron-doped silicon (Si:B), a compound of boron and silicon, such as silicon triboride (SiB 3 ), silicon hexaboride (SiB 6 ), or the like, boron-doped germanium (Ge:B), or boron-doped silicon germanium (SiGe:B). In some embodiments, the blocking structure 141 is a boron-rich layer with a boron concentration in the range of about 1 atomic percent to about 20 atomic percent. If the boron concentration is less than about 1 atomic percent, the blocking structure 141 may not be able to prevent the etchant from leaking through the interface 135 during subsequent gate replacement processes. On the other hand, if the boron concentration is greater than about 20 atomic percent, the manufacturing cost will increase and there is no significant additional advantage for preventing etchant leakage. In some embodiments that can be combined with any one or more embodiments of the present disclosure, the blocking structure 141 has a constant germanium concentration throughout the entire body of the blocking structure 141. In some embodiments, the germanium in the blocking structure 141 has a concentration that gradually changes along the thickness of the blocking structure 141. For example, the blocking structure 141 can have a gradually increasing germanium concentration along the direction X. Alternatively, the blocking structure 141 can have a gradually decreasing germanium concentration along the direction X.

[0153] In some embodiments, the blocking structure 141 can have a range of about 5E20 atoms / cm 3 to about 1E22 atoms / cm 3The dopant concentration. For example, boron doping can be incorporated into the barrier structure 141 during the growth of the barrier structure 141 by an epitaxial process or after the formation of the barrier structure 141 by an implantation process. In some embodiments, the barrier structure 141 can be a strained or relaxed structure. The barrier structure 141 can have a thickness D7 ranging from about 0.5 nm to about 10 nm. It has been observed that the barrier structure 141 formed of a highly doped semiconductor (e.g., Si:B) can effectively block leakage through the interface 135. The barrier structure 141 can also delay the etchant chemicals for removing the second semiconductor layer 108 during the formation of the nanostructured channel in the multi-gate device. Thus, the integrity of the subsequent S / D components 146 is protected. The highly boron-doped barrier structure 141 also helps to reduce the resistivity of the S / D components 146 (P-type epitaxy). Additionally, it may be advantageous to use a boron-doped semiconductor as the barrier structure 141 because the boron dopant can change the crystal orientation of the underlying materials (e.g., the first semiconductor layer 106 and the N-type well 107, P-type well 109 of the substrate 101) to facilitate the formation of facets of the barrier structure 141, and thus facilitate the growth of the subsequent epitaxial S / D components 146 on the faceted barrier structure 141.

[0154] Depending on the material of the barrier structure 141 to be formed, the exposed surface of the semiconductor device structure 100 can be exposed to (a) silicon precursor(s), (a) germanium precursor(s), (a) boron precursor(s), an etch gas, and a diluent / carrier gas during the formation of the barrier structure 141. In the case where the barrier structure 141 comprises boron-doped silicon germanium (SiGe:B), the barrier structure 141 can be formed by heating the semiconductor device structure 100 to a temperature of about 300 degrees Celsius to about 800 degrees Celsius and exposing the first semiconductor layer 106 (and the N-type well 107, P-type well 109 of the substrate 101) to a precursor comprising at least a silicon precursor, a germanium precursor, and a boron precursor. Suitable silicon precursors can include but are not limited to silane (SiH 4 ), disilane (Si 2 H 6 ), trisilane (Si 3 H 8 ), tetrasilane (Si 4 H 10 ), dimethylsilane ((CH 3 ) 2 SiH 2 ), methylsilane (SiH(CH 3 ) 3 ), dichlorosilane (SiH 2 Cl 2, dichlorosilane; DCS), trichlorosilane (SiHCl 3 , trichlorosilane; TCS), or analogs thereof. Suitable germanium-containing precursors may include but are not limited to germane (GeH 4 ), digermane (Ge 2 H 6 ), trigermane (Ge 3 H 8 ), or germylsilane (GeH 6 Si), or analogs thereof. Suitable gases for boron-containing precursors may include but are not limited to borane (BH 3 ), diborane (B 2 H 6 ), boron trichloride (BCl 3 ), triethyl borate (TEB), borazine (B 3 N 3 H 6 ), or alkyl-substituted derivatives of borazine, or analogs thereof. In the case of using (multiple) etch gases (e.g., in a cyclic deposition etch (CDE) epitaxial process or a selective etch growth (SEG) process), the deposition process may use one or more etch gases. Suitable etch gases may include but are not limited to hydrogen chloride (HCl), chlorine (Cl 2 ), or analogs thereof. Diluent / purge gases, such as hydrogen (H 2 ), nitrogen (N 2 ) and / or argon (Ar), may be used with the precursors of the barrier structure 141. In one embodiment, the barrier structure 141 is formed using a precursor comprising SiH 4 and DCS and B 2 H 6 . In another embodiment, the barrier structure 141 is formed using a precursor comprising DCS, GeH 4 and B 2 H 6 . In yet another embodiment, the barrier structure 141 is formed using a precursor comprising DCS, GeH 4 , and BCl 3 . The formation of the barrier structure 141 may be performed in an epitaxy or CVD-based reaction chamber.

[0155] In some embodiments, the blocking structure 141 is boron-doped silicon (Si:B) deposited by CDE epitaxy process. The CDE epitaxy process can be carried out in a process chamber at a temperature in the range of about 300 °C to 800 °C, at a pressure in the range of about 1 Torr to 760 Torr, and the duration of the execution ranges from about 20 seconds to 300 seconds, by exposing the semiconductor device structure 100 to one or more silicon-containing precursors (e.g., SiCl 2 H 2 、SiH 4 etc.), p-type dopant gas (e.g., B 2 H 6 ), and carrier gas (e.g., Ar, H 2 etc.) for a first period of time to form a first part of the blocking structure 141, followed by selective etching, wherein the first part of the blocking structure 141 is exposed to an etchant (e.g., HCl etc.) for a second period of time to selectively remove the amorphous or polycrystalline part of the blocking structure 141 while keeping the crystalline part of the blocking structure 141 intact. A purge gas (e.g., N 2 ) can be flowed into the process chamber between epitaxial growth and selective etching. The (multiple) silicon-containing precursors can be provided at a flow rate in the range of about 10 sccm to about 500 sccm, the dopant gas can be provided at a flow rate in the range of about 10 sccm to about 500 sccm, the carrier gas can be provided at a flow rate in the range of about 0 sccm to about 50000 sccm, and the purge gas can be provided at a flow rate in the range of about 0 sccm to about 50000 sccm. The epitaxial growth and selective etching of the CDE epitaxy process are repeated until the blocking structure 141 reaches the desired thickness and the above-mentioned dopant concentration (e.g., reaches the first dopant concentration).

[0156] Once the predetermined volume of the blocking structure 141 is reached, the flow of the (multiple) boron-containing precursors can be terminated, and a Group IV or Group V precursor can be introduced into the fabrication chamber together with the silicon-containing precursor to form the S / D component 146. Thus, the blocking structure 141 is formed of a material having a different chemical property from the subsequent S / D component 146. The dopant in the S / D component 146 can be added during the formation of the S / D component 146, or added by an implantation process after the formation of the S / D component 146.

[0157] In Figure 13A and Figure 13BIn [the description], after forming the blocking structure 141, the S / D components 146 are formed in the S / D regions between the adjacent sacrificial gate structures 130 in the second device region 105. The epitaxial S / D components 146 may include a first epitaxial layer 146a and a second epitaxial layer 146b formed on the first epitaxial layer 146a. The first epitaxial layer 146a and the second epitaxial layer 146b may be formed by any suitable process, such as a cyclic deposition etching (CDE) epitaxial process, a selective etching growth (SEG) process, ALD, molecular beam epitaxy (MBE), or any combination of the above. The S / D components 146 may be the S / D regions. For example, one of a pair of S / D components 146 located on one side of the sacrificial gate structure 130 may be a source region, and the other of a pair of S / D components 146 located on the other side of the sacrificial gate structure 130 may be a drain region. A pair of S / D components 146 includes a source component and a drain component connected by a nanostructure channel (i.e., the first semiconductor layer 106). Source and drain are used interchangeably in the present disclosure.

[0158] The first epitaxial layer 146a is conformally formed on the blocking structure 141 and the inner spacer 144. In some embodiments, the first epitaxial layer 146a includes the same material as the epitaxial layer 148 but has a higher dopant concentration. In some embodiments, the first epitaxial layer 146a is formed of silicon germanium and the Ge concentration ranges from about 25% to 40%. Depending on the conductivity type of the device to be formed in the second device region 105, the first epitaxial layer 146a may have an n-type dopant or a p-type dopant. The first epitaxial layer 146a serves as a leakage barrier layer to prevent the possible diffusion of subsequent backside metal elements into the gate region. The first epitaxial layer 146a may also serve as a lattice transition layer between the blocking structure 141 and the second epitaxial layer 146b.

[0159] In some embodiments, the first epitaxial layer 146a is a highly doped layer. In this case, the first epitaxial layer 146a may include a P-type dopant and the dopant concentration may range from about 1E20 atoms / cm 3 to about 8E20 atoms / cm 3 . In some embodiments, the first epitaxial layer 146a includes phosphorus and the dopant concentration ranges from about 1E20 atoms / cm 3 to about 5E20 atoms / cm 3The dopants can be implanted using the sacrificial gate structure 130 and the gate spacers 138 as masks. The thickness of the first epitaxial layer 146a along the direction Z can range from about 3 nm to about 20 nm. If the thickness of the first epitaxial layer 146a is less than 3 nm, the thickness of the first epitaxial layer 146a may not be sufficient to serve as a leakage barrier layer or a lattice transition layer between the blocking structure 141 and the second epitaxial layer 146b to be formed. If the thickness of the first epitaxial layer 146a is greater than 20 nm, the manufacturing cost will increase and there is no obvious additional advantage for the transition of the crystal structure.

[0160] The second epitaxial layer 146b is formed on the first epitaxial layer 146a and has sidewalls at least surrounded by the first epitaxial layer 146a. In some embodiments, at least three surfaces of the second epitaxial layer 146b are in contact with the first epitaxial layer 146a. The second epitaxial layer 146b forms the main part of the epitaxial S / D component 146. In the case where the second device region 105 is used to form a P-type device, the second epitaxial layer 146b can include Si, SiGe, or Ge. In some embodiments, the second epitaxial layer 146b is formed of silicon germanium, and the Ge concentration ranges from about 50% to 60%. Depending on the conductivity type of the device to be formed in the second device region 105, the second epitaxial layer 146b can have n-type dopants or p-type dopants. In either case, the dopant concentration of the second epitaxial layer 146b is greater than the dopant concentration of the first epitaxial layer 146a. The higher dopant concentration of the second epitaxial layer 146b can reduce the contact resistance of the epitaxial S / D component 146 and provide better conductivity for the subsequently formed source / drain metal contacts (e.g., Figure 19A and Figure 19B the source / drain contact 186 in 3 to about 3E21 atoms / cm 3 . In some embodiments, the second epitaxial layer 146b includes boron and the dopant concentration ranges from about 8E20 atoms / cm 3 to about 3E21 atoms / cm 3 . Similarly, the sacrificial gate structure 130 and the gate spacers 138 can be used as masks to implant the dopants for the second epitaxial layer 146b. Alternatively, the dopants for the first epitaxial layer 146a and the second epitaxial layer 146b can be implanted after the first epitaxial layer 146a and the second epitaxial layer 146b are formed.

[0161] In Figures 14A to 14D , the S / D component 146 and the sacrificial gate structure 130 in the second device region 105 are protected by the hard mask layer 113 and the photoresist layer 115 (such as seen above Figure 11Aand Figure 11B the hard mask layer 137 and the photoresist layer 139 discussed above. Once the second device region 105 has been protected, the hard mask layer 137 and the photoresist layer 139 of the first device region 103 are removed (e.g., by ashing) to expose the sacrificial gate structure 130, the first semiconductor layer 106, the inner spacer 144, and the epitaxial layer 148. Then, S / D components 147 are formed in the S / D regions between adjacent sacrificial gate structures 130 of the first device region 103.

[0162] The S / D components 147 may include a first epitaxial layer 147a, a second epitaxial layer 147b, and a third epitaxial layer 147c. The first, second, and third epitaxial layers 147a, 147b, 147c may be formed by any suitable process, such as a cyclic deposition etch (CDE) epitaxial process, a selective etch growth (SEG) process, ALD, molecular beam epitaxy (MBE), or any combination of the above. The first epitaxial layer 147a may include a semiconductor material, such as Si, SiP, SiC, SiAs, and SiCP. The first epitaxial layer 147a may have an n-type dopant (e.g., phosphorus (P) or arsenic (As)). The first epitaxial layer 147a may have a first dopant concentration that is lower than the dopant concentration of the second epitaxial layer 147b. The lower dopant concentration of the first epitaxial layer 147a avoids dopant diffusion into the channel region (e.g., the first semiconductor layer 106). The first epitaxial layer 147a may also be used as a barrier structure to prevent etchant chemicals (used during subsequent removal of the second semiconductor layer 108) from leaking into the S / D components 147. In some embodiments, the first epitaxial layer 147a may be an undoped silicon layer. The first epitaxial layer 147a on the first semiconductor layer 106 may have a curved or circular surface.

[0163] The second epitaxial layer 147b is formed on the first epitaxial layer 147a. In some embodiments, the second epitaxial layer 147b is a semiconductor material, such as Si, SiP, SiC, SiAs, and SiCP. Similarly, the second epitaxial layer 147b may have an n-type dopant. The second epitaxial layer 147b may have a second dopant concentration that is lower than the dopant concentration of the third epitaxial layer 147c. In some embodiments, the second dopant concentration ranges from about 15E19 atoms / cm 3 to about 5E20 atoms / cm 3 . Similar to the first epitaxial layer 146a, the second epitaxial layer 147b may have a thickness along the direction Z ranging from about 3 nm to about 15 nm.

[0164] A third epitaxial layer 147c is formed on the second epitaxial layer 147b and has sidewalls that are at least surrounded by the second epitaxial layer 147b. The third epitaxial layer 147c forms a major part of the epitaxial S / D component 147. Approximately, the third epitaxial layer 147c can be a semiconductor material such as Si, SiP, SiC, SiAs, and SiCP. The third epitaxial layer 147c can have an n-type dopant. The third epitaxial layer 147c can have a third dopant concentration that is higher than the second dopant concentration of the second epitaxial layer 147b. The higher dopant concentration of the third epitaxial layer 147c can reduce the contact resistance of the epitaxial S / D component 147 and provide better conductivity for a subsequently formed source / drain metal contact (e.g., Figure 19A and Figure 19B the S / D contact 186 in 3 to about 5E21 atoms / cm 3 .

[0165] Figure 14A-1 is an enlarged schematic view of part C of a semiconductor device structure, showing Figure 14A in accordance with some embodiments, Figure 14B-1 is an enlarged schematic view of part D of a semiconductor device structure, showing Figure 14B in accordance with some embodiments, and shows the barrier structure 141 and the first epitaxial layer 147a, respectively. As can be seen from Figure 14A-1 , the barrier structure 141 is a faceted structure having a rhombus-shaped shape. The faceted structure is formed with at least facets 141a, 141b. The facets 141a, 141b of the faceted structure provide an increased surface area to facilitate the epitaxial growth of the S / D component 146 (the first epitaxial layer 146a, the second epitaxial layer 146b). Specifically, the barrier structure 141 extends above and covers an interface 135 defined by the gate spacer 138 and the sacrificial gate dielectric layer 132 (or the sacrificial gate electrode layer 134). Figure 14B-1 The embodiment shown in Figure 14A-1 is similar to the embodiment in

[0166] Figure 14E is a top-down schematic view of a portion of the semiconductor device structure 100 taken along a cross-section E-E of Figure 14A in accordance with some embodiments. As can be seen from Figure 14EAs can be seen, the blocking structure 141 grows from the first semiconductor layer 106. The blocking structure 141 may have at least three surfaces in contact with the first epitaxial layer 146a of the S / D component 146. The first side of the inner spacer 144 is substantially flat and is disposed against the S / D component 146 (e.g., the first epitaxial layer 146a), while the second side of the inner spacer 144 is curved (e.g., has a substantially convex shape) and is disposed against the cladding layer 117. It should be noted that the cladding layer 117 will subsequently be removed and replaced with materials from the replacement gate structure 190( Figure 18B ), such as the interface layer (IL) 178, the gate dielectric layer 180, and / or the gate electrode layer 182b. Thus, in some embodiments, the inner spacer 144 may be in contact with the interface layer 178 (e.g., Figure 18E ), the gate dielectric layer 180 (e.g., Figure 18E ), and / or the gate electrode layer 182a (e.g., Figure 18E ).

[0167] Figure 14F FIG. is a top-down schematic view of a portion of the semiconductor device structure 100 taken along the Figure 14A section F-F according to some embodiments. In this schematic view, portions of the second semiconductor layer 108 and the cladding layer 117 are concave because they may contain the same material (e.g., SiGe). The removal of portions of the second semiconductor layer 108 and the cladding layer 117 creates space for the inner spacer 144. In one embodiment, the inner spacer 144 may include a first portion 144-1 disposed between and in contact with the second semiconductor layer 108 and the S / D component 146 (e.g., the first epitaxial layer 146a), and at least a second portion 144-2 disposed between and in contact with the cladding layer 117 and the S / D component 146 (e.g., the first epitaxial layer 146a). The first sides of the first portion 144-1 and the second portion 144-2 are substantially flat and are disposed against the S / D component 146, while the second sides of the first portion 144-1 and the second portion 144-2 are curved (having, for example, a substantially convex shape). Similarly, the cladding layer 117 and the second semiconductor layer 108 will subsequently be removed and replaced with materials from the replacement gate structure 190, such as the interface layer 178, the gate dielectric layer 180, and / or the gate electrode layer 182b. Thus, in some embodiments, the first portion 144-1 and the second portion 144-2 may be in contact with the interface layer 178 (e.g., Figure 18F ), the gate dielectric layer 180 (e.g., Figure 18F ), and / or the gate electrode layer 182b (e.g., Figure 18F ).

[0168] In Figures 15A to 15DIn [description], after forming the S / D components 146, 147, a contact etch stop layer (CESL) 162 is conformally formed on the exposed surface of the semiconductor device structure 100. The CESL 162 covers the S / D components 146, 147, the gate spacers 138, and the dielectric material 125 at the first and second device regions 103, 105. The CESL 162 can comprise an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbonitride, silicon oxynitride, carbon nitride, silicon oxide, silicon carbon oxide, or the like, or a combination of the foregoing, and can be formed by CVD, PECVD, ALD, or any suitable deposition technique. Then, an interlayer dielectric (ILD) layer 164 is formed on the CESL 162 over the semiconductor device structure 100. The material of the ILD layer 164 can comprise an oxide formed using tetraethylorthosilicate (TEOS), undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials containing Si, O, C, and / or H. The ILD layer 164 can be deposited by a PECVD process or other suitable deposition techniques.

[0169] In Figure 16A FIG. to Figure 16D In [description], once the ILD layer 164 is formed, a planarization operation such as CMP is performed on the semiconductor device structure 100 to remove portions of the ILD layer 164, the CESL 162, and the mask layer 136 until the sacrificial gate electrode layer 134 is exposed.

[0170] In Figure 17A FIG. to Figure 17DTherein, the sacrificial gate structures 130, the cladding layer 117, and the second semiconductor layer 108 are removed from the semiconductor device structures 100 of the first and second device regions 103, 105. The removal of the sacrificial gate structures 130 and the second semiconductor layer 108 forms openings 166 between the gate spacers 138 and between the first semiconductor layers 106. The ILD layer 164 protects the epitaxial S / D components 146 during the removal process. Plasma dry etching and / or wet etching can be used to remove the sacrificial gate structures 130. The sacrificial gate electrode layer 134 can first be removed by any suitable process, such as dry etching, wet etching, or a combination of the above, and then the sacrificial gate dielectric layer 132 is removed, which can also be performed by any suitable process, such as dry etching, wet etching, or a combination of the above. In some embodiments, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution can be used to selectively remove the sacrificial gate electrode layer 134 without removing the gate spacers 138, the dielectric material 125, the ILD layer 164, and the CESL 162. In some embodiments, the gate spacers 138 can be etched recess by the etchant used to remove the sacrificial gate electrode layer 134 and / or the sacrificial gate dielectric layer 132.

[0171] After removing the sacrificial gate structures 130, the cladding layer 117 and the second semiconductor layer 108 are exposed. The removal of the cladding layer 117 and the second semiconductor layer 108 exposes the first semiconductor layer 106. During the removal of the cladding layer 117 and the second semiconductor layer 108, the blocking structure 141 (and the first epitaxial layer 147a) minimizes or avoids damage to the S / D components 146, 147 by blocking the etchant from passing through the interface 135 (defined by the sacrificial gate dielectric layer 132 and the gate spacers 138, see Figure 14A-1 ). Thus, the integrity of the S / D components 146, 147 is retained. The removal process can be any suitable etching process, such as dry etching, wet etching, or a combination of the above. The etching process can use an etchant that selectively removes the cladding layer 117 and the second semiconductor layer 108 while substantially not removing the gate spacers 138, the ILD layer 164, the CESL 162, the dielectric material 125, the first semiconductor layer 106, the blocking structure 141, and the first epitaxial layer 147a. In one embodiment where the first semiconductor layer 106 is Si and the second semiconductor layer 108 is SiGe, the etchant can be ammonium hydroxide (NH 4 OH) and H 2 O 2 solution or any suitable etchant. When the sacrificial gate structures 130 and the second semiconductor layer 108 are removed, a portion of the first semiconductor layer 106, the blocking structure 141, and the first epitaxial layer 147a are exposed in the openings 166.

[0172] In Figures 18A to 18D , a replacement gate structure 190 is formed in a region provided by removing the cladding layer 117 and the second semiconductor layer 108 at the first device region 103 and the second device region 105. Each of the replacement gate structures 190 includes an interface layer (IL) 178, a gate dielectric layer 180, and a gate electrode layer 182a / 182b. The interface layer (IL) 178 is formed to surround the exposed surface of the first semiconductor layer 106. The interface layer 178 may also be formed on the exposed N-type well 107 and P-type well 109 of the substrate 101. The interface layer 178 may comprise or be formed of an oxygen-containing material or a silicon-containing material, such as silicon oxide, silicon oxynitride, nitrogen oxide, hafnium silicate, etc. In one embodiment, the interface layer 178 is silicon oxide. The interface layer 178 may be formed by CVD, ALD, a cleaning process, or any suitable process. Next, a gate dielectric layer 180 is formed on the exposed surface of the semiconductor device structure 100. Multiple portions of the interface layer 178 and the optional gate dielectric layer 180 are in contact with the blocking structure 141. In some embodiments, the gate dielectric layer 180 is formed to wrap around and contact the interface layer 178. The gate dielectric layer 180 is also formed on and in contact with the liner 119 and the dielectric material 125 ( Figure 18C and Figure 18D ). The gate dielectric layer 180 may comprise or be formed of a high-k dielectric material, such as hafnium oxide (HfO 2 ), hafnium silicate (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), hafnium zirconium oxide (HfZrO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), lanthanum oxide (LaO), aluminum oxide (Al 2 O 3 ), aluminum silicon oxide (AlSiO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta 2 O 5 ), yttrium oxide (Y 2 O 3 ), silicon oxynitride (SiON), a combination of an oxide with a nitrogen-doped dielectric and a high-k dielectric with a high metal content (having a k value > 13), or other suitable dielectrics having a k value ≧ 9. The gate dielectric layer 180 may be a conformal layer formed by a conformal process such as an ALD process or a CVD process. The gate dielectric layer 180 may have a thickness in the range of about 0.5 nm to about 3 nm.

[0173] After forming the interface layer 178 and the gate dielectric layer 180, a gate electrode layer 182a / 182b is formed above the gate dielectric layer 180. The gate electrode layer 182a may be formed to fill the opening 166 ( Figure 17Aand Figure 17B ) and a portion of each first semiconductor layer 106 that completely surrounds the second device region 105. A gate electrode layer 182b may be formed to fill the opening 166 and completely surround a portion of each first semiconductor layer 106 of the first device region 103. In some embodiments, the gate electrode layers 182a, 182b may be formed using a multi-film layer, and each film layer is sequentially deposited adjacent to each other using a highly conformal deposition process such as ALD. Other deposition techniques may also be used, such as physical vapor deposition (PVD), CVD, or electroplating. Although not shown, the gate electrode layer 182a may include a capping layer, a barrier layer, an n-type metal work function layer, a p-type metal work function layer, and a filling material. The capping layer and the barrier layer may be metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicate, zirconium aluminate, combinations of the above, or analogs thereof. The barrier layer may be formed of a material different from the capping layer. The n-type metal work function layer may be formed of a metal material such as W, Cu, AlCu, TiAlC, TiAlN, Ti, TiN, Ta, TaN, Co, Ni, Ag, Al, TaAl, TaAlC, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations of the above. The p-type metal work function layer may be formed of a metal material such as W, Al, Cu, TiN, Ti, TiAlN, Ta, TaN, Co, Ni, TaC, TaCN, TaSiN, TaSi 2 , NiSi 2 , Mn, Zr, ZrSi 2 , TaN, Ru, AlCu, Mo, MoSi 2 , WN, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicate, zirconium aluminate, combinations of the above, or analogs thereof. Once the n-type metal work function layer and the p-type metal work function layer are formed, a filling material is deposited to fill the remaining portion of the opening 166. The material of the filling material may be such as W, Al, Cu, AlCu, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ta, TaN, Co, Ni, combinations of the above, or analogs thereof.

[0174] Similarly, the gate electrode layer 182b can be formed using a multi-layer film, and the material is similar to the gate electrode layer 182a discussed above. In some embodiments, one or more layers within the gate electrode layer 182a and the gate electrode layer 182b can be formed during the same series of steps. For example, the capping layer and the barrier layer in both the gate electrode layer 182a and the gate electrode layer 182b can be formed simultaneously, while other film layers such as the n-type metal work function layer and the p-type metal work function layer can be formed and / or patterned independently of each other. Any suitable combination of deposition and removal can be utilized to form the gate electrode layer 182a and the gate electrode layer 182b.

[0175] Once the opening 166 is filled, the materials of the gate electrode layer 182a and the gate electrode layer 182b can be planarized by a planarization process (e.g., CMP) to remove any material outside the opening left after removing the sacrificial gate electrode layer 134.

[0176] Figure 18A-1 is an enlarged schematic view of part E of the semiconductor device structure 100, shown Figure 18A in accordance with some embodiments. The first semiconductor layer 106 defined between two adjacent barrier structures 141 can have a length D8. The interface layer 178 is disposed between and in contact with the gate dielectric layer 180 and the first semiconductor layer 106. A portion of the interface layer 178 further contacts the barrier structure 141. The interface layer 178 above the topmost first semiconductor layer 106 can have a length D9 greater than the length D8. The first semiconductor layer 106 is surrounded by the interface layer 178. The gate dielectric layer 180 is disposed to surround the interface layer 178. The gate electrode layer 182a is disposed on the interface layer 178 and configured to surround the first semiconductor layer 106. The barrier structure 141 contacts the topmost first semiconductor layer 106, the interface layer 178, the gate spacer 138, and the first epitaxial layer 146a. In some embodiments, the barrier structure 141 further contacts the CESL 162 (FIG. 18A-2). Specifically, the barrier structure 141 extends a distance along the direction X to cover the interface 167 defined by the interface layer 178 and the gate spacer 138. Figure 18A-2 is an enlarged schematic view of part F of the semiconductor device structure 100, shown Figure 18A-1 in accordance with some embodiments. In this embodiment, during the removal of the sacrificial gate structure 130, a portion of the barrier structure 141 is removed, resulting in the formation of a groove (facet 141a) adjacent to the interface 167. The bottom of the interface layer 178 in contact with the topmost first semiconductor layer 106 can have a curved profile due to the groove (facet 141a).

[0177] Figure 18EAccording to some embodiments, a top view schematic diagram shows a part of the semiconductor device structure 100 taken along the cross-section E-E of FIG. 18A. Figure 18E The illustrated embodiment is substantially the same as Figure 14E the illustrated embodiment, but the difference is that the cladding layer 117 has been replaced by the gate electrode layer 182a. Figure 18F According to some embodiments, a top view schematic diagram shows a part of the semiconductor device structure 100 along Figure 18A the cross-section F-F. Similarly, Figure 18F the illustrated embodiment is substantially the same as Figure 14F the illustrated embodiment, but the difference is that the second semiconductor layer 108 and the cladding layer 117 have been replaced by the gate electrode layer 182b.

[0178] In Figures 19A to 19D , one or more metal gate etching back (MGEB) processes can be performed on the gate electrode layers 182a, 182b. The MGEB process is performed to etch the top surfaces of the gate electrode layers 182a, 182b and the gate dielectric layer 180 to a level lower than the top surface of the gate spacer 138. In some embodiments, the gate spacer 138 is also etched to a level lower than the top surface of the ILD layer 164, as shown in Figure 19A and Figure 19B . The self-aligned contact layer 173 is formed above the gate electrode layers 182a, 182b and the gate dielectric layer 180 between the gate spacers 138. The self-aligned contact layer 173 can be a dielectric material having an etching selectivity with respect to the ILD layer 164. In some embodiments, the self-aligned contact layer 173 can be a dielectric material such as silicon nitride or a high-k dielectric layer. Once the self-aligned contact layer 173 is formed, a planarization process such as CMP can be used to planarize the self-aligned contact layer 173.

[0179] After forming the self-aligned contact layer 173, contact openings are formed through the ILD layer 164 and the CESL 162 to expose the epitaxial S / D components 146, 147. Then, a silicide layer 184 is formed on the epitaxial S / D components 146, 147, and S / D contacts 186 are formed in the contact openings on the silicide layer 184. The S / D contacts 186 may comprise an electrically conductive material such as Al, Cu, W, Co, Ti, Ta, Ru, TiN, TiAl, TiAlN, TaN, TaC, NiSi, CoSi, combinations thereof, or the like. Silicidation may be performed by blanket deposition of a suitable metal layer, followed by an annealing step to react the metal with the underlying exposed silicon. The unreacted metal is then removed by, for example, a selective etching process. The S / D contacts 186 may be formed in the contact openings using sputtering, CVD, electroplating, electroless plating, or similar methods to fill and / or overfill the contact openings. A planarization process such as CMP may be used to remove any deposited material outside the contact openings.

[0180] Subsequently, the semiconductor device structure 100 may undergo further complementary metal oxide semiconductor (CMOS) and / or back-end-of-line (BEOL) processes to form various components such as transistors, contacts / vias, interconnect metal layers, dielectric layers, passivation layers, and the like.

[0181] The various embodiments or examples described in the present disclosure provide several advantages over the prior art. According to an embodiment of the present disclosure, prior to the gate replacement process, damage to the S / D components of the nanostructured channel FET caused by the line release process can be prevented by providing a barrier structure 141 to seal the interface 135 defined by the sacrificial gate dielectric and the gate spacer ( Figure 14A-1 ). The barrier structure 141 may be a highly doped semiconductor (e.g., Si:B) or a compound material (e.g., SiGe:B). The barrier structure 141 can effectively prevent the etchant chemicals used during the nanostructure formation process from leaking through the interface 135 to the S / D components. Thus, the integrity of the S / D components is maintained. The use of a highly doped semiconductor in the barrier structure 141 also helps to reduce the resistivity in the p-type epitaxy.

[0182] The present disclosure provides an embodiment of a semiconductor device structure. The semiconductor device structure includes a first source / drain component and a second source / drain component, a plurality of semiconductor layers vertically stacked and disposed between the first source / drain component and the second source / drain component, a gate electrode layer surrounding a portion of each semiconductor layer, and an interface layer (IL) disposed between the gate electrode layer and one of the semiconductor layers, wherein the topmost semiconductor layer of the semiconductor layers has a first length, and the interface layer has a second length greater than the first length.

[0183] In some embodiments, the semiconductor device structure further includes a blocking structure in contact with sidewalls of each semiconductor layer. In some embodiments, the semiconductor device structure further includes a gate spacer in contact with the interface layer and the blocking structure. In some embodiments, a portion of the blocking structure is in contact with the first source / drain component or the second source / drain component. In some embodiments, the blocking structure extends above an interface defined by the interface layer and the gate spacer. In some embodiments, the blocking structure includes a doped semiconductor or a doped semiconductor compound. In some embodiments, the blocking structure is a boron-doped semiconductor material or a compound containing boron and a semiconductor material. In some embodiments, the blocking structure has a dopant concentration in the range of about 1 atomic percent to about 20 atomic percent. In some embodiments, the blocking structure is boron-doped silicon germanium. In some embodiments, the blocking structure has a constant concentration of germanium throughout the thickness of the blocking structure. In some embodiments, the germanium in the blocking structure has a concentration that varies gradually along the thickness of the blocking structure.

[0184] The present disclosure provides another embodiment of a semiconductor device structure. The semiconductor device structure includes a plurality of semiconductor layers vertically and parallelly stacked, a gate electrode layer completely surrounding a portion of each semiconductor layer, an interface layer disposed between the gate electrode layer and the topmost semiconductor layer of the semiconductor layers, a gate spacer adjacently disposed to the gate electrode layer and in contact with the interface layer, and a blocking structure in contact with sidewalls of each semiconductor layer, wherein the blocking structure covers an interface defined by the interface layer and the gate spacer.

[0185] In some embodiments, the interface layer in contact with the topmost semiconductor layer has a first length, and the topmost semiconductor layer of the semiconductor layers has a second length less than the first length. In some embodiments, the blocking structure has a rhomboid shape in a cross-sectional view. In some embodiments, the blocking structure is a faceted structure having planes from the {111} plane family, the {100} plane family, the {311} plane family, or the {911} plane family. In some embodiments, the blocking structure is a boron-doped semiconductor material or a compound containing boron and a semiconductor material. In some embodiments, the blocking structure includes a range of about 5E20 atoms / cm 3 to about 1E22 atoms / cm 3The doping concentration.

[0186] The present disclosure provides an embodiment of a method for forming another semiconductor device structure. The method includes forming a fin structure from a stack of a plurality of semiconductor layers, the stack including a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked alternately, forming a sacrificial gate structure over a portion of the fin structure, the sacrificial gate structure including a sacrificial gate dielectric and a sacrificial gate electrode layer, forming gate spacers on a plurality of sidewalls of the sacrificial gate structure, removing a plurality of portions of the fin structure not covered by the sacrificial gate structure, performing an etching process on the first semiconductor layer and the second semiconductor layer to form a plurality of recesses at both ends of the second semiconductor layer, forming dielectric spacers in the recesses, forming a blocking structure on both ends of the first semiconductor layer, wherein the blocking structure covers an interface defined by the sacrificial gate dielectric and the sacrificial gate electrode layer, forming source / drain components on both sides of the sacrificial gate structure, the source / drain components being in contact with the blocking structure, removing the sacrificial gate structure and the second semiconductor layer to expose a plurality of portions of the first semiconductor layer and the blocking structure, and forming a gate electrode layer to surround the exposed portion of the first semiconductor layer.

[0187] In some embodiments, the blocking structure is a boron-doped semiconductor material or a compound containing boron and a semiconductor material. In some embodiments, an etching process is performed on the first semiconductor layer and the second semiconductor layer to remove a plurality of edge portions of the second semiconductor layer at a first lateral distance and to remove a plurality of edge portions of the first semiconductor layer at a second lateral distance less than the first lateral distance.

[0188] The above outlines the features of several embodiments so that those skilled in the art to which the present invention pertains can better understand the viewpoints of the embodiments of the present invention. Those skilled in the art to which the present invention pertains should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art to which the present invention pertains should also understand that such equivalent structures do not depart from the spirit and scope of the present invention and can be changed, substituted, and replaced in various ways without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be defined by the appended claims.

Claims

1. A semiconductor device structure, characterized in that: include: a first source / drain component and a second source / drain component; a plurality of semiconductor layers vertically stacked and disposed between the first source / drain component and the second source / drain component; a gate electrode layer surrounding a portion of each semiconductor layer; as well as an interface layer disposed between the gate electrode layer and one of the plurality of semiconductor layers, A topmost semiconductor layer of the plurality of semiconductor layers has a first length, and the interface layer has a second length greater than the first length.

2. The semiconductor device structure according to claim 1, wherein: Also includes: A barrier structure is in contact with a side wall of each semiconductor layer.

3. The semiconductor device structure according to claim 2, wherein: Also includes: A gate spacer is in contact with the interface layer and the blocking structure.

4. The semiconductor device structure according to claim 2 or 3, characterized in that: A portion of the blocking structure contacts the first source / drain feature or the second source / drain feature.

5. The semiconductor device structure according to claim 3, wherein: The blocking structure extends above an interface defined by the interfacial layer and the gate spacer.

6. A semiconductor device structure, characterized in that: include: A plurality of semiconductor layers are stacked vertically and in parallel; a gate electrode layer completely surrounding a portion of each semiconductor layer; an interface layer disposed between the gate electrode layer and a topmost semiconductor layer of the plurality of semiconductor layers; a gate spacer disposed adjacent to the gate electrode layer and in contact with the interface layer; as well as A blocking structure is in contact with a side wall of each semiconductor layer, wherein the blocking structure covers an interface defined by the interface layer and the gate spacer.

7. The semiconductor device structure according to claim 6, wherein: The interface layer contacting the top semiconductor layer has a first length, and the top semiconductor layer of the plurality of semiconductor layers has a second length smaller than the first length.

8. The semiconductor device structure according to claim 6, wherein: The blocking structure has a diamond shape in a cross-sectional view.

9. The semiconductor device structure according to claim 6, wherein: The blocking structure is a faceted structure having a plane from the {111} plane family, the {100} plane family, the {311} plane family, or the {911} plane family.

10. The semiconductor device structure according to claim 6, wherein: A top surface of the gate electrode layer is lower than a top surface of the gate spacer.

Images