Semiconductor structure

Abstract

An example semiconductor structure includes a bulk substrate and a silicon-on-insulator substrate. The bulk substrate has a top surface, and the silicon-on-insulator substrate is fused into the bulk substrate. The silicon-on-insulating-layer substrate further comprises a heavily doped layer, an insulating layer and an active substrate. The insulating layer is disposed on the heavily doped layer and surrounded by the heavily doped layer, and the active substrate is disposed on the insulating layer and surrounded by the insulating layer. The semiconductor structure also includes one or more semiconductor devices disposed in the active substrate, a peripheral heavily doped region connected to the heavily doped layer, and a discharge metal structure electrically interconnecting the one or more semiconductor devices and the peripheral heavily doped region.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a semiconductor structure. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Advancements in integrated circuit materials and design have produced several generations of integrated circuits, with each generation having smaller and more complex circuits than the previous one. However, these advancements have increased the complexity of integrated circuit processing and manufacturing, and to achieve these advancements, similar developments in integrated circuit processing and manufacturing are required. In the mainstream path of integrated circuit evolution, the functional density (i.e., the number of interconnect devices per unit area of the wafer) generally increases, while the geometric size (i.e., the smallest component that can be fabricated by the process) decreases. Therefore, there is a continuing need to develop integrated circuits with low power consumption, better performance, smaller wafer area, and lower cost. Summary of the Utility Model

[0003] One aspect of the present disclosure is a semiconductor structure. In an example, the semiconductor structure includes a bulk substrate, a silicon-on-insulator substrate, one or more semiconductor devices, a peripheral heavily doped region, and a discharge metal structure. The bulk substrate has a top surface. The silicon-on-insulator substrate is incorporated into the bulk substrate, and the silicon-on-insulator substrate further has a heavily doped layer, an insulating layer, and an active substrate. The heavily doped layer includes a bottom and sides. The bottom of the heavily doped layer extends horizontally, and the sides of the heavily doped layer extend peripherally from a top end portion in a downward direction to a bottom end portion, where the top end portion is connected to the top surface of the bulk substrate, and the bottom end portion is connected to the bottom of the heavily doped layer. The insulating layer is disposed on the heavily doped layer and surrounded by the heavily doped layer. The active substrate is disposed on the insulating layer and surrounded by the insulating layer, where the active substrate is isolated by the insulating layer and the heavily doped layer and has a top surface coplanar with the top surface of the bulk substrate. One or more semiconductor devices are disposed in the active substrate. The peripheral heavily doped region is connected to the top end portion of the side of the heavily doped layer and extends horizontally from the top end portion of the side of the heavily doped layer. The discharge metal structure electrically interconnects the one or more semiconductor devices and the peripheral heavily doped region.

[0004] One aspect of the present disclosure is a semiconductor structure. In another example, the semiconductor structure includes a bulk substrate, a silicon-on-insulator substrate, one or more semiconductor devices, one or more antenna diodes, and a first discharge metal structure. The bulk substrate has a top surface. The silicon-on-insulator substrate is integrated into the bulk substrate, and the silicon-on-insulator substrate further has a heavily doped layer, an insulating layer, and an active substrate. The heavily doped layer includes a bottom and sides. The bottom of the heavily doped layer extends horizontally, and the sides of the heavily doped layer extend peripherally from a top end portion in a downward direction to a bottom end portion, where the top end portion is connected to the top surface of the bulk substrate, and the bottom end portion is connected to the bottom of the heavily doped layer. The insulating layer is disposed on the heavily doped layer and is surrounded by the heavily doped layer. The active substrate is disposed on the insulating layer and is surrounded by the insulating layer, wherein the active substrate is isolated by the insulating layer and the heavily doped layer and has a top surface coplanar with the top surface of the bulk substrate. One or more semiconductor devices are disposed in the active substrate. One or more antenna diodes are integrated into the bulk substrate and are adjacent to the silicon-on-insulator substrate. The first discharge metal structure electrically interconnects the one or more semiconductor devices and the one or more antenna diodes.

[0005] One aspect of the present disclosure is a semiconductor structure. In another example, a semiconductor structure includes a bulk substrate, a silicon-on-insulator substrate, one or more semiconductor devices, a doped well, and a first discharge metal structure. The bulk substrate has a top surface. The silicon-on-insulator substrate is integrated into the bulk substrate, and the silicon-on-insulator substrate further has a heavily doped layer, an insulating layer, and an active substrate. The heavily doped layer includes a bottom and sides. The bottom of the heavily doped layer extends horizontally, and the sides of the heavily doped layer extend peripherally from a top end portion in a downward direction to a bottom end portion, where the top end portion is connected to the top surface of the bulk substrate, and the bottom end portion is connected to the bottom of the heavily doped layer. The insulating layer is disposed on the heavily doped layer and is surrounded by the heavily doped layer. The active substrate is disposed on the insulating layer and is surrounded by the insulating layer, wherein the active substrate is isolated by the insulating layer and the heavily doped layer and has a top surface coplanar with the top surface of the bulk substrate. One or more semiconductor devices are disposed in the active substrate. The doped well is disposed in the bulk substrate. The first discharge metal structure electrically interconnects the one or more semiconductor devices and the doped well. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] As will be best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A FIG. is a schematic top view of a layout of an exemplary semiconductor structure in accordance with some embodiments;

[0008] Figure 1B In accordance with some embodiments, FIG. shows Figure 1ASchematic diagram of a cross-sectional view of an exemplary semiconductor structure;

[0009] Figure 2A Schematic diagram of a top view of a layout of another exemplary semiconductor structure according to some embodiments;

[0010] Figure 2B According to some embodiments, depicts Figure 2A Schematic diagram of a cross-sectional view of the exemplary semiconductor structure in;

[0011] Figure 2C According to some embodiments, depicts Figure 2A Top view of another layout of the exemplary semiconductor structure of;

[0012] Figure 2D Schematic diagram of a top view of a layout of another exemplary semiconductor structure according to some embodiments;

[0013] Figure 3 Schematic diagram of a top view of a layout of yet another exemplary semiconductor structure according to some embodiments;

[0014] Figure 4 Flowchart of an exemplary method for manufacturing a semiconductor structure according to some embodiments;

[0015] Figure 5 According to some embodiments, depicts Figure 4 Flowchart of an exemplary operation shown in;

[0016] Figures 6A to 6N Using Figure 4 And Figure 5 Cross-sectional views of an exemplary semiconductor structure at various stages manufactured by the exemplary method shown in.

[0017]

Symbol Explanation

[0018] 100: Semiconductor structure

[0019] 101: Large substrate

[0020] 102a, 102b: SOI structure

[0021] 103: Top surface

[0022] 108: STI structure

[0023] 111~114: Dielectric layer

[0024] 115: MLI structure

[0025] 120: Heavily doped layer

[0026] 121: Bottom

[0027] 122: Side

[0028] 123: Proximal side wall

[0029] 124: Distal side wall

[0030] 125a, 125b, 125c: Peripheral heavily doped region

[0031] 126: Top surface

[0032] 127: Bottom surface

[0033] 128: Top surface

[0034] 129: Bottom surface

[0035] 130: Insulating layer

[0036] 131: Bottom

[0037] 132: Side

[0038] 133: Top surface

[0039] 138: Top end portion

[0040] 139: Bottom end portion

[0041] 140: Active substrate

[0042] 141: Bottom surface

[0043] 142: Side wall

[0044] 143: Top surface

[0045] 145a, 145b, 145c: Transistor

[0046] 146: S / D region

[0047] 147: Gate structure

[0048] 150: Device region

[0049] 160a, 160b, 160c, 160d: Discharge metal structure

[0050] 161: Metal wire

[0051] 162: Via contact

[0052] 190: Surface

[0053] 200: Semiconductor structure

[0054] 200': Semiconductor structure

[0055] 202: Antenna diode

[0056] 204: Heavily doped region

[0057] 206: Doped well

[0058] 210: Antenna metal structure

[0059] 212: Antenna metal layer

[0060] 214: Via contact

[0061] 220: Electrical wiring structure

[0062] 222: Interconnect metal

[0063] 290 - 292: Surface

[0064] 300: Semiconductor structure

[0065] 302: Antenna metal wire

[0066] 400: Method

[0067] 402 - 412: Operations

[0068] 502 - 520: Operations

[0069] 600: Semiconductor structure

[0070] 602: Mask pattern

[0071] 604: Groove

[0072] 606: Bottom

[0073] 608: Sidewall

[0074] 610: Silicon epitaxial layer

[0075] 620: Oxygen implantation layer

[0076] 621: Bottom

[0077] 622: Side

[0078] 630: Silicon epitaxial layer

[0079] 631: Bottom

[0080] 632: Side

[0081] 640: Silicon epitaxial layer

[0082] D 1 : Distance

[0083] D 2 : Distance

[0084] M0 - M3: Layers

[0085] T 1 ~T 4 : Thickness

[0086] α: Angle

[0087] β: Angle

[0088] γ: Angle Detailed implementation manners

[0089] The following disclosure provides many different embodiments or examples for implementing different features of the described subject matter. Specific examples of components and configurations are described below to simplify this specification. Of course, these are merely examples and not restrictive. For example, in the subsequent description, forming the first feature above or on top of the second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature, such that the first feature and the second feature may not be in direct contact. Additionally, this disclosure may reuse reference numerals and / or reference letters in multiple examples. Such repetition is for the purpose of simplicity and clarity, and does not itself indicate a relationship between the multiple embodiments and / or configurations being discussed.

[0090] Spatial relative terms such as "under", "below", "bottom", "on", "top", etc. may be used herein for the purpose of facilitating description to describe the relationship between one element or feature and another element or feature as shown in the drawings. Spatial relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation shown in the drawings. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0091] In addition, the source / drain regions (which may also be referred to as S / D regions and may be used interchangeably) may refer to the source or the drain separately or collectively depending on the context. For example, a device may include a first source / drain region, a second source / drain region, and other components. The first source / drain region may be a source region, and the second source / drain region may be a drain region, or vice versa. Those skilled in the art will recognize that there are many variations, modifications, and alternatives.

[0092] Some embodiments of this disclosure are described. Additional operations may be added before, during, and / or after each of the stages described in these embodiments. In different embodiments, some stages may be replaced or removed. In different embodiments, some features may be replaced or removed, and additional features may be added. Even though some embodiments discuss operations being performed in a specific order, these operations may be performed in another logical order.

[0093] Overview

[0094] Metal induced charge damage, also known as antenna effect, refers to the phenomenon that charges and ions can be trapped at the interface within the semiconductor lattice or semiconductor device, resulting in the introduction of unwanted energy levels in the energy gap of the material. These energy levels can trap and hold carriers (electrons and holes), affecting the electrical characteristics of semiconductor devices, such as carrier mobility, threshold voltage, and overall device performance. This phenomenon becomes more pronounced as the IC size shrinks and semiconductor devices become smaller and more densely packed. Metal induced charge damage can cause signal attenuation, physical damage, interference between adjacent metal lines, increased power consumption, and potential IC reliability issues, with physical damage such as metal migration, hole formation, or interface degradation.

[0095] For example, in the manufacture of ICs using metal oxide semiconductor (MOS) technology, processes involving charged ions are commonly used, such as plasma etching processes and ion implantation processes. For instance, during a plasma etching process used to form a gate polysilicon pattern or an interconnect metal line pattern, static charges may accumulate on the floating gate polycrystalline electrode. The voltage thus generated on the gate polycrystalline electrode may be large enough to cause charges to flow into the gate oxide and be trapped within the gate oxide or to flow through the gate oxide. These charges can severely weaken the strength of the gate oxide and cause MOS device reliability failures. Each polycrystalline gate will accumulate electrostatic charges proportional to its area. A small gate oxide connected to a large polycrystalline geometry or a large interconnect metal geometry can accumulate a disproportionate amount of charge and may suffer severe damage. The strength of the antenna effect is proportional to the ratio of the area of the exposed conductor to the area of the gate oxide.

[0096] Silicon on insulator (SOI) substrates have become an alternative to bulk semiconductor substrates. An SOI substrate generally comprises a bulk substrate (processing substrate), an insulating layer covering the bulk substrate, and an active substrate (device substrate) covering the insulating layer. SOI substrates offer reduced parasitic capacitance, reduced leakage current, reduced latch-up effect, improved semiconductor device performance (i.e., lower power consumption and higher switching speed), and other advantages.

[0097] For conventional SOI-based integrated circuits, in order to release excess charge and mitigate antenna effects during the manufacturing process, an electrical path is formed from the active substrate through the insulating layer to the bulk substrate. Since the insulating layer completely separates the active substrate and the bulk substrate on the horizontal plane, a hole must be formed in the insulating layer and filled with a conductive material. The effectiveness of charge release is limited and compromised because the area of the conductive structures fabricated on the SOI substrate is not large enough. In addition, in SOI-based integrated circuits, lateral isolation is based on oxides using chemical vapor deposition (CVD) technology, and the quality of CVD oxides is not as good as that of thermal oxides. Moreover, the SOI manufacturing process is more complex and costly than the bulk silicon manufacturing process.

[0098] The present disclosure provides techniques for addressing the aforementioned shortcomings regarding antenna effect protection in SOI-based integrated circuits. According to some embodiments, the SOI structure has a three-dimensional (3D) sandwich-like configuration and includes a heavily doped layer, an insulating layer disposed on and surrounded by the heavily doped layer, and active substrates individually and separately disposed on and surrounded by the insulating layer. The insulating layer buried in the SOI structure does not extend over the entire horizontal plane but has a folded configuration that laterally surrounds the active substrates to physically and electrically isolate the active substrates from the bulk substrate. A first discharge metal structure is used to electrically connect semiconductor devices formed in the active substrates and the bulk substrate, such that an electrical path is formed to release or dissipate excess charge generated and accumulated in the active substrates through the first discharge metal structure to the bulk substrate, obviating the need to form a hole through the insulating layer for discharging and preventing damage to the SOI structure. In addition, the insulating layer can be made of thermal oxide by a thermal process and thus has better quality than the insulating layer based on CVD oxide in conventional SOI structures.

[0099] Another aspect of the present disclosure relates to an antenna effect prevention device (also referred to as an "antenna diode"). According to some embodiments, the antenna effect prevention device is formed and arranged in proximity to the SOI substrate. The antenna effect prevention device can be an antenna diode integrated into the bulk substrate. A second discharge metal structure is used to interconnect the antenna effect prevention device and the semiconductor formed in the active substrate in the SOI structure. The second discharge metal structure can provide an additional electrical path to facilitate or enhance the release of excess charge generated in a multi-layer interconnect (MLI) structure (hereinafter referred to as the "MLI structure") during the back-end-of-line (BEOL) process.

[0100] Exemplary semiconductor and SOI structures

[0101] According to some embodiments, Figure 1A and Figure 1B illustrates an exemplary semiconductor structure 100. Figure 1AFIG. 0 is a schematic top view of an exemplary semiconductor structure 100 from a surface 190 (i.e., the interface between the M1 layer and the M2 layer in the MLI structure 115). For simplicity, some components, such as dielectric layers 112 and 111, are not shown in Figure 1A to depict other components in the semiconductor structure 100. Figure 1B FIG. 4 is a cross-sectional view of the semiconductor structure 100 along a virtual line A - A' shown in Figure 1A .

[0102] In the depicted example, the semiconductor structure 100 includes a bulk substrate 101, multiple SOI structures 102a, 102b, 102c (collectively referred to as SOI structures 102), multiple IC devices (or semiconductor devices, such as transistors) 145a, 145b, and 145c (collectively referred to as IC devices 145), multiple discharge metal structures 160a, 160b, and 160c (collectively referred to as discharge metal structures 160), and other components. Additional components, such as multiple device regions 150, multiple shallow trench isolation (STI) feature structures 108, etc., may also be included in the semiconductor structure 100.

[0103] The bulk substrate 101 can be a semiconductor substrate, such as a (single crystal) silicon substrate. In some embodiments, the bulk substrate 101 is a doped substrate with a dopant of a semiconductor type. For example, the bulk substrate 101 can be a P-type substrate or an N-type substrate. The bulk substrate 101 can have a first doping concentration (or doping amount), e.g., from 10 13 to 10 17 doping atoms per square centimeter, from 10 13 to 10 16 doping atoms per square centimeter, or from 10 13 to 10 15 doping atoms per square centimeter. It should be noted that other possible values of the first doping concentration are also within the scope of this disclosure. The bulk substrate 101 has a top surface 103.

[0104] Each SOI structure 102 is fused with the bulk substrate 101 and has a 3D sandwich configuration. In Figure 1B the example, the SOI structures 102 (i.e., SOI structures 102a, 102b, and 102c) may respectively include corresponding portions of the bulk substrate 101 on which the SOI structures 102 are constructed, a heavily doped layer 120, an insulating layer 130 disposed on and surrounded by the heavily doped layer 120, an active substrate 140 disposed on and surrounded by the insulating layer 130, and other components.

[0105] The heavily doped layer 120 may include a relatively high concentration of p-type dopants or n-type dopants. In some embodiments, the heavily doped layer 120 has the same type of dopants as the bulk substrate 101. In one example, both the heavily doped layer 120 and the bulk substrate 101 are doped with p-type dopants. In another example, both the heavily doped layer 120 and the bulk substrate 101 are doped with n-type dopants. In some embodiments, the heavily doped layer 120 has a doping concentration that is higher than or substantially higher than that of the bulk substrate 101. In some embodiments, the doping concentration of the heavily doped layer 120 is at least one order of magnitude (i.e., 10 times) higher than that of the bulk substrate. In some embodiments, the heavily doped layer 120 has a second doping concentration, e.g., from 10 14 to 10 20 doping atoms per square centimeter, or from 10 15 to 10 18 doping atoms per square centimeter. It should be noted that the second doping concentration is also within the scope of the present disclosure.

[0106] The heavily doped layer 120 may provide at least the following advantages. During the charge release process, the heavily doped layer 120 may provide a low-resistance path for current. The high doping concentration of the heavily doped layer can facilitate the formation of low-resistance contacts with other components in the semiconductor structure 100 to improve the overall device performance. The heavily doped layer 120 may also provide a layer of barrier / isolation / protection outside the insulating layer 130 to prevent excessive leakage current and improve the isolation of the IC device 145 formed within the SOI structure 102.

[0107] The heavily doped layer 120 includes a bottom 121 and a side portion 122. The bottom 121 is below the side portion 122 and extends along a horizontal plane (i.e., the X-Y plane). The bottom 121 extends vertically from the top surface 128 to the bottom surface 127. The side portion 122 extends along the perimeter from the proximal sidewall 123 (i.e., adjacent to the active substrate 140) to the distal sidewall 124 (i.e., away from the active substrate 140) and further includes a top end portion 138 and a bottom end portion 139. The bottom end portion 139 is connected to the bottom 121 along the perimeter such that the proximal sidewall 123 is connected to the top surface 128 and the distal sidewall 124 is connected to the bottom surface 127. The top end portion 138 is connected to the top surface 103 of the bulk substrate 101.

[0108] In some embodiments, the heavily doped layer 120 further includes a top horizontal extension portion 125 that extends horizontally from the top end portion 138. The top horizontal extension portion 125 can be regarded as the top peripheral portion of the heavily doped layer 120. The peripheral heavily doped region 125 of the heavily doped layer 120 can also be regarded as the peripheral extension of the heavily doped layer 120 on the top surface 103 of the bulk substrate 101. For convenience, the top horizontal extension portion 125 is also referred to as the "peripheral heavily doped region 125", and the two names can be used interchangeably. The peripheral heavily doped region 125 extends vertically from the top surface 126 to the bottom surface 127. The top surface 126 is connected to the proximal sidewall 123 of the side portion 122 and is coplanar with the top surface 103 of the bulk substrate 101. The bottom surface 129 is connected to the distal sidewall 124 of the side portion 122. In some embodiments, the peripheral heavily doped region 125 between two adjacent SOI substrates (i.e., SOI substrates 102a and 102b), denoted as the peripheral heavily doped region 125b, can interconnect the heavily doped layers 120 of the two adjacent SOI substrates. In some embodiments, the heavily doped layer 120 surrounds and partially encloses the insulating layer 130 and the active substrate 140.

[0109] In some embodiments, the heavily doped layer 120 has a substantially uniform doping concentration distribution. In other embodiments, the heavily doped layer has a doping concentration gradient. For example, the doping concentration gradually decreases from the top surface 128 to the bottom surface 127 in the bottom portion 121. Similarly, the doping concentration gradually decreases from the proximal sidewall 123 to the distal sidewall 124 in the side portion 122. Similarly, the peripheral heavily doped region 125 can also have a doping concentration gradient. For example, the doping concentration can gradually decrease from the top surface 126 to the bottom surface 129 in the peripheral heavily doped region 125.

[0110] Similar to the heavily doped layer 120, the insulating layer 130 includes a bottom portion 131 and side portions 132 connected to the bottom portion 131 along the periphery. The bottom portion 131 is disposed on the bottom portion 121 of the heavily doped layer 120, and the side surfaces 132 are disposed on the side portion 122 (i.e., the proximal sidewall 123) of the heavily doped layer 120. The side portion 132 has a top surface 133, and the top surface 133 is coplanar with the top surface 126 of the heavily doped layer 120 and the top surface 103 of the bulk substrate 101. The insulating layer 130 can be composed of an oxide or a nitride, such as silicon oxide (also known as buried oxide, or BOX), silicon nitride, silicon oxynitride, high-k materials, such as hafnium oxide (HfO 2 )), zirconium oxide (ZrO 2 ), tantalum oxide (Ta 2 O 5 ) or a combination thereof.

[0111] In some embodiments, the insulating layer 130 is composed of thermal silicon oxide. Thermal silicon oxide is usually formed by exposing silicon to high temperature in an oxygen-rich environment. As mentioned above, conventional SOI substrates usually have an insulating layer composed of CVD silicon oxide. Compared with the CVD silicon oxide of the conventional SOI substrate, the thermal silicon oxide of the insulating layer has better electrical properties, higher quality interfaces, lower interface defect density, minimum charge trapping, higher uniformity and higher compatibility with other components, and therefore has better cost performance and manufacturability.

[0112] The active substrate 140 is disposed on the insulating layer 130 and is surrounded by the insulating layer 130. The active substrate 120 extends from a top surface 143 to a bottom surface 141 and has a sidewall 142 connected to the top surface 143 and the bottom surface 141 along the periphery. The top surface 143 is coplanar with the top surface 133 of the insulating layer 130, the top surface 126 of the heavily doped layer 120, and the top surface 103 of the bulk substrate 101. Similar to the bulk substrate, the active substrate 140 may be a semiconductor substrate such as a silicon substrate or a doped semiconductor substrate.

[0113] In the depicted example, the active substrate 140 forms an angle (α) between the sidewall 142 and the bottom surface 141, the insulating layer 130 forms an angle (β) between the side 132 and the bottom 131, and the heavily doped layer 120 forms an angle (γ) between the side 122 and the bottom 121 (or between the proximal sidewall 123 and the top surface 128, or between the distal sidewall 124 and the bottom surface 127). In some embodiments, the angles α, β, and γ are the same or substantially the same. In some embodiments, each of the angles α, β, and γ may be at least 85 degrees, at least 90 degrees, at least 100 degrees, at least 110 degrees, or at least 120 degrees. It should be noted that other possible values ​​of the angles α, β, and γ are also within the scope of the present disclosure.

[0114] The heavily doped layer 120 may have a thickness (T 1 ), which is obtained by measuring the vertical distance between the top surface 128 and the bottom surface 127 of the bottom 121, or the distance between the proximal sidewall 123 and the distal sidewall 124 of the side 122. Similarly, the peripheral heavily doped region 125 has a thickness (T 1 ), which is obtained by measuring the vertical distance between the top surface 126 and the bottom surface 129. The insulating layer 130 has a thickness (T 2 ), which is obtained by measuring the distance between the bottom surface 141 of the active substrate 140 and the top surface 128 of the heavily doped layer 120. The active substrate 140 has a thickness (T 3 ), which is obtained by measuring the distance between the top surface 143 and the bottom surface 141. The SOI structure 102 has a thickness (T 4 ), by measuring T 1 , T 2 and T 3is obtained by the sum. In some embodiments, T 1 is from 0.01 micrometers to 3 micrometers, from 0.05 micrometers to 2 micrometers, or from 0.1 micrometers to 1 micrometer. In some embodiments, T 2 is from 0.01 micrometers to 3 micrometers, from 0.05 micrometers to 2 micrometers, or from 0.1 micrometers to 1 micrometer. In some embodiments, T 3 is from 0.5 micrometers to 400 micrometers, from 1 micrometers to 200 micrometers, from 1 micrometers to 100 micrometers, or from 1 micrometers to 50 micrometers. In some embodiments, T 4 is from 0.5 micrometers to 400 micrometers, from 1 micrometers to 200 micrometers, from 1 micrometers to 100 micrometers, or from 1 micrometers to 50 micrometers. It should be noted that other values of T 1 、T 2 、T 3 and T 4 are also within the scope of this disclosure.

[0115] The IC device 145 formed in the active substrate 140 may include any passive or active semiconductor device, such as transistors, diodes, capacitors, resistors. Non-limiting examples of transistors include bipolar junction transistors (BJTs), field effect transistors (FETs) such as metal-oxide-semiconductor field effect transistors (MOSFETs) and junction field effect transistors (JFETs). For example, the IC device 145 generated in the SOI substrate 102a may include a first transistor 145a and a second transistor 145b. The transistors 145a and 145b may each include two S / D regions 146 and a gate structure 147. The first transistor 145a and the second transistor 145b may be separated and isolated by the STI structure 108 formed in the active substrate 140. The transistor 145c is formed in the active substrate 140 of the SOI structure 102b.

[0116] The MLI structure 115 is disposed on the top surface 103 of the bulk substrate 101, the top surface 143 of the active substrate 140, the top surface 133 of the insulating layer 130, and the top surface 126 of the heavily doped layer 120. The MLI structure 115 generally provides electrical wiring and distribution for the IC device 145 included in the SOI structure 102. For example, the MLI structure 115 can be used to electrically connect the IC device 145 (e.g., the gate structure 147 of the transistor 145a or the S / D region 146 of the transistor 145c) to another component inside or outside the semiconductor structure 100.

[0117] An MLI structure is a set of metallization layers (sometimes also referred to as "metal layers" or "M layers") added to one side of a substrate. The metallization layers are patterned to form a complex network of interconnects that connect different components together. Each metallization layer is formed in a corresponding dielectric layer and includes a plurality of horizontal metal features (i.e., metal lines) and vertical metal features (i.e., via contacts) formed in the corresponding dielectric layer. In the depicted example, the MLI structure 115 includes a base metallization layer (M0 layer), an M1 layer, an M2 layer, and an M3 layer. Additional M layers (e.g., M4 layer, M5 layer, etc.) can be formed sequentially on top of the M3 layer. The M0 layer is formed on the top surface 103 of the bulk substrate 101 and includes a dielectric layer 111. The gate structures 147 of the transistors 145a, 145b, and 145c and the metal components of other IC devices can be formed in the dielectric layer 111. The M1, M2, and M3 layers respectively include dielectric layers 112, 113, and 114, and a plurality of metal lines and via contacts can be formed in any of the M1, M2, and M3 layers to form the desired wiring.

[0118] A discharge metal structure 160 (e.g., 160a, 160b, and 160c) can be formed in the M1 layer or the M0 layer of the MLI structure 115. In some embodiments, the discharge metal structure 160 includes a horizontal metal line 161 and a plurality of vertical via contacts 162. The metal line 161 extends horizontally in the M1 layer, and the via contacts 162 are disposed in the M1 layer and / or the M0 layer and extend vertically. One of the via contacts 162 electrically interconnects the IC device 145 (e.g., the gate structure 147 or the S / D structure 146) and the metal line 161, and the other of the via contacts 162 electrically interconnects the peripheral heavily doped region 125. Thus, the discharge metal structure 160 provides an electrical path through which the charge accumulated in the IC device 145 and the active substrate 140 can be released or dissipated to the bulk substrate 101. Since the bulk substrate can serve as a ground plane and the peripheral heavily doped region 125 of the heavily doped layer 120 further reduces the resistance, the charge accumulated in the active substrate 140 can be effectively released by the electrical path provided by the discharge metal structure 160 without the need to form a through-insulating-layer via that risks damaging the SOI structure 102. In addition, the discharge metal structure 160 can be easily formed when the MLI structure 115 of the BEOL is formed without the need for an additional mask or an additional process, thus having both manufacturability and cost efficiency.

[0119] In the depicted example, a plurality of discharge metal structures are formed. A discharge metal structure 160a interconnects the first transistor 145a and the peripheral heavily doped region 125a surrounding the SOI structure 102a. A discharge metal structure 160b interconnects the first transistor 145b and the peripheral heavily doped region 125b between the SOI structures 102a and 102b. A discharge metal structure 160c interconnects the first transistor 145c and the peripheral heavily doped region 125c between the SOI structure 102b and the device region 150. It is understood that additional discharge metal structures may be formed, and the total number of discharge metal structures may be determined based on the number of IC devices in each SOI structure 102 and other design factors.

[0120] At least because of the partially enclosed and discrete nature of SOI structure 102, SOI structure 102 can be formed in selected areas on bulk substrate 101 (i.e., not the entire area of ​​the bulk substrate). For example, SOI structure 102 can be formed in selected areas that contain high priority IC devices (e.g., Figure 1A ), and other IC devices may be formed outside the SOI structure 102 (e.g., Figure 1A The discharge metal structure 160 can be used to protect these high priority IC devices from antenna effect. Therefore, the SOI structure according to the present disclosure provides more design flexibility than the traditional SOI substrate with a planar insulating layer.

[0121] Figures 2A to 2C According to some implementations, another semiconductor structure 200 is depicted. Figure 2A FIG. 2 is a schematic diagram illustrating a layout of an exemplary semiconductor structure 200 from a top view of a surface 290 (ie, the interface between the M1 layer and the M2 layer of the MLI structure 115 ). Figure 2B An example semiconductor device 200 is depicted in Figure 2A Schematic diagram of a cross-section view along the imaginary line AA'. Figure 2C A schematic diagram depicting a layout of the exemplary semiconductor structure 200 from a top view of a surface 291 or 292 (ie, the interface between the M2 layer and the M3 layer or the top surface of the M3 layer of the MLI structure 115 ).

[0122] For the sake of simplicity, some components, such as dielectric layers 114, 113, 112 and / or 111, are not shown. Figure 2A and Figure 2C , to depict other components of the semiconductor structure 200. The semiconductor structure 200 is a close variation of the semiconductor structure 100, and the semiconductor structure 200 may include any components of the semiconductor structure 100. Unless otherwise specified, in the semiconductor device 200, multiple forms of similar components will not be repeated here.

[0123] Similar to semiconductor device 100, semiconductor device 200 includes a bulk substrate 101, a plurality of SOI structures 102a and 102b, a plurality of IC devices 145a, 145b, and 145c, an MLI structure 115, a plurality of discharge metal structures 160a, 160b, and 160c, and other components. Additional components, such as a multi-device region 150, a plurality of STI structures 108, etc., may also be included in semiconductor structure 200. For example, device region 150 is adjacent to SOI structure 102b and is isolated from SOI structure 102b by STI structure 108. Peripheral heavily doped region 125c extends horizontally between SOI structure 102b and STI structure 108.

[0124] As Figure 2B shown, semiconductor structure 200 also includes one or more antenna diodes 202. Antenna diodes 202 are configured to reduce or avoid antenna effects and further release or dissipate excess charge accumulated in the IC devices 145 or other functional components in SOI structures 102, device region 150, or MLI structure 115. It should be understood that the antenna diodes are just an example of an antenna effect protection device, and other types of devices or structures may also be used for antenna effect protection according to the present disclosure.

[0125] In some embodiments, semiconductor structure 102 includes a first antenna diode 202a and a second antenna diode 202b (collectively referred to as antenna diodes 202) formed in bulk substrate 101. First antenna diode 202a is adjacent to SOI structure 102a (i.e., adjacent to peripheral heavily doped region 125a of the heavily doped layer 120 of SOI structure 102a). Second antenna diode 202b is located beside first antenna diode 202a and away from SOI structure 102a. Semiconductor structure 200 may include STI structure 108, and STI structure 108 is used to isolate first antenna diode 202a from second antenna diode 202b. It should be understood that the number and location of antenna diodes 202 can be changed according to design requirements. For example, the pattern of antenna diodes 202 (such as rows, columns, or arrays) may be formed in the region adjacent to one of the SOI substrates 102. As another example, antenna diodes 202 may be arranged around or partially around the perimeter of SOI structure 102. Adjacent antenna diodes 202 (i.e., first antenna diode 202a and second antenna diode 202b) may be electrically interconnected.

[0126] Each antenna diode 202 also includes a doped well 206 buried in a bulk substrate 101 and a heavily doped region 204 disposed on the doped well 206. In some embodiments, the doped well 206 and the heavily doped region 204 include a first dopant of a first semiconductor type, while the bulk substrate 101 includes a second dopant of a second semiconductor type. The second semiconductor type is opposite to the first semiconductor type. Thus, the bulk substrate 101, the heavily doped region 204, and the doped well disposed therebetween form the antenna diode 202. In some embodiments, the bulk substrate 101 is a P-type substrate and includes P-type dopants, while the doped well 206 and the heavily doped region 204 of the antenna diode 202 include N-type dopants. In some embodiments, the bulk substrate 101 is an N-type substrate and includes N-type dopants, while the doped well 206 and the heavily doped region 204 of the antenna diode 202 include P-type dopants. In some embodiments, the heavily doped region 204 has a doping concentration higher than or approximately higher than that of the doped well 206 and the bulk substrate 101. In some embodiments, the doped well 206 has a doping concentration of from 10 13 to 10 17 dopant atoms per square centimeter. In some embodiments, the heavily doped region 204 has from 10 14 to 10 20 dopant atoms per square centimeter, or from 10 15 to 10 18 dopant atoms per square centimeter. It should be noted that other possible values of the doping concentration of the heavily doped layer 204 are also within the scope of this disclosure. The antenna diode 202 is configured to have a low breakdown voltage to initiate and conduct current when the cross-voltage exceeds a specific threshold, and to provide a discharge path for excess charge.

[0127] As Figure 2B shown, at least one discharge metal structure 160 (i.e., 160d) will interconnect the first transistor 145a and the first antenna diode 202a included in the SOI substrate 102a. For example, the via contact 162 of the discharge metal structure 160d interconnects the gate structure 147 of the transistor 145a and the metal line 161 of the first antenna diode 202a, and another via contact 162 of the discharge metal structure 160d interconnects the heavily doped region 204 and the metal line 161 of the first antenna diode 202a. Accordingly, a path is formed to electrically connect the active substrate 140 of the SOI substrate 102a to the bulk substrate 101 without using a through-insulating-layer via, thus being more cost-effective and more manufacturing-friendly. The excess charge accumulated in the first transistor 145a can be discharged through the electrical path corresponding to the discharge metal structure 160d and the antenna diode 202a.

[0128] In some embodiments, the semiconductor structure 200 further includes an antenna metal structure 210, and the antenna metal structure 210 is connected to at least one antenna diode 202. The antenna metal structure 210 is configured to electrically connect the antenna diode 202 to other components within or on the MLI structure 115. As Figure 2B shown, the antenna metal structure 210 may include one or more antenna metal layers 212 and a plurality of via contacts 214. The antenna metal layers 212 extend horizontally in one or more M-layers (such as M1 layer, M2 layer, M3 layer, etc.), and the plurality of via contacts 214 interconnect the antenna metal layers 212 in the plurality of M-layers. The antenna metal layers 212 of the antenna metal structure 210 can be fabricated in the same process as forming the MLI structure 115. The antenna metal structure 210 provides a conduction path for releasing the excess charge accumulated in each M-layer during the manufacturing process and operation of the semiconductor structure 200. In addition, the antenna metal structure 210 can be electrically connected to the discharge metal structures 160 (such as discharge metal structures 160a, 160b, and 160c) to provide a discharge path for releasing the charge in the M-layers of the MLI structure to the bulk substrate 101 via the antenna diode 202 and the peripheral heavily doped layer 125.

[0129] As Figure 2C shown, the antenna metal layers 212 of the antenna metal structure 210 can be in the form of a continuous metal layer covering a selected area of the bulk substrate 101. The antenna metal layer 212 can be disposed in the M1 layer and formed in the same process as the metal line 161 of the discharge metal structure 160. As described above, the antenna metal layer 212 can include a plurality of metal layers formed in the respective corresponding M-layers (such as M2 layer, M3 layer, etc.) in the MLI structure 115. The antenna metal layer 212 may not cover the active substrate 140 of the SOI structure 102 in the vertical direction. Similarly, the antenna metal layer 212 may not cover the device region 150. In some embodiments, the active substrate 140 may be spaced apart from the antenna metal layer 212 by a distance D 1 . The distance D 1 can be at least 0.2 microns, at least 0.5 microns, or at least 1 micron. In some embodiments, the device region 150 may be spaced apart from the antenna metal layer 212 by a distance D 2 . The distance D 2 can be at least 0.1 microns, at least 0.3 microns, or at least 0.5 microns. It should be noted that other possible values of D 1 and D 2 are also within the scope of this disclosure.

[0130] In some embodiments, the MLI structure 115 may include an electrical wiring structure 220 for interconnecting IC devices included in the active substrate 140 and the device region 150 of the SOI structures 102a and 102b, respectively. The electrical wiring structure 220 may include a plurality of horizontal metal lines and vertical vias in one or more M layers of the MLI structure 115. In some embodiments, the electrical wiring structure 220 is not electrically connected to (i.e., electrically isolated from) the antenna metal layer 212 of the antenna metal structure 210, especially when the electrical wiring structure 220 is at a different electrical potential than the antenna metal layer 212 of the antenna metal structure 210.

[0131] Figure 2D FIG. 2 is a schematic diagram illustrating a top view of a layout of another exemplary semiconductor structure 200 ′ according to some embodiments. Figure 2D As shown in the example of FIG. 2 , the semiconductor structure 200 ′ includes an interconnect metal 222 that interconnects the electrical wiring structure 220 and the antenna metal layer 212 of the antenna metal structure 120. Such an arrangement may be useful when the electrical wiring structure 220 and the antenna metal layer 212 are at the same potential.

[0132] Figure 3 FIG. 1 is a schematic diagram illustrating a top view of a layout of another exemplary semiconductor structure 300 according to some embodiments, wherein the semiconductor structure 300 is Figure 2C A close variation of the semiconductor structure 200. Figure 3 In the example of FIG. 1 , the antenna metal layer 212 is in the form of multiple horizontally interconnected antenna metal lines rather than a single continuous metal layer. As shown, the antenna metal layer 212 includes multiple horizontally interconnected antenna metal lines 302 in one or more M layers of the MLI structure. Compared to a single continuous antenna metal layer, multiple horizontally interconnected antenna metal lines 302 can provide better routing flexibility, better current carrying capacity, and reduced material cost.

[0133] Exemplary manufacturing process flow

[0134] Figure 4 is a flow chart depicting an example method 400 of fabricating a semiconductor structure 600 , according to some embodiments. Figure 5 is a depiction according to some embodiments, Figure 4 Flowchart of example operation 402 is shown in FIG. Figures 6A to 6N According to some embodiments, the use of Figure 4 The exemplary method 400 is shown in cross-sectional views at various stages of manufacturing a semiconductor structure 600. It should be noted that the semiconductor structure 600 is a close variation of the semiconductor structures 100 and 200, and the semiconductor structures 100 and 200 can also be manufactured by the method 400 or any operation thereof.

[0135] likeFigure 4 As shown, method 400 may include operations 402, 403, 406, and 408. In some embodiments, method 400 may further include optional operations 404, 410, and 412. Additional operations may be performed. Also, it should be understood that the order of operations discussed with reference to Figure 4 and Figure 5 is provided for illustrative purposes, and thus, other embodiments may use other orders. These various orders of operations are within the scope of the embodiments of the present disclosure.

[0136] At 402, an SOI structure integrated into a large substrate is fabricated. The SOI structure includes a heavily doped layer, an insulating layer disposed on the heavily doped layer and surrounded by the heavily doped layer, and an active substrate disposed on the insulating layer and surrounded by the insulating layer. Examples of operation 402 are further described below with reference to Figure 5 and Figures 6A to 6J

[0137] Now referring to Figure 5 , operation 402 may include operations 502, 504, 506, 508, 510, 514, 516, 518, and 520. In other embodiments, operation 402 may include operations 502, 504, 506, 511, 514, 516, 518, and 520.

[0138] At 502, a large substrate is provided. The large substrate may be a doped substrate, such as a P-type substrate (e.g., P-type doped silicon) or an N-type substrate (such as N-type doped silicon).

[0139] At 504, a groove is formed in the large substrate. In some embodiments, the semiconductor substrate is selectively etched to form the groove. In some embodiments, the groove is etched by etching the exposed area left by the first mask pattern on the semiconductor substrate. In some embodiments, the first mask pattern is a photoresist mask pattern. In some embodiments, the first mask pattern is a hard mask pattern, and the hard mask pattern may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In some embodiments, the large substrate is etched by wet etching. In some embodiments, the large substrate is etched by dry etching. In some embodiments, the large substrate is etched by plasma etching.

[0140] At Figure 6A and Figure 6B In the example shown, the large substrate 101 has an exposed area left by the first mask pattern 602a. The groove 604 is formed by etching the large substrate 101. After etching the large substrate 101, the groove 604 has a bottom 606 and sidewalls 608. The bottom 606 and sidewalls 608 define Figure 1A ​The angle (γ) shown. In some embodiments, γ is greater than 85 degrees. In one example, the angle γ is 90 degrees. In another example, the angle γ is 100 degrees. In yet another example, the angle γ is 110 degrees. In still another example, the angle γ is 120 degrees. It should be noted that other possible values of the angles α, β, and γ are also within the scope of this disclosure.

[0141] At 506, a heavily doped layer is formed. At Figure 6C In the example shown, the heavily doped layer 120 can be formed by performing an ion implantation process to implant dopants into the bottom 606 and the sidewalls 608. Accordingly, the bottom 121 of the heavily doped layer 120 is formed on the bottom 606, and the side portions 122 of the heavily doped layer 120 are formed on the sidewalls 608. In some embodiments, P-type dopants such as boron, aluminum, gallium, or indium are implanted to form the heavily doped layer 120 (i.e., the P+ layer). In some embodiments, N-type dopants such as phosphorus, arsenic, or antimony are implanted to form the heavily doped layer 120 (i.e., the N+ layer). In some embodiments, the doping concentration of the heavily doped layer 120 is from 10 2 to 10 14 per square centimeter (cm 20 ), or from 10 2 to 10 15 per square centimeter (cm 18 ) dopant molecules. It should be noted that other possible values of the doping concentration of the heavily doped layer 120 are also within the scope of this disclosure. In some embodiments, the doping concentration of the heavily doped layer 120 has a gradient distribution in the downward direction.

[0142] In some embodiments, operation 402 is followed by operation 508 at 508, where a first silicon epitaxial layer is formed on the heavily doped layer. The first silicon epitaxial layer can be epitaxially grown on the heavily doped layer. In some embodiments, the first silicon epitaxial layer is generated using chemical vapor deposition (CVD) techniques (e.g., metalorganic CVD (MOCVD), atmospheric pressure CVD (APCVD), low pressure CVD (LPCVD), ultra-high vacuum CVD (UHVCVD), molecular beam epitaxy (MBE), atomic layer deposition (ALD), other suitable techniques, or a combination of the above).

[0143] At Figure 6D In the example shown, the first silicon epitaxial layer 610 is formed on the heavily doped layer 120. The second mask pattern 602b covers the top surface of the side portions 122 of the heavily doped layer 120 to prevent the first silicon epitaxial layer from forming thereon. The first silicon epitaxial layer 610 corresponds to the insulating layer 130 formed in subsequent operations.

[0144] At 510, an oxygen implantation process is performed to implant oxygen into the silicon epitaxial layer and form an oxygen implanted layer. The areas of the bulk substrate left exposed by the second mask pattern are implanted with oxygen. Thus, oxygen is implanted into the bottom surface of the heavily doped layer and the semiconductor substrate beneath the sidewall surfaces. The thickness of the oxygen implanted layer can be adjusted according to the implantation energy and duration. The thickness of the oxygen implanted layer is defined as the portion below the top surface where the oxygen concentration is higher than a preset amount. In one example, the oxygen concentration is in the range of 5×10 15 cm -2 to 5×10 18 cm -2 . It should be noted that other values of oxygen concentration can be used in other examples.

[0145] In another embodiment, operation 402 continues from operation 506 to operation 511. At 511, by adding an oxygen dopant during the formation of the first silicon epitaxial layer, operations 508 and 511 are performed simultaneously, or in one step, and the oxygen implanted layer is formed in a single process.

[0146] In the Figure 6E illustrated example, an oxygen implanted layer 620 is formed. The oxygen implanted layer 620 includes a bottom 621 disposed on the bottom 121 of the heavily doped layer 120, and sides 622 disposed on the sides 122 of the heavily doped layer 120.

[0147] After the oxygen implanted layer 620 is formed, the operation continues to operation 514. At 514, a second silicon epitaxial layer is formed on the oxygen implanted layer. The second silicon epitaxial layer can be formed in a manner similar to the first silicon epitaxial layer. In the Figure 6F example, a silicon epitaxial layer 630 is formed on the oxygen implanted layer 620. A third mask pattern 602c covers the top surface of the oxygen implanted layer 620, the top surface of the sides 122 of the heavily doped layer 120, and the top surface of the bulk substrate 101, preventing the second silicon epitaxial layer 630 from being formed thereon. The second silicon epitaxial layer 630 has a bottom 631 disposed on the bottom 621 of the oxygen implanted layer 620, and sides 632 disposed on the sides 622 of the oxygen implanted layer 620.

[0148] At 516, an annealing process is performed to form an insulating layer. In some embodiments, the annealing process is a thermal annealing process. In one example, the temperature of the thermal annealing process is in the range of 900 degrees Celsius to 1100 degrees Celsius. After the thermal annealing process, the oxygen in the oxygen implanted layer reacts with the silicon in the oxygen implanted layer to form silicon dioxide. Thus, the oxygen implanted layer is transformed into a silicon dioxide layer, which forms an insulating layer between the second silicon epitaxial layer and the heavily doped layer. In the Figure 6G example, the insulating layer 130 is formed from the oxygen implanted layer 620 after the annealing process. The insulating layer includes a bottom 131 corresponding to the bottom 621 of the oxygen implanted layer 620, and sides 132 corresponding to the sides 622 of the oxygen implanted layer 620.

[0149] At 518, a third silicon epitaxial layer is formed. The third silicon epitaxial layer can be formed in a manner similar to that of the first and second silicon epitaxial layers. In Figure 6H an example, the third silicon epitaxial layer 640 is formed on the second silicon epitaxial layer 630 and fills the remaining portion of the groove 604. As Figure 6H shown, the third silicon epitaxial layer can protrude vertically above the top surface of the second silicon epitaxial layer 630. As discussed below, the top surfaces of both the third silicon epitaxial layer 640 and the second silicon epitaxial layer 630 can be planarized in a subsequent planarization process.

[0150] At 520, a planarization process is performed. In Figure 6I an example, a chemical mechanical planarization (CMP) process is performed on the top surface of the bulk substrate 101. After operation 520, the portions of the third silicon epitaxial layer outside the groove or above the top surface of the bulk substrate 101 are removed. Most of the remaining third silicon epitaxial layer 640 and the second silicon epitaxial layer 630 together form the active substrate 140. Thus, the SOI structure 102 is formed and includes a heavily doped layer 120, an insulating layer 130, and the active substrate 140.

[0151] Now refer back to Figure 4 . At 403, a peripheral heavily doped region is formed. The peripheral heavily doped region can be formed in a manner similar to that of the heavily doped layer. In Figure 6J an example, a fourth photomask pattern 602d is applied to cover the top surfaces of the bulk substrate 101 and the SOI structure 102, and an opening is made to expose the peripheral region of the SOI substrate. Then an ion implantation process is performed to implant dopants of the same semiconductor type as the heavily doped layer 120 into the peripheral region of the bulk substrate 101 exposed by the opening to form the peripheral heavily doped region 125. Note that the peripheral heavily doped region can only partially (i.e., not completely) surround the SOI structure 102, as Figure 6J shown. The peripheral heavily doped region 125 is connected to the side portion 122 of the heavily doped layer 120, and the peripheral heavily doped region 125 has a top surface 126 coplanar with the top surfaces of the bulk substrate 101 and the active substrate 140.

[0152] In optional operation 404, an antenna effect protection device is formed in the bulk substrate. In some embodiments, the antenna effect protection device includes one or more antenna diodes incorporated into the bulk substrate. The antenna diodes are arranged and positioned horizontally close to the SOI. In some embodiments, the antenna diodes are formed by sequentially forming doped wells in the bulk substrate and forming heavily doped regions in the doped wells. In some embodiments, the bulk substrate includes a first dopant, and the doped wells and the heavily doped regions each include a second dopant. In some embodiments, the first dopant is a P-type dopant and the second dopant is an N-type dopant. In some embodiments, the first dopant is an N-type dopant and the second dopant is a P-type dopant. Thus, the heavily doped region, the doped well, and the underlying bulk substrate form an antenna diode.

[0153] In Figure 6K an example of, a fifth photomask pattern 602e is applied to cover the top surface of the bulk substrate 101, the SOI structure 102, and the top surface 125 of the peripheral heavily doped region to expose an opening of an adjacent SOI structure 102. A groove (not shown) can be formed in the region of the bulk substrate 101 corresponding to the opening, and then subsequent ion implantation is performed to form a doped well 206 and a heavily doped region 204, respectively. In some embodiments, the heavily doped region 204 and the doped well 206 can be formed in a single implantation process by adjusting implantation parameters such as energy and dopant concentration. In some embodiments, the doping concentration of the heavily doped region 204 is at least one order of magnitude (i.e., 10 times) higher than that of the doped well 206. The heavily doped region 204, the doped well 206, and the underlying bulk substrate 101 form an antenna diode 202.

[0154] In Figure 6L an example of, a CMP process can be performed to planarize the top surface of the antenna diode 202 such that the top surfaces of the antenna diode 202 and the active substrate 140 are coplanar.

[0155] In operation 406, one or more IC devices (i.e., semiconductor devices) are formed in the active substrate or the SOI structure. In some embodiments, one or more transistors (e.g., MOS transistors) can be formed in the active substrate. In Figure 6M an example of, a plurality of IC devices 145 are formed in the active substrate 140 of the SOI structure 102.

[0156] In operation 408, a first discharge metal structure is formed to electrically connect the IC devices in the active substrate to the peripheral heavily doped region. The first discharge structure can be formed in the same process as forming the MLI structure in the bulk substrate 101 during BEOL manufacturing. In Figure 6MIn the example, a first discharge metal structure 160b is formed. As an example, the M0 layer and the M1 layer are sequentially formed on the bulk substrate 101. A horizontal metal line and two via contacts 162a and 162b (collectively referred to as via contacts 162) are formed in the M1 layer and / or the M0 layer. In some embodiments, in a damascene or dual damascene process, the first metal discharge structure 160b can be formed simultaneously with other metal lines and via contacts in the M0 and M1 layers. The first via contact 162a electrically connects the transistor 145b in the active substrate 140 to the metal line 161, and the second via contact 162b electrically connects the peripheral heavily doped region 125 to the metal line 161, thereby forming a first electrical path to release the charge generated in the IC device of the active substrate and discharge it to the bulk substrate 101 (i.e., the ground plane) through the antenna diode 202.

[0157] In optional operation 410, a second discharge metal structure is formed to electrically connect the IC device in the active substrate to the antenna effect protection device. The second discharge metal structure can be formed in the same manner as in the same process of forming the first discharge metal structure or in the same process of forming the MLI structure. In Figure 6M the example, a second discharge metal structure 160a is formed. Similar to the first metal discharge structure 160b, the second metal discharge structure 160a is formed by forming a horizontal metal line 161 in the M1 layer and two via contacts 162a and 162b in the M1 layer and / or the M0 layer. The first via contact 162a electrically connects the first transistor 145a in the active substrate 140 to the metal line 161, and the second via contact electrically connects the heavily doped region 204 of the antenna diode 202 to the metal line 161, thereby forming a second electrical path to release the charge generated in the IC device of the active substrate and discharge it to the bulk substrate 101 (i.e., the ground plane) through the antenna diode 202.

[0158] In optional operation 412, an antenna metal structure is formed to electrically connect the antenna effect protection device. The antenna metal structure can be formed by forming one or more antenna metal layers and interconnect vias when forming the M layer of the MLI structure. In Figure 6NIn an example, an antenna metal structure 210 is formed. The antenna metal structure 210 may be formed by sequentially forming one or more antenna metal layers 212 (e.g., antenna metal layer 212a in the M2 layer and antenna metal layer 212b in the M3 layer) when forming the M2 layer and the M3 layer of the MLI structure 115. A plurality of via contacts 214 are also formed to interconnect the antenna metal layers 212a / 212b and the metal wires 161 of the second discharge metal structures 160a / 160b, such that the antenna metal structure 210 is also electrically connected to an antenna diode 202 (not shown). In some embodiments, the plurality of antenna metal layers 212 may be formed in M layers above one or more M0 layers of the MLI structure 115, and the plurality of antenna metal layers 212 in different M layers may be interconnected by via contacts.

[0159] Summary

[0160] According to some aspects of the present disclosure, a semiconductor structure is provided. In an example, a semiconductor structure includes a bulk substrate, a silicon-on-insulator substrate, one or more semiconductor devices, a peripheral heavily doped region, and a discharge metal structure. The bulk substrate has a top surface. The silicon-on-insulator substrate is integrated into the bulk substrate, and the silicon-on-insulator substrate further has a heavily doped layer, an insulating layer, and an active substrate. The heavily doped layer includes a bottom and sides. The bottom of the heavily doped layer extends horizontally, and the sides of the heavily doped layer extend peripherally from a top end portion in a downward direction to a bottom end portion, where the top end portion is connected to the top surface of the bulk substrate, and the bottom end portion is connected to the bottom of the heavily doped layer. The insulating layer is disposed on the heavily doped layer and surrounded by the heavily doped layer. The active substrate is disposed on the insulating layer and surrounded by the insulating layer, wherein the active substrate is isolated by the insulating layer and the heavily doped layer and has a top surface coplanar with the top surface of the bulk substrate. One or more semiconductor devices are disposed in the active substrate. The peripheral heavily doped region is connected to the top end portion of the side of the heavily doped layer and extends horizontally from the top end portion of the side of the heavily doped layer. The discharge metal structure electrically interconnects the one or more semiconductor devices and the peripheral heavily doped layer.

[0161] In an example, a semiconductor structure, wherein the bulk substrate is a doped substrate, and the bulk substrate, the heavily doped layer, and the peripheral heavily doped region are doped with dopants of the same semiconductor type.

[0162] In an example, a semiconductor structure, wherein the bulk substrate has a first doping concentration, the heavily doped layer and the peripheral heavily doped region have a second doping concentration, and the second doping concentration is at least one order of magnitude higher than the first doping concentration.

[0163] In an example, a semiconductor structure wherein the heavily doped layer forms an angle of at least 85 degrees between the sides and the bottom.

[0164] In one example, a semiconductor structure in which a heavily doped layer and a peripheral heavily doped region have a thickness ranging from 0.1 micrometer to 1 micrometer.

[0165] In one example, a semiconductor structure in which an insulating layer has a thickness ranging from 0.1 micrometer to 1 micrometer.

[0166] In one example, a semiconductor structure in which an active substrate has a thickness ranging from 1 micrometer to 200 micrometers.

[0167] In one example, a semiconductor structure in which the insulating layer is a thermally oxidized silicon layer.

[0168] In one example, a semiconductor structure in which the discharge metal structure further includes a horizontal metal wire and two via contacts that respectively interconnect the one or more semiconductor devices and the horizontal metal wire, and interconnect the peripheral heavily doped region and the horizontal metal wire.

[0169] In one example, a semiconductor structure in which the discharge metal structure is formed in one or more metallization layers of a multi-layer interconnect structure disposed on a bulk substrate.

[0170] In another example, a semiconductor structure includes a bulk substrate, a silicon-on-insulator substrate, one or more semiconductor devices, one or more antenna diodes, and a first discharge metal structure. The bulk substrate has a top surface. The silicon-on-insulator substrate is integrated into the bulk substrate, and the silicon-on-insulator substrate further has a heavily doped layer, an insulating layer, and an active substrate. The heavily doped layer includes a bottom and sides. The bottom of the heavily doped layer extends horizontally, and the sides of the heavily doped layer extend peripherally from a top end portion in a downward direction to a bottom end portion, where the top end portion is connected to the top surface of the bulk substrate, and the bottom end portion is connected to the bottom of the heavily doped layer. The insulating layer is disposed on the heavily doped layer and surrounded by the heavily doped layer. The active substrate is disposed on the insulating layer and surrounded by the insulating layer, where the active substrate is isolated by the insulating layer and the heavily doped layer and has a top surface coplanar with the top surface of the bulk substrate. One or more semiconductor devices are disposed in the active substrate. One or more antenna diodes are integrated into the bulk substrate and adjacent to the silicon-on-insulator substrate. The first discharge metal structure electrically interconnects the one or more semiconductor devices and the one or more antenna diodes.

[0171] In another example, a semiconductor structure further includes a peripheral heavily doped region that is connected to the top end portion of the side of the heavily doped layer and extends horizontally from the top end portion of the side of the heavily doped layer, and a second discharge metal structure that electrically interconnects the one or more semiconductor devices and the peripheral heavily doped layer.

[0172] In another example, a semiconductor structure in which the antenna diode further includes a doped well and a heavily doped region. The doped well is disposed in the bulk substrate, and the heavily doped region is disposed in the doped well and has a top surface coplanar with the top surface of the bulk substrate.

[0173] In another example, a semiconductor structure in which the bulk substrate is a doped substrate, the bulk substrate, the heavily doped layer, and the peripheral heavily doped region have a first dopant of a first semiconductor type, and the doped well and the heavily doped region of the antenna diode have a second dopant of a second semiconductor type, and the first semiconductor type is opposite to the second semiconductor type.

[0174] In another example, a semiconductor structure in which the first discharge structure further includes a horizontal metal line and two via contacts that respectively interconnect one or more semiconductor devices and the horizontal metal line, and interconnect the peripheral heavily doped region and the horizontal metal line.

[0175] In another example, a semiconductor structure in which the first discharge structure further includes a horizontal metal line and two via contacts that respectively interconnect one or more semiconductor devices and the horizontal metal line, and interconnect the heavily doped region of the antenna diode and the horizontal metal line.

[0176] In another example, a semiconductor structure includes an antenna metal structure, where the antenna metal structure further includes one or more antenna metal layers and a plurality of via contacts. The one or more antenna metal layers are respectively disposed on one or more metallization layers of a multi-layer interconnect structure on the bulk substrate, and the plurality of via contacts interconnect the antenna diode and the one or more antenna metal layers.

[0177] In another example, a semiconductor structure includes a bulk substrate, a silicon-on-insulator substrate, one or more semiconductor devices, a doped well, and a first discharge metal structure. The bulk substrate has a top surface. The silicon-on-insulator substrate is integrated into the bulk substrate, and the silicon-on-insulator substrate further has a heavily doped layer, an insulating layer, and an active substrate. The heavily doped layer includes a bottom and sides. The bottom of the heavily doped layer extends horizontally, and the sides of the heavily doped layer extend peripherally downward from a top end to a bottom end, where the top end connects to the top surface of the bulk substrate and the bottom end connects to the bottom of the heavily doped layer. The insulating layer is disposed on the heavily doped layer and surrounded by the heavily doped layer. The active substrate is disposed on the insulating layer and surrounded by the insulating layer, where the active substrate is isolated by the insulating layer and the heavily doped layer and has a top surface coplanar with the top surface of the bulk substrate. One or more semiconductor devices are disposed in the active substrate. The doped well is disposed in the bulk substrate. The first discharge metal structure electrically interconnects the one or more semiconductor devices and the doped well.

[0178] According to some aspects of the present disclosure, a method of manufacturing a semiconductor structure is provided. In one example, a method of manufacturing a semiconductor structure includes providing a bulk substrate having a top surface; forming a heavily doped layer, the heavily doped layer including a bottom portion and side portions, the bottom portion extending horizontally, and the side portions extending downward along the perimeter from a top end portion to a bottom end portion, wherein the top end portion is connected to the top surface of the bulk substrate, and the bottom end portion is connected to the bottom portion; forming an insulating layer on the heavily doped layer; forming an active substrate on the insulating layer, the active substrate being isolated by the insulating layer and the heavily doped layer, and the active substrate having a top surface coplanar with the top surface of the bulk substrate; forming one or more antenna diodes in the bulk substrate proximate to the active substrate; forming one or more semiconductor devices in the active substrate; and forming a first discharge metal structure, wherein the first discharge metal structure electrically interconnects the one or more semiconductor devices and the antenna diodes.

[0179] In one example, a method of manufacturing a semiconductor structure further includes forming a peripheral heavily doped region on the top surface of the bulk substrate, the peripheral heavily doped region being connected to and extending horizontally from the top end portion of the side portions of the heavily doped layer; and forming a second discharge metal structure that electrically interconnects the one or more semiconductor devices and the peripheral heavily doped region.

[0180] In one example, a method of manufacturing a semiconductor structure further includes forming an antenna metal structure electrically connected to the antenna diodes.

[0181] The foregoing outlines the features of several embodiments so that those skilled in the art may better understand the various aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or obtaining the same advantages as those introduced herein. Those skilled in the art should also recognize that such equivalent constructs do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that: Include: a large substrate having a top surface; A silicon-on-insulator (SOI) substrate is integrated into the bulk substrate, and the SOI substrate further comprises: A heavily doped layer comprising: a bottom extending in a horizontal direction; and A side portion extends from a top end portion to a bottom end portion along a periphery in a downward direction, wherein The top end portion is connected to the top surface of the bulk substrate, and the bottom end portion is connected to the bottom; an insulating layer, disposed on the heavily doped layer and surrounded by the heavily doped layer; as well as an active substrate disposed on the insulating layer and surrounded by the insulating layer, wherein the active substrate is isolated by the insulating layer and the heavily doped layer and has a top surface coplanar with the top surface of the bulk substrate; One or more semiconductor devices disposed in the active substrate; a peripheral heavily doped region connected to the top end of the side portion of the heavily doped layer and horizontally extending from the top end of the side portion of the heavily doped layer; as well as A discharge metal structure electrically interconnects the one or more semiconductor devices with the peripheral heavily doped region.

2. The semiconductor structure according to claim 1, wherein: The bulk substrate is a doped substrate, and the bulk substrate, the heavily doped layer and the peripheral heavily doped region are doped with dopants of the same semiconductor type.

3. The semiconductor structure according to claim 2, wherein: The bulk substrate has a first doping concentration, the heavily doped layer and the peripheral heavily doped region have a second doping concentration, and the second doping concentration is at least one order of magnitude higher than the first doping concentration.

4. The semiconductor structure according to claim 1, wherein: The insulating layer is a thermal silicon oxide layer.

5. The semiconductor structure according to claim 1, wherein: The discharge metal structure further comprises a horizontal metal line and two through-hole contacts. The two through-hole contacts respectively interconnect the one or more semiconductor devices with the horizontal metal line, and interconnect the peripheral heavily doped region with the horizontal metal line.

6. The semiconductor structure according to claim 1, wherein: The discharge metal structure is formed in one or more metallization layers of a multi-layer interconnect structure disposed on a bulk substrate.

7. A semiconductor structure, characterized in that: include: a large substrate having a top surface; A silicon-on-insulator substrate is integrated into the bulk substrate, and the silicon-on-insulator substrate further comprises: A heavily doped layer comprising: a bottom extending in a horizontal direction; and A side portion extends from a top end portion to a bottom end portion along a periphery in a downward direction, wherein The top end portion is connected to the top surface of the bulk substrate, and the bottom end portion is connected to the bottom; an insulating layer, disposed on the heavily doped layer and surrounded by the heavily doped layer; and an active substrate disposed on the insulating layer and surrounded by the insulating layer, wherein the active substrate is isolated by the insulating layer and the heavily doped layer and has a top surface coplanar with the top surface of the bulk substrate; One or more semiconductor devices disposed in the active substrate; one or more antenna diodes integrated into the bulk substrate and adjacent to the SOI substrate; as well as A first discharge metal structure electrically interconnects the one or more semiconductor devices and the one or more antenna diodes.

8. The semiconductor structure according to claim 7, wherein: Also includes: a peripheral heavily doped region connected to the top end of the side portion of the heavily doped layer and extending horizontally from the top end of the side portion of the heavily doped layer; and A second discharge metal structure electrically interconnects the one or more semiconductor devices with the peripheral heavily doped layer.

9. The semiconductor structure of claim 7, further comprising an antenna metal structure, wherein the antenna metal structure further comprises: One or more antenna metal layers, respectively disposed on one or more metallization layers of a multi-layer interconnect structure on the bulk substrate; and A plurality of via contacts interconnect the antenna diode to the one or more antenna metal layers.

10. A semiconductor structure, characterized in that: include: a large substrate having a top surface; A silicon-on-insulator substrate is integrated into the bulk substrate, and the silicon-on-insulator substrate further comprises: A heavily doped layer comprising: a bottom extending in a horizontal direction; and A side portion extends from a top end portion to a bottom end portion along a periphery in a downward direction, wherein The top end portion is connected to the top surface of the bulk substrate, and the bottom end portion is connected to the bottom; an insulating layer, disposed on the heavily doped layer and surrounded by the heavily doped layer; and an active substrate disposed on the insulating layer and surrounded by the insulating layer, wherein the active substrate is isolated by the insulating layer and the heavily doped layer and has a top surface coplanar with the top surface of the bulk substrate; One or more semiconductor devices disposed in the active substrate; a doping well disposed in the bulk substrate; as well as A first discharge metal structure electrically interconnects the one or more semiconductor devices and the doping well.

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