Surface-mounted high-voltage silicon stack

Abstract

The utility model provides a surface-mounted high-voltage silicon stack, which relates to the field of semiconductor components, comprises a plastic package body and is characterized by further comprising at least two chip sets and metal frames which are plastically packaged in the plastic package body, and the two chip sets are respectively connected onto the two metal frames through the bottom surfaces of the chip sets. The two metal frames extend to the two sides of the plastic package body respectively to form two pins, and the top faces of the two chip sets are connected so that the two chip sets can be connected in series. Each chip group comprises a plurality of diode chips which are stacked and connected in series; according to the utility model, automation is facilitated, automatic production of a matrix type frame is easier, the production efficiency of a high-voltage silicon stack is improved, a surface-mounted product is more beneficial to miniaturization, and a plurality of chips can be stacked to form a high-voltage series circuit by adopting the connection structure and packaging a commercially available diode chip of about 1000V; prefabricated processing of the chip is avoided, and the production process is simpler.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductor components, and particularly relates to a surface-mounted high-voltage silicon stack. Background Art

[0002] In a high-voltage rectification circuit of over a thousand volts, it is obvious that a single rectifier diode cannot meet the requirement of reverse voltage resistance. A high-voltage silicon stack is formed by connecting multiple rectifier diodes in series and then encapsulating them, and is specifically used for high-voltage rectification of electronic devices. It is widely used in household appliances, such as televisions, microwave ovens and other fields.

[0003] Most of the common high-voltage silicon stacks on the market are of an axial lead type structure. Usually, they have a relatively large volume and are mostly stacked by 8 - 10 chips above 1000V. Their processing technology is relatively complex, the degree of automation is low, generally manual insertion and lead trimming are required, and the production cost is high. At present, with the increasingly fierce market competition, how to improve production efficiency quickly and efficiently and reduce product costs are all problems that need to be solved urgently.

[0004] In the prior art, the publication number CN106057789A discloses a surface-mounted high-voltage silicon stack and its production process. In order to meet the requirement of a high voltage of 8kV, the die (i.e., silicon column) needs to be processed, and there is a problem of complex chip processing. Content of the Utility Model

[0005] The utility model provides a surface-mounted high-voltage silicon stack for solving the above problems in the prior art. It does not need to process the die, but uses commercially available conventional chips to meet the high-voltage typical requirements of the surface-mounted high-voltage silicon stack.

[0006] The technical solution of the utility model for solving the above technical problems is as follows: A surface-mounted high-voltage silicon stack includes a plastic package body, and is characterized in that it further includes at least two chip groups and a metal frame encapsulated in the plastic package body. The two chip groups are respectively connected to the two metal frames through their bottom surfaces, and the two metal frames respectively extend to both sides of the plastic package body to form two pins. The top surfaces of the two chip groups are connected to form a series connection between the two chip groups; each chip group includes a plurality of diode chips arranged in a stacked manner and connected in series.

[0007] Further, the two pins are respectively used as the input end and the output end of the surface-mounted high-voltage silicon stack.

[0008] Further, the top surfaces between the two chip groups are connected through a jumper.

[0009] Furthermore, the jumper is connected to the chip group through solder.

[0010] Further, the plurality of diode chips in each chip group are connected through copper grains.

[0011] Furthermore, the copper particles are connected to the diode chip through solder.

[0012] Further, the diode chip is an N-type substrate diode chip or a P-type substrate diode chip. At this time, multiple diode chips in one chip group are arranged in the forward direction, while multiple diode chips in the other chip group are arranged in the reverse direction.

[0013] Alternatively, the diode chips in one chip group are N-type substrate diode chips, and the diode chips in the other chip group are P-type substrate diode chips. At this time, multiple diode chips in the two chip groups are arranged in the same direction.

[0014] The beneficial effects of the present utility model are as follows:

[0015] 1. Compared with the existing axial lead type high voltage silicon stack, the present utility model is a surface mount package structure, which is more conducive to automation during customer assembly, and is more suitable for automated production of matrix frames, improving the production efficiency of high voltage silicon stacks. The surface-mounted product is more conducive to miniaturization.

[0016] 2. Compared with the existing surface mount high voltage silicon stack made of specially processed die (i.e., silicon column), by using the connection structure of the present utility model and encapsulating commercially available diode chips of about 1000V, a high voltage series circuit composed of multiple chips can be realized, avoiding the prefabrication process of the chips, and the production process is simpler. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a schematic diagram of the external structure of the present utility model;

[0018] Figure 2 is a schematic cross-sectional structure diagram of the present utility model;

[0019] Figure 3 is a schematic diagram of the arrangement structure of the metal frame in the plastic package in the top view state;

[0020] In the figure: 1. The first chip group, 11. The second diode chip, 2. The second chip group, 21. The second diode chip, 3. The first metal frame, 4. The second metal frame, 5. The pin, 6. The plastic package, 7. The jumper, 8. The copper particle. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0021] The principles and features of the present utility model will be described below. The examples given are only for explaining the present utility model and are not intended to limit the scope of the present utility model.

[0022] As shown in the attached drawings, the surface mount high voltage silicon stack of this embodiment includes a plastic package 6, two chip groups (the first chip group 1 and the second chip group 2) and metal frames (the first metal frame 3 and the second metal frame 4) encapsulated in the plastic package 6. The two chip groups are respectively connected to the two metal frames through their bottom surfaces. The two metal frames respectively extend to both sides of the plastic package to form two pins 5, which are respectively used as the input end and the output end of the surface mount high voltage silicon stack. The top surfaces of the two chip groups are connected through a jumper 7 so that a series connection is formed between the two chip groups. Each chip group includes a plurality of diode chips arranged in a stacked manner and connected in series.

[0023] Specifically, in this embodiment, the first chip group 1 includes a plurality of first diode chips 11 arranged in a stacked manner and connected in series. Specifically, N-type substrate diode chips are used. The bottom first diode chip 11 is connected to the PAD surface (the position for welding the chip) of the first metal frame 3 through solder (not shown in the attached drawings). The top first diode chip 11 is connected to the jumper 7 through solder. Adjacent first diode chips 11 are connected by copper particles 8, and the copper particles and the first diode chips 11 are connected and fixed through solder. The second chip group 2 includes a plurality of second diode chips 21 arranged in a stacked manner and connected in series. Specifically, N-type substrate diode chips are used. The top second diode chip 21 is connected to the jumper 7 through solder. The bottom second diode chip 21 is connected to the PAD surface (the position for welding the chip) of the second metal frame 4 through copper particles. Adjacent second diode chips 21 are connected by copper particles 8, and the copper particles 8 are connected and fixed to the second diode chips 21 and the PAD surface of the second metal frame 4 through solder.

[0024] In this embodiment, both the first diode chips 11 and the second diode chips 21 use N-type substrate diode chips. The plurality of first diode chips 11 in the first chip group 1 are arranged in the forward direction, while the plurality of second diode chips 21 in the second chip group 2 are arranged in the reverse direction, that is, the second diode chips 21 are inverted relative to the first diode chips 11. Among them, the N-type substrate diode chips are ordinary commercially available chips of about 1000V.

[0025] In other embodiments, it is also possible to use the method that both the first diode chips 11 and the second diode chips 21 use P-type substrate diode chips and the second diode chips 21 are inverted relative to the first diode chips 11.

[0026] In addition, in other embodiments, it is also possible that one of the first diode chips 11 and the second diode chips 21 uses a P-type substrate diode chip and the other uses an N-type substrate diode chip. At this time, the second diode chips 21 and the first diode chips 11 are arranged in the same direction.

Claims

1. A SMD high voltage silicon stack, comprising a plastic package, characterized in that: It also includes at least two chip groups and a metal frame encapsulated in a plastic package body. The two chip groups are connected to the two metal frames through their bottom surfaces respectively. The two metal frames extend to both sides of the plastic package body to form two pins. The top surfaces of the two chip groups are connected so that the two chip groups are connected in series. Each chip group includes a plurality of diode chips that are stacked and connected in series.

2. The SMD high voltage silicon stack according to claim 1, characterized in that: The two pins are used as the input end and the output end of the SMD high voltage silicon stack respectively.

3. The SMD high voltage silicon stack according to claim 1, characterized in that: The top surfaces of the two chipsets are connected via a jumper.

4. The SMD high voltage silicon stack according to claim 3, characterized in that: The jumper chip is connected to the chipset via solder.

5. The SMD high voltage silicon stack according to claim 1, characterized in that: Multiple diode chips in each chip group are connected by copper particles.

6. The SMD high voltage silicon stack according to claim 5, characterized in that: The copper particles are connected to the diode chip via solder.

7. The SMD high voltage silicon stack according to any one of claims 1 to 6, characterized in that: The diode chip adopts an N-type substrate diode chip or a P-type substrate diode chip.

8. The SMD high voltage silicon stack according to claim 7, characterized in that: The multiple diode chips in one chip group are arranged in a forward direction, while the multiple diode chips in another chip group are arranged in an inverted direction.

9. The SMD high voltage silicon stack according to any one of claims 1 to 6, characterized in that: The diode chips in one chip group use N-type substrate diode chips, and the diode chips in another chip group use P-type substrate diode chips.

10. The SMD high voltage silicon stack according to claim 9, characterized in that: The multiple diode chips of the two chip groups are arranged in the same direction.

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