Semiconductor device

Abstract

A semiconductor device includes a lower contact member over a substrate; a first dielectric layer over the lower contact feature; a metal-insulator-metal structure over the first dielectric layer; a second dielectric layer over the metal-insulator-metal structure; the conductive feature extends through the second dielectric layer, the metal-insulator-metal structure, and the first dielectric layer, and is electrically coupled to the lower contact feature, where the metal-insulator-metal structure includes a first conductor plate layer, a second conductor plate layer over the first conductor plate layer, and an insulator layer over the second conductor plate layer, and an insulator layer between the first conductor plate layer and the second conductor plate layer, where the conductive feature interfaces with the first conductor plate layer on a first interface and the conductive feature interfaces with the second conductor plate layer on a second interface, where the insulator layer extends a distance greater than about 5 nanometers beyond the first interface and the second interface, the insulator layer is in direct contact with the top, bottom, and conductive features on the side surfaces of the insulator layer.

Description

Technical Field

[0001] Embodiments of the present utility model relate to semiconductor devices, and more particularly to contact components. Background Art

[0002] The semiconductor integrated circuits (IC) industry has experienced exponential growth. Advancements in integrated circuit materials and design in modern technology have produced several generations of integrated circuits, each generation having smaller and more complex circuits compared to the previous generation. During the development of integrated circuits, the functional density (i.e., the number of interconnect devices per unit chip area) generally increases while the geometry size (i.e., the smallest element (or line) that can be produced using the process) decreases. This miniaturization process generally provides benefits by increasing production efficiency and reducing related costs. This miniaturization also increases the complexity of manufacturing and fabricating integrated circuits.

[0003] As the geometry size of integrated circuit devices decreases, passive devices that require a large surface area are transferred to the back-end-of-line (BEOL) structure. A Metal-Insulator-Metal (MIM) capacitor is one example of such a passive device. A typical MIM capacitor includes several conductor plate layers that are insulated from each other by several insulator layers. Contact vias are formed through the MIM capacitor. Forming the contact vias requires forming openings through the MIM capacitor and the dielectric layers above and below the MIM capacitor. Forming the openings typically results in a stepped structure, which may affect the conformity of the barrier layer and / or seed layer deposited on the sidewalls of the openings. Therefore, although existing semiconductor devices generally meet their intended purposes, they are not entirely satisfactory in all aspects. Summary of the Utility Model

[0004] An object of the present utility model is to provide a semiconductor device to solve at least one of the above problems.

[0005] An embodiment of the present utility model provides a semiconductor device, including a lower contact component above a substrate; a first dielectric layer above the lower contact component; a metal-insulator-metal structure above the first dielectric layer; a second dielectric layer above the metal-insulator-metal structure; and a conductive component extending through the second dielectric layer, the metal-insulator-metal structure, and the first dielectric layer and electrically coupled to the lower contact component, wherein the metal-insulator-metal structure includes a first conductor plate layer, a second conductor plate layer above the first conductor plate layer, and an insulator layer between the first conductor plate layer and the second conductor plate layer, wherein the conductive component interfaces with the first conductor plate layer at a first interface and the conductive component interfaces with the second conductor plate layer at a second interface, wherein the insulator layer extends more than about 5 nanometers beyond the first interface and the second interface, and the insulator layer directly contacts the conductive component on the top, bottom, and side surfaces of the insulator layer.

[0006] According to one embodiment of the present utility model, the first interface and the second interface are respectively curved towards the first conductor plate layer and the second conductor plate layer.

[0007] According to one embodiment of the present utility model, the conductive component interfaces with the first dielectric layer on a first sidewall, the conductive component interfaces with the metal-insulator-metal structure on a second sidewall, and the conductive component interfaces with the second dielectric layer on a third sidewall, wherein the second sidewall forms a second angle with the bottommost surface of the metal-insulator-metal structure, the third sidewall forms a first angle with the topmost surface of the metal-insulator-metal structure, and the difference between the first angle and the second angle is less than 10 degrees.

[0008] According to one embodiment of the present utility model, the first sidewall forms a third angle with the top surface of the lower contact component, and the difference between the first angle and the third angle is less than 5 degrees.

[0009] According to one embodiment of the present utility model, the thickness of the insulator layer ranges from 4 nm to 20 nm.

[0010] According to one embodiment of the present utility model, the ratio of the distance that the insulator layer extends beyond the first interface and the second interface to the thickness of the insulator layer ranges from 0.2 to 5, or from 0.5 to 2.

[0011] According to one embodiment of the present utility model, the distance that the insulator layer extends beyond the first interface is greater than or equal to the distance that the insulator layer extends beyond the second interface.

[0012] According to one embodiment of the present utility model, the distance that the insulator layer extends beyond the first interface and the second interface ranges from 5 nm to 20 nm, or from 5 nm to 15 nm, or from 5 nm to 10 nm.

[0013] According to one embodiment of the present utility model, in a top view, the conductive component has a square shape, a circular shape, an oval shape, a racetrack shape, a polygonal shape, or a rectangular shape.

[0014] According to one embodiment of the present utility model, an upper portion of the conductive component has a substantially straight sidewall. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Embodiments of the present utility model can be best understood from the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various elements can be arbitrarily enlarged or reduced to clearly show the features of the embodiments of the present utility model.

[0016] Figure 1 is a schematic flow chart showing a method of manufacturing a semiconductor device according to an embodiment of the present utility model.

[0017] Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 and Figure 10 are partial cross-sectional schematic views showing a semiconductor device at various stages of manufacture according to an embodiment of the present utility model.

[0018] Figure 9A 、 Figure 9B and Figure 9C are partial cross-sectional schematic views showing an opening through a conductor plate layer in a MIM structure according to an embodiment of the present utility model.

[0019] Figure 11 is a partial top view showing a semiconductor device according to an embodiment of the present utility model.

[0020] The reference numerals are as follows:

[0021] 10: Method

[0022] 12, 14, 16: Blocks

[0023] 18, 20, 22: Blocks

[0024] 24, 26, 28: Blocks

[0025] 200: Workpiece

[0026] 200 - 1, 200 - 2, 200 - 3: Region

[0027] 202: Substrate

[0028] 250: First dielectric layer

[0029] 255: Lower contact component

[0030] 256: Second dielectric layer

[0031] 258: Third dielectric layer

[0032] 260: MIM structure

[0033] 262: Bottom conductor plate layer

[0034] 262a: Conductor plate layer

[0035] 264: Insulator layer

[0036] 264a: Insulator layer

[0037] 264b: Insulator layer

[0038] 266: Top conductor plate layer

[0039] 266a: Conductor plate layer

[0040] 267: Fourth dielectric layer

[0041] 272: Opening

[0042] 276: Metal filling layer

[0043] 277, 277 - 1, 277 - 2, 277 - 3: Upper contact component

[0044] 278: Barrier layer

[0045] 287: Hard mask layer

[0046] D1: First angle

[0047] D2: Second angle

[0048] D3: Third angle

[0049] D4: Fourth angle

[0050] DL: Depth

[0051] L: Dimension

[0052] L1: First dimension

[0053] L1’: Second dimension

[0054] L2: Third dimension

[0055] L2’: Fourth dimension

[0056] L3: Fifth dimension

[0057] S: Side wall

[0058] P1, P1’: Distance

[0059] X: Direction

[0060] Y: Direction

[0061] Z: Direction Detailed implementation manners

[0062] It should be understood that the following disclosure provides a number of embodiments or examples for implementing different elements of the provided subject matter. Specific examples of each element and its configuration are described below to simplify the description of the embodiments of the present utility model. Of course, these are only examples and are not intended to limit the embodiments of the present utility model. For example, when it is mentioned in the description that the first element is formed on the second element, it may include embodiments where the first and second elements are in direct contact, and may also include embodiments where additional elements are formed between the first and second elements such that they are not in direct contact.

[0063] Furthermore, spatially relative terms may be used herein, such as "under", "below", "lower", "above", "higher", etc., for the purpose of facilitating the description of the relationship between one or more components or features in the drawings. Spatially relative terms are intended to cover different orientations of the device in use or operation, as well as the orientations described in the drawings. When the device is turned to different orientations (rotated 90 degrees or other orientations), the spatially relative adjectives used therein will also be interpreted according to the turned orientation.

[0064] In addition, when using terms such as "about", "approximate", etc. to describe a number or a range of numbers, such terms are intended to cover numbers within a reasonable range, which is considered according to the variations inherently occurring in the manufacturing process as understood by those skilled in the art. For example, based on the known manufacturing tolerances for manufacturing components with features related to that number, the quantity or range of numbers covers a reasonable range including the said number, such as within + / - 10% of the said number. For example, those skilled in the art know that the manufacturing tolerance related to the deposited material layer is + / - 15%, and a material layer with a thickness of "about 5 nanometers" can cover a size range from 4.25 nanometers to 5.75 nanometers. In addition, the embodiments of the present utility model may repeat reference to numerical values and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity, and is not intended to represent the relationship between the different embodiments and / or configurations discussed.

[0065] Metal-insulator-metal (MIM) capacitors (also known as MIM structures) have been widely used in functional circuits such as mixed-signal circuits, analog circuits, radio frequency (RF) circuits, dynamic random access memories (DRAMs), embedded DRAMs, and logic arithmetic circuits. In system-on-chip (SOC) applications, different capacitors of different functional circuits must be integrated on the same chip to achieve different purposes. For example, in a mixed-signal circuit, capacitors are used as decoupling capacitors and high-frequency noise filters. For DRAM and embedded DRAM circuits, capacitors are used to store memories, and for RF circuits, capacitors are used in oscillators and phase-shift networks for coupling and / or bypassing purposes. For microprocessors, capacitors are used for decoupling. As the name implies, an MIM capacitor comprises a sandwich structure of alternating metal layers (also known as conductor plate layers) and insulator layers. An exemplary MIM capacitor comprises a bottom conductor plate layer, an intermediate conductor plate layer above the bottom conductor plate layer, and a top conductor plate layer above the intermediate conductor plate, with each conductor plate layer insulated from an adjacent conductor plate layer by an insulator layer. Since MIM capacitors are fabricated in a BEOL structure to have a larger surface area, their conductor plate layers extend over several lower contact components. Contact via holes can be formed through the conductor plate layers to electrically couple the lower contact components to upper contact components, such as contact pads, for connection to an external circuit.

[0066] The openings of the contact via holes can penetrate the conductor plate layers and insulator layers of the MIM capacitor and the dielectric layers above and below the MIM capacitor. Before depositing a conductive fill material, a barrier layer and / or a seed layer can be deposited in the openings. The uniformity of the barrier layer and / or the seed layer may affect the reliability level to prevent the conductive fill material from penetrating into the MIM capacitor, which may lead to voltage breakdown. In addition, the openings in the same semiconductor device can have different dimensions (e.g., width, length, diameter) to form contact via holes with different dimensions in the semiconductor device. Different dimensions may result in non-uniform etching rates, which may lead to defects.

[0067] Traditionally, fluorine-based etchants (e.g., sulfur hexafluoride (SF 6)) for etching through a conductor plate layer and dielectric layers above and below it. According to observations, conventional etching processes may produce metal fluorides as byproducts (hereinafter referred to as "metal fluoride byproducts"). For example, etching of a titanium nitride conductor plate layer may produce titanium fluoride (TF X , where X = 3 or 4). Metal fluoride byproducts are non-volatile and may not be removable during the etching process. When the conductor plate layer is etched, this metal fluoride may redeposit onto the newly etched surface and slow down the etching process. Generally, the redeposition of metal fluoride may result in the formation of stepped sidewalls of the opening because redeposition may occur when the etching process proceeds towards the lower conductor plate layer. In a side view schematic, the characteristics of a contact via formed using a conventional process may be a steep taper first as the contact via penetrates the MIM capacitor, followed by a shallow taper. Additionally, residual metal fluoride byproducts may remain at the interface between the conductor plate layer and the contact via. The residual metal fluoride byproducts may redeposit on the dielectric layer below the conductor plate layer, slowing down the etching rate through the underlying dielectric layer and causing dishing of the underlying dielectric layer. Dishing of the underlying dielectric layer may lead to non-uniform etching through an etch stop layer (ESL) located below the underlying dielectric layer. The presence or absence of residual metal fluoride byproducts at the interface can be observed or verified by energy-dispersive X-ray spectroscopy (EDX).

[0068] The present disclosure provides a method for forming an opening in a semiconductor device having substantially linear sidewalls in a cross-sectional profile. The method of the present disclosure uses a multi-step etching process to form an opening through a MIM structure (and dielectric layers and an etch stop layer (ESL) above and below it). In some embodiments, a first etching process uses a first fluorine-containing etchant to etch through the upper dielectric layer, a second etching process uses a chlorine-containing etchant to etch through the MIM structure, a third etching process uses a second fluorine-containing etchant to etch into the lower dielectric layer, and then a fourth etching process uses the second fluorine-containing etchant to etch through the lower dielectric layer and the etch stop layer. During the fourth etching process, a non-zero bias power and a non-zero source power are applied to the semiconductor device. After the fourth etching process and before forming a contact via in the opening, a wet cleaning process is performed to smooth the profile of the opening. The method of the present disclosure can form a contact via having a substantially linear taper.

[0069] Aspects of the present disclosure will now be described in more detail with reference to the accompanying drawings. In this regard, Figure 1 is a flow schematic diagram showing a method 10 for manufacturing a semiconductor device, according to an embodiment of the present disclosure. Method 10 is merely an example and is not intended to limit the present disclosure to what is expressly recited in method 10. Additional steps may be provided before, during, and after method 10, and some of the described operational steps may be replaced, eliminated, or moved forward or backward for additional embodiments of the method. For simplicity, not all steps are described in detail in the present disclosure. Method 10 will be described below in conjunction with Figures 2 to 8 and Figure 10 which are exemplary partial cross-sectional schematic diagrams showing a semiconductor device at different manufacturing stages, according to an embodiment of the present disclosure.

[0070] Referring to Figure 1 and Figure 2 , method 10 includes a block 12 of providing a workpiece 200. The workpiece 200 includes various film layers that have been formed thereon. Since the semiconductor device will be formed from the workpiece 200, the workpiece 200 may be referred to as the semiconductor device 200 in a suitable context. The workpiece 200 includes a substrate 202, which may be formed of silicon or other semiconductor materials such as germanium. The substrate 202 may also include compound semiconductors such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. In some embodiments, the substrate 202 may include alloy semiconductors such as silicon germanium, silicon carbide germanium, gallium phosphoarsenide, or gallium indium phosphide. In some embodiments, the substrate 202 may include an epitaxial layer, for example, an epitaxial layer covering a bulk semiconductor. Various microelectronic components may be formed in or on the substrate 202, such as transistor elements including source / drain components, gate structures, gate spacers, source / drain contacts, gate contacts, isolation structures including shallow trench isolation (STI), or any other suitable elements.

[0071] In some embodiments, workpiece 200 includes an interconnect layer, a carbide layer, and / or an oxide layer over substrate 202. For simplicity, these film layers or elements are not shown. The interconnect layer can be one of the interconnect layers in a multi-layered interconnect (MLI) structure, which is formed over substrate 202 and can include a plurality of patterned dielectric layers and conductive layers that provide interconnects (e.g., wiring) between various microelectronic elements of workpiece 200. The interconnect layer can include a plurality of conductive elements and interlayer dielectric (ILD) elements that partially or completely surround the conductive elements. In an embodiment, the carbide layer is deposited over the interconnect layer. Any suitable type of carbide material, such as silicon carbide (SiC), can be used in the carbide layer. In an embodiment, the oxide layer is deposited over the carbide layer. In some embodiments, the oxide layer includes undoped silicon oxide. In an embodiment, the interconnect layer, the carbide layer, and the oxide layer can be replaced by one or more interconnect structures.

[0072] In some embodiments, workpiece 200 includes a first dielectric layer 250 deposited over substrate 202. In some embodiments, first dielectric layer 250 includes undoped silica glass (USG) or silicon oxide. In some embodiments, first dielectric layer 250 includes USG. In some embodiments, the thickness of first dielectric layer 250 ranges from about 800 nm to about 1000 nm.

[0073] In some embodiments, workpiece 200 includes a lower contact member 255 embedded in a first dielectric layer 250. Although the lower contact member 255 is located below an upper contact member (to be discussed below), the lower contact member 255 is sometimes referred to as a top metal (TM) contact because it can be located above a transistor component (not shown in the figures of the present disclosure). The lower contact member 255 can extend vertically through the first dielectric layer 250. The lower contact member 255 can include a barrier layer and a metal fill layer embedded in the barrier layer. Forming the lower contact member 255 involves multiple processes. The first dielectric layer 250 can be patterned, for example, using a lithography process to form trenches. A barrier layer can then be formed in the trenches, and subsequently a metal fill layer can be deposited over the barrier layer in the trenches. In some embodiments, the barrier layer includes titanium nitride, tantalum, tantalum nitride, or a combination of the foregoing. In some embodiments, the metal fill layer includes a metal or a metal alloy, such as copper, cobalt, nickel, aluminum, tungsten, titanium, or a combination of the foregoing. In one embodiment, the metal fill layer of the lower contact member 255 includes copper. In some embodiments, the metal fill layer is formed by deposition or electroplating, followed by a chemical mechanical planarization (CMP) process. In an embodiment, about 5% to about 10% of the thickness of the first dielectric layer 250 is also removed by the CMP process.

[0074] In some embodiments, workpiece 200 includes a second dielectric layer 256 deposited over the lower contact member 255. The second dielectric layer 256 can also be referred to as an etch stop layer (ESL) 256. In some embodiments, the thickness of the second dielectric layer 256 ranges from about 65 nm to about 85 nm. The second dielectric layer 256 can include silicon carbonitride (SiCN), silicon nitride (SiN), silicon oxycarbide (SiOC), silicon carbide (SiC), silicon oxynitride (SiOCN), and / or other suitable materials. In some embodiments, the second dielectric layer 256 includes SiCN. The second dielectric layer 256 is used to indicate an etch endpoint during an etching process.

[0075] In some embodiments, workpiece 200 includes a third dielectric layer 258 deposited over the second dielectric layer 256. In some embodiments, the thickness of the third dielectric layer 258 ranges from about 300 nm to about 500 nm. In an embodiment, the third dielectric layer 258 includes a suitable dielectric material, such as SiN.

[0076] In some embodiments, workpiece 200 includes a metal-insulator-metal (MIM) structure 260 formed over a third dielectric layer 258. Forming the MIM structure 260 involves multiple processes, including the formation and patterning of conductor plate layers (e.g., bottom conductor plate layer 262 and top conductor plate layer 266).

[0077] In some embodiments, forming the bottom conductor plate layer 262 involves multiple processes such as deposition, lithography, development, and / or etching. The bottom conductor plate layer 262 may be surface treated, such as using nitrous oxide (N 2 O) gas for sidewall passivation. As Figure 2 shown, an insulator layer 264 is formed over the bottom conductor plate layer 262. In an embodiment, the insulator layer 264 is deposited to have a generally uniform thickness above the top surface of the workpiece 200. Then, the top conductor plate layer 266 is formed over the insulator layer 264. The top conductor plate layer 266 may be formed in a manner similar to that used to form the bottom conductor plate layer 262. In some embodiments, the thickness of each of the bottom conductor plate layer 262 and the top conductor plate layer 266 ranges from about 30 nm to about 80 nm. In some embodiments, to prevent electron migration and oxygen diffusion, the conductor plate layers in the MIM structure 260 (e.g., bottom conductor plate layer 262 and top conductor plate layer 266) may be formed of a transition metal or a transition metal nitride. For example, the conductor plate layers in the MIM structure 260 may be formed of titanium (Ti), tantalum (Ta), titanium nitride (TiN), or tantalum nitride (TaN). In an embodiment, the conductor plate layer includes TiN.

[0078] Although only two conductor plate layers (bottom conductor plate layer 262 and top conductor plate layer 266) and one insulator layer (insulator layer 264) are shown, the MIM structure 260 may include more than two conductor plate layers and more than one insulator layer. Each conductor plate layer is insulated from an adjacent conductor plate layer by an insulator layer. In some embodiments, the MIM structure 260 includes multiple conductor plate layers, including the bottom conductor plate layer 262 and the top conductor plate layer 266, which serve as the metal plates of a capacitor. The MIM structure 260 may also include multiple insulator layers, including the insulator layer 264 disposed between the bottom conductor plate layer 262 and the top conductor plate layer 266. The MIM structure 260 is used to implement one or more capacitors, which may be connected to other electronic components such as transistors. The multi-layer MIM structure 260 allows capacitors to be closely arranged together in the vertical and lateral directions, thereby reducing the amount of lateral space required to implement the capacitors. Thus, the MIM structure 260 can accommodate ultra-high density capacitors.

[0079] In some embodiments, to increase the capacitance value, the insulator layer 264 comprises a high-k dielectric material having a k value (dielectric constant) greater than that of silicon oxide. The insulator layer 264 can be relatively thin to increase the capacitance value. However, a minimum thickness of the insulator layer 264 is maintained to avoid potential breakdown of the capacitor in the MIM structure 260 (e.g., when there is a high potential difference between the two conductor plate layers, current may leak between them, resulting in breakdown). In some embodiments, the thickness of the insulator layer 264 ranges from about 4 nm to about 20 nm. In some embodiments, the insulator layer 264 is formed of zirconium oxide (ZrO 2 ), hafnium oxide (HfO 2 ), aluminum oxide (Al 2 O 3 ), tantalum oxide (TaO 5 ), silicon oxide (SiO 2 ), or titanium oxide (TiO 2 ). Further, to optimize the capacitor performance, in some embodiments, the insulator layer 264 is a three-layer structure that includes, from bottom to top, a first zirconium oxide (ZrO 2 ) layer, an aluminum oxide (Al 2 O 3 ) layer, and a second zirconium oxide (ZrO 2 ) layer, where each of the sub-layers has the same thickness.

[0080] In some embodiments, the workpiece 200 includes a fourth dielectric layer 267 deposited over the MIM structure 260. In some embodiments, the thickness of the fourth dielectric layer 267 ranges from about 400 nm to about 500 nm. In some embodiments, the third dielectric layer 258 comprises a suitable dielectric material such as SiN. In some embodiments, the fourth dielectric layer 267 is formed by depositing about 900 nm to about 1000 nm of dielectric material and then performing a CMP process to achieve the final thickness. As Figure 2 shown, the MIM structure 260 is sandwiched between the third dielectric layer 258 and the fourth dielectric layer 267, and the third dielectric layer 258 and the fourth dielectric layer 267 can have the same material and / or the same thickness. In some embodiments, the second dielectric layer 256, the third dielectric layer 258, the MIM structure 260, and the fourth dielectric layer 267 are regarded as multiple parts of the passivation structure.

[0081] See Figure 1 and Figure 3, Method 10 includes box 14, patterning and etching through the fourth dielectric layer 267 to form an opening 272. Patterning can include depositing a hard mask layer 287 over the first conductive layer (bottom conductor plate layer 262), forming a photoresist layer (not shown) over the hard mask layer, patterning the photoresist layer using photolithography, using the patterned photoresist layer as an etch mask to etch the hard mask layer 287, and then using the patterned hard mask layer 287 as an etch mask to etch the fourth dielectric layer 267. The etching of the fourth dielectric layer 267 can also be referred to as the first etching process. The first etching process etches through the fourth dielectric layer 267 at a uniform rate, causing the sidewalls of the fourth dielectric layer 267 to form a linear tapered profile. The first etching process is controlled by time such that it terminates at the top surface of the top conductor plate layer 266. The first etching process can be a dry etching process using a first etchant. In an embodiment, the first etchant is a fluorine-based etchant, including sulfur hexafluoride (SF 6 ), nitrogen trifluoride (NF 3 ), difluoromethane (CH 2 F 2 ), trifluoromethane (CHF 3 ), octafluorocyclobutane (C 4 F 8 ), hexafluoroethane (C 2 F 6 ), carbon tetrafluoride (CF 4 ), or a combination of the above. In an embodiment, the first etchant includes SF 6 .

[0082] See Figure 1 and Figure 4, Method 10 includes block 16, etching through MIM structure 260 to extend opening 272. This step may also be referred to as a second etching process. In an embodiment, the second etching process etches through MIM structure 260 at a substantially uniform rate, thereby creating a linearly tapered profile of the sidewalls (S) of MIM structure 260. Notably, in some embodiments, the second etching process etches the insulator layer 264 at a rate different from that of etching the bottom conductor plate layer 262 and the top conductor plate layer 266, so the insulator layer 264 may taper with a different profile from the bottom conductor plate layer 262 and the top conductor plate layer 266. However, because the thickness of each of the bottom conductor plate layer 262 and the top conductor plate layer 266 is greater than that of the insulator layer 264, the profile of the sidewalls (S) of MIM structure 260 is dominated by the portions passing through the bottom conductor plate layer 262 and the top conductor plate layer 266, so the portion of opening 272 passing through MIM structure 260 has a substantially linear tapered profile. The second etching process may be a dry etching process. The second etchant for the second etching process is selected from etchants that do not produce any non-volatile by-products during the second etching process that are difficult to remove during the second etching process in the reaction between the second etchant and the conductor plate layer. In some embodiments, the second etchant is a chlorine-based etchant, such as chlorine gas (Cl 2 ), hydrogen chloride (HCl), silicon tetrachloride (SiCl 4 ), carbon tetrachloride (CCl 4 ), chloroform (CHCl 3 ), boron trichloride (BCl 3 ), tungsten pentachloride (WCl 5 ), or a combination of the above. In other words, the second etchant does not contain fluorine or fluorine atoms. In an embodiment, the exposed sidewalls (S) of MIM structure 260 are treated with oxygen to form a surface region that is more susceptible to subsequent etching processes. Then the workpiece 200 is etched with the second etchant, which will form gaseous products with the oxygen-treated surface region. In an embodiment where the second etchant contains WCl 5 , tungsten residues (not shown) may remain on the sidewalls (S) of MIM structure 260. Energy dispersive X-ray fluorescence (XRF) can be used to detect the presence of tungsten residues.

[0083] In some embodiments, the second etch process is controlled by time such that it terminates after completely etching through all of the conductor plate layers in the MIM structure 260. In some cases, the second etch process may extend the opening 272 downward to a level below the MIM structure 260. The second etch process does not cause dishing on the top surface of the third dielectric layer 258 because no non-volatile by-products are redeposited on the third dielectric layer 258 near the sidewalls of the opening 272. That is, at the end of the second etch process, the bottom surface of the opening 272 is substantially flat. The flat bottom surface of the opening 272 prevents dishing during the third etch process (to be described below).

[0084] See Figure 1 and Figure 5 , method 10 includes block 18 of etching the third dielectric layer 258 to further extend the opening 272. This step may also be referred to as the third etch process. In an embodiment, the third etch process etches the third dielectric layer 258 at a substantially uniform rate, resulting in a linear tapered profile of the sidewalls of the third dielectric layer 258. The third etch process is controlled by time such that it terminates slightly above the top surface of the second dielectric layer 256 (as Figure 5 shown) or at the top surface of the second dielectric layer 256. The third etch process may be a dry etch process using a third etchant that etches the third dielectric layer 258 and the second dielectric layer 256 at a faster rate than the second etchant. Additionally, the third etchant is selected such that it does not damage the lower contact member 255. For example, in an exemplary second etch process, the third etchant does not contain chlorine because chlorine etches oxides and nitrides at a slower rate than carbon tetrafluoride (CF 4 ). And it is known that chlorine can damage copper, which is used as the material of the lower contact member 255. In some embodiments, the third etchant includes a fluorine-based etchant such as SF 6 , NF 3 , CH 2 F 2 , CHF 3 , C 4 F 8 , C 2 F 6 , CF 4 , or a combination of the above. In some embodiments, the third etch process uses CF 4 as the etchant.

[0085] In some embodiments, the first etching process, the second etching process, and the third etching process are performed using a source power (e.g., radio frequency (RF) source power) and a bias power (e.g., RF bias power). The source power and the bias power can provide energy to convert the etchant gas into a plasma, thereby increasing the etching ability (e.g., etching rate) of the process. In some embodiments, the source power ranges from about 1,000 watts (W) to about 3,000 W, alternatively from about 1,000 W to about 2,500 W, or alternatively from about 1,500 W to about 2,500 W. In some embodiments, the bias power ranges from about 1,000 W to about 3,000 W, alternatively from about 1,000 W to about 2,500 W, or alternatively from about 1,500 W to about 2,500 W. If the source power and the bias power (collectively also referred to as "power") are too small, the etching ability (e.g., etching rate) may be too small, and the etching rate may also be different when the opening 272 has different sizes (e.g., widths). If the power is too large, the etching rate may be too large, which increases the difficulty of controlling the etching process.

[0086] See Figure 1 and Figure 6 , method 10 includes block 20 that performs a first cleaning process to clean the exposed surface (e.g., conductive surface), such as through the sidewalls (S) of the MIM structure 260. In an embodiment, the sidewalls of the conductor plate layer are recessed at a higher rate than the sidewalls of the insulator layer. In some examples, the first cleaning process includes a wet cleaning that applies a first cleaning solution to the workpiece 200. In an embodiment, the first cleaning solution includes de-ionized (DI) water, hydrogen peroxide (H 2 O 2 ), SC1 (DI water, NH 4 OH and / or H 2 O 2 ), SC2 (DI, HCl and / or H 2 O 2 ), de-ionized water with ozone (DIWO 3 ), SPM (H 2 SO 4 and / or H 2 O 2 ), SOM (H 2 SO 4 and / or O 3 ), SPOM, H 3 PO 4, dilute hydrofluoric acid (DHF), HF, HF / ethylene glycol (EG), HF / HNO 3 , NH 4 OH, tetramethylammonium hydroxide (TMAH), or a combination of the above. In an embodiment, the first cleaning solution contains H 2 O 2 . Before or after the first cleaning process, the hard mask layer 287 and the photoresist layer can be selectively removed.

[0087] See Figure 1 and Figure 7 , method 10 includes block 22, etching through the second dielectric layer 256 to expose the top surface of the lower contact member 255. This step can also be referred to as the fourth etching process. In Figure 5 the illustrated embodiment, the third dielectric layer 258 is not etched through in the third etching process, and the remaining portion of the third dielectric layer 258 is etched through together with the second dielectric layer 256 in the fourth etching process. In some other embodiments, the third dielectric layer 258 is etched through in the third etching process, and the second dielectric layer 256 is etched through in the fourth etching process. In an embodiment, the fourth etching process etches through the remaining portion of the second dielectric layer 256 and / or the third dielectric layer 258 at a substantially uniform rate, thereby forming a linear tapered profile on the sidewalls of the remaining portion of the second dielectric layer 256 and / or the third dielectric layer 258. In some embodiments, the profile of the opening 272 is smoothed in the fourth etching process. That is, bumps (not shown) on the sidewalls of the second dielectric layer 256, the third dielectric layer 258, and the fourth dielectric layer 267 exposed in the opening 272 can be removed. The fourth etching process can be a dry etching process using a fluorine-based etchant. The fluorine-based etchant can be the same as the third etchant, or can be an etchant different from the third etchant. The fluorine-based etchant can include SF 6 , NF 3 , CH 2 F 2 , CHF 3 , C 4 F 8 , C 2 F 6 , CF 4 , or a combination of the above. The fluorine-based etchant can include CF 4 . The fourth etching process is controlled by time such that it terminates at the top surface of the lower contact member 255.

[0088] In some embodiments, the fourth etching process is performed with a non-zero source power (e.g., non-zero RF source power) and a non-zero bias power (e.g., non-zero RF bias power). In an embodiment, the non-zero source power is less than the source powers of the first, second, and third etching processes. In an embodiment, the non-zero bias power is less than the bias powers of the first, second, and third etching processes. In some embodiments, the non-zero source power ranges from about 200 W to about 1,000 W, alternatively from about 300 W to about 800 W, or alternatively from about 400 W to about 700 W. In some embodiments, the non-zero bias power ranges from about 200 W to about 1,000 W, alternatively from about 300 W to about 800 W, or alternatively from about 400 W to about 700 W. If the non-zero source power and the non-zero bias power (collectively also referred to as "non-zero power") are too small, the etching ability (e.g., etching rate) may be too small, and the second dielectric layer 256 may be etched at too small a rate, such that the sidewalls of the etched second dielectric layer 256 may further taper from the sidewalls of the third dielectric layer 258, and the etching rate may be different when the opening 272 has different sizes (e.g., widths). If the non-zero power is too large, the non-zero power may leak through the lower contact member 255 into the substrate 202 and damage any components therein, and the etching rate may be too large, which increases the difficulty of controlling the fourth etching process, and the lower contact member 255 may be damaged.

[0089] See Figure 1 and Figure 8 , method 10 includes block 24 of performing a second cleaning process to clean the exposed surfaces, such as through the sidewalls (S) of the MIM structure 260. In an embodiment, the sidewalls of the conductor plate layer are etched away at a higher rate than the sidewalls of the insulator layer. Additionally, the sidewalls of the fourth, third, and second dielectric layers 267 / 258 / 256 exposed in the opening 272 can be further smoothed in the second cleaning process. Thus, the second cleaning process laterally expands the opening 272 by a depth DL (δL) (as Figure 8 shown, the dashed line is the position of the sidewall of the opening 272 before the second cleaning process). The depth DL can be less than about 1% of the size L of the opening 272. Thus, the second cleaning process can substantially not change the taper angle of the sidewalls in the opening 272. In some examples, the second cleaning process includes a wet cleaning, applying a second cleaning solution to the workpiece 200. In some embodiments, the second cleaning solution includes a copper protectant, DI, H 2 O 2 , SC1, SC2, DIWO 3 , SPM, SOM, SPOM, H 3 PO 4 , DHF, HF, HF / EG, HF / HNO 3 , NH4 OH, TMAH, or a combination thereof. In one embodiment, the second cleaning solution comprises a copper protectant and H 2 O 2 The copper protectant may include an azole compound, an amine compound, or a combination thereof. In embodiments where the lower contact member 255 includes copper, the copper protectant may react with the copper to form a protective layer (e.g., a copper nitride layer) over the top surface of the lower contact member 255, which prevents the copper below from further reacting with the second cleaning solution. At this point, the opening 272 is substantially formed.

[0090] To keep it simple, Figure 8 The outline of the opening 272 shown is simplified. In practice, different etching processes can etch different film layers at different rates to form tapered surfaces with different tapered angles. Detailed side views of the opening 272 through the MIM structure 260 are representatively shown in Figure 9A and Figure 9B as well as Figure 9C First see Figure 9A . The sidewalls of the fourth dielectric layer 267 are at a first angle D1 relative to the topmost surface of the MIM structure 260. The sidewalls of the bottom conductor plate layer 262 and the top conductor plate layer 266 are at a second angle D2 relative to the bottommost surface of the MIM structure 260. The sidewalls of the third dielectric layer 258 are at a third angle D3 relative to the top surface of the lower contact component 255. The sidewalls of the fourth dielectric layer 256 are at a fourth angle D4 relative to the top surface of the lower contact component 255. In some embodiments, D1 may be greater than D2 and D3, and D3 may be greater than D2. D3 may be substantially equal to D4. In some cases, the difference between D1 and D2 is less than about 10 degrees (°). In some cases, the difference between D1 and D3 is less than about 5°. Therefore, the opening 272 can be considered to have three parts: a top portion having sidewalls at a first angle D1, a middle portion having sidewalls at a second angle D2, and a bottom portion having sidewalls at a third angle D3 (or a fourth angle D4). Because the thickness of the MIM structure 260 is relatively small compared to the total thickness of the fourth, third, and second dielectric layers 267 / 258 / 256, the profile through the MIM structure 260 is a relatively small portion of the total profile of the opening 272, and because the difference between D1 and D3 is less than about 5°, the opening 272 has a substantially linear taper.

[0091] Because the sidewalls of the bottom conductor plate layer 262 and the top conductor plate layer 266 are etched at a higher rate than the sidewalls of the insulator layer during the first and second cleaning processes, the insulator layer 264 protrudes from the top conductor plate layer 266 and the bottom conductor plate layer 262 of the MIM structure 260 by distances P1 and P1', respectively. In an embodiment, P1' is equal to or greater than P1. In some embodiments, P1 and P1' are greater than about 5 nm. In an embodiment, P1 and P1' range from about 5 nm to about 20 nm, alternatively from about 5 nm to about 15 nm, or alternatively from about 5 nm to about 10 nm. If P1 and P1' are too small, the first and second cleaning processes may not sufficiently clean the exposed surfaces in the opening 272. If P1 and P1' are too large, the barrier layer and / or the seed layer (to be described below) may not conformally deposit on the sidewalls of the MIM structure 260, which may result in leakage current or voltage breakdown. In some embodiments, the ratio of P1 or P1' to the thickness of the insulator layer 264 ranges from about 0.2 to about 5, alternatively from about 0.5 to about 2.

[0092] As Figure 9B shown, in some embodiments, the sidewalls of the bottom conductor plate layer 262 and the top conductor plate layer 266 of the MIM structure 260 are curved towards the bottom conductor plate layer 262 and the top conductor plate layer 266. This may be caused by the first and second cleaning processes. In some embodiments, the sidewall of the lower conductor plate layer (e.g., the bottom conductor plate layer 262) is curved more than the sidewall of the upper conductor plate layer (e.g., the top conductor plate layer 266). In an embodiment, a straight line extending from the highest point to the lowest point of the sidewalls of the bottom conductor plate layer 262 and the top conductor plate layer 266 of the MIM structure 260 forms a second angle D2 with the bottommost surface of the MIM structure 260.

[0093] The MIM structure 260 may include more conductor plate layers and more insulator layers, and the profile of the opening 272 remains approximately the same as that Figure 9A and Figure 9B described above, except that each insulator layer protrudes from the adjacent conductor plate layer by a distance P1. For example, as Figure 9CAs shown, the MIM structure 260 includes four conductor plate layers (266 / 266a / 262a / 262) and more than three insulator layers (264a / 264 / 264b). The insulator layer 264a protrudes from the conductor plate layers (266 / 266a) by distances P1 / P1'; the insulator layer 264 protrudes from the conductor plate layers (266a / 262a) by distances P2 / P2'; the insulator layer 264b protrudes from the conductor plate layers (262a / 262) by distances P3 / P3'. In some embodiments, P3' is equal to or greater than P3, P3' is equal to or greater than P2', P2' is equal to or greater than P2, P2' is equal to or greater than P1', and P1' is equal to or greater than P1.

[0094] See Figure 1 and Figure 10 , method 10 includes block 26 to form an upper contact member 277 (also referred to as a contact via, a metal via, or a wire) in the opening 272. The upper contact member 277 includes a metal fill layer 276 filling the opening 272. In some embodiments, to form the upper contact member 277, first, a barrier layer 278 is conformally deposited over the fourth dielectric layer 267 and into the opening 272 using a suitable deposition technique such as atomic layer deposition (ALD), physical vapor deposition (PVD), or chemical vapor deposition (CVD), and then a metal fill layer 276 is deposited over the barrier layer 278 using a suitable deposition technique such as ALD, PVD, or ALD. In some embodiments, the barrier layer 278 can be formed of the same material as the bottom conductor plate layer 262 and the top conductor plate layer 266. In those embodiments, the barrier layer 278 can be formed of titanium, tantalum, titanium nitride, or tantalum nitride. The metal fill layer 276 can be formed of copper, aluminum, or an alloy of the foregoing. The deposited barrier layer 278 and metal fill layer 276 are then patterned to form the upper contact member 277, as shown in the example of Figure 10 . In some embodiments, the barrier layer 278 and the metal fill layer 276 are formed in a two-stage or multi-stage etching process. Before forming the metal fill layer 276, a seed layer can be conformally deposited over the fourth dielectric layer 267 and into the opening 272 by any suitable method such as PVD. The seed layer can include a metal material such as the same material as the metal fill layer 276. Since the opening 272 has a substantially linear taper, the barrier layer 278 and / or the seed layer each have a substantially conformal thickness. This can increase the reliability level to prevent the metal fill layer from penetrating into the MIM structure 260, which may cause voltage breakdown.

[0095] In Figure 10 the illustrated embodiment, the upper contact member 277 includes an upper portion above the fourth dielectric layer 267 and a lower portion filled in the opening 272. In some embodiments, the upper portion of the upper contact member 277 has substantially straight sidewalls. In Figure 10 other embodiments not explicitly shown, the upper portion of the upper contact member 277 has tapered sidewalls. In some other embodiments, the upper contact member 277 does not include an upper portion. Although not shown in the drawings, when viewed along the direction Z, the upper contact member 277 may have a square shape, a circular shape, an oval shape, a racetrack shape, a polygonal shape, or a rectangular shape.

[0096] At least the upper portion of the upper contact member 277 is part of a redistribution layer (RDL) to reroute the bonding connections between the upper layer and the lower layer. The upper contact member 277 penetrates through the fourth dielectric layer 267, the MIM structure 260, the third dielectric layer 258, and the second dielectric layer 256 from top to bottom. The upper contact member 277 is in electrical contact with the lower contact member 255. The upper contact member 277 may be electrically coupled to any conductor plate layer of the MIM structure 260 or insulated from any conductor plate layer of the MIM structure 260.

[0097] Although Figure 10 not explicitly shown therein, the shape and profile of the lower portion of the upper contact member 277 generally conform to the shape and profile of the opening 272. That is, the lower portion of the upper contact member 277 will conform to the Figure 9A and Figure 9B and Figure 9C tapered profile shown therein. However, for simplicity, the detailed description in this regard is omitted.

[0098] See Figure 1, Method 10 includes box 28 and can perform further processes. Such further processes may include forming a passivation structure above the upper contact member 277 and above the fourth dielectric layer 267. The passivation structure may include one or more passivation layers, which may include one or more plasma-enhanced oxide layers, one or more undoped quartz glass layers, silicon nitride (SiN), or a combination of the above. The further processes may also include forming an opening through the passivation layer, depositing one or more layers of polymeric material, patterning one or more layers of polymeric material, depositing an under-bump-metallurgy (UBM) layer, depositing a copper-containing bump layer, depositing a capping layer, depositing a solder layer, and reflowing the solder layer. These further processes form a contact structure for connection to an external circuit.

[0099] Figure 10 The lower portion of the upper contact member 277 in [reference] can have any shape, such as being substantially rectangular or substantially circular when viewed from the top. Similarly, in some embodiments, the method includes forming a plurality of upper contact members 277 in the workpiece 200 simultaneously. Each upper contact member 277 is electrically connected to a lower contact member (not shown) similar to the lower contact member 255. These lower contact members can be arranged in different patterned loads.

[0100] Now refer to Figure 11 , which is a cross-sectional schematic view of the workpiece 200. The workpiece 200 includes a plurality of upper contact members 277-1, 277-2, 277-3, which are respectively disposed in three regions 200-1, 200-2, and 200-3 that pass through the fourth dielectric layer 267 in the XY plane. Each of the upper contact members 277-1, 277-2, 277-3 can be manufactured by the same method as the above-described manufacturing of the upper contact member 277, and thus can have the same material and profile as the upper contact member 277. In some embodiments, the upper contact members 277-1, 277-2, 277-3 are formed simultaneously by the same process. In some embodiments, the upper contact members 277-1 and 277-2 are substantially rectangular, as Figure 11 representatively shown in [reference]. The rectangular cross-section of the upper contact member 277-1 has a first dimension L1 (also referred to as the first width L1) and a second dimension L1' (also referred to as the first length L1'), while the rectangular cross-section of the upper contact member 277-2 has a third dimension L2 (also referred to as the second width L2) and a fourth dimension L2' (also referred to as the second length L2'). In some cases, L1 can be the same as L1', and L2 can be the same as L2'. In some other embodiments, the upper contact member 277-3 is substantially circular, asFigure 11 is representatively shown. The circular cross-section of the upper contact member 277-3 has a fifth dimension L3 (also referred to as diameter L3). In some embodiments, the ranges of L1, L1', L2, L2', and L3 are from about 500 nm to about 3000 nm. In some embodiments, L1, L2, and L3 are different from each other. The ratio of L1 / L2 or L1 / L3 can range from about 1 to about 6. If this ratio is too large, the etching rate for forming the opening for the upper contact member 277-1 may be greater than the etching rate for forming the openings for the upper contact members 277-2 or 277-3. This may result in the height of the upper contact member 277-1 being greater than the height of the upper contact members 277-2 or 277-3, and result in greater variations in the dimensions (e.g., width, length, diameter) of the upper contact members 277-1, 277-2, and 277-3. Although only three regions 200-1, 200-2, and 200-3 are shown, the workpiece 200 can include any number of regions, which can be in any relative positions, and each region can include any number of upper contact members. The upper contact members in different regions can have different shapes and dimensions.

[0101] Method 10 can include controlling power, non-zero power, the flow rate and composition of the etchant, pressure, and temperature, etc. during the first to fourth etching processes such that openings having different dimensions (e.g., L1, L2, L3) extend downward at similar etching rates throughout the process. Thus, the depths of the openings of different dimensions are controlled to be similar during different steps of the process. For example, the non-zero power, composition, and flow rate of the fourth etchant can be selected such that the etching rates of the second dielectric layer 256 in the openings of different dimensions are similar. Thus, the openings having different dimensions will terminate at the same level (e.g., terminate at the top surface of the lower contact member) at the end of the fourth etching process. In another example, the power, composition, and flow rate of the second etchant are selected such that the MIM structures 260 exposed in the openings of different dimensions are etched at approximate etching rates. At the end of the second etching process, the openings having different dimensions terminate at the same level (e.g., terminate at the top surface of the third dielectric layer 258).

[0102] The methods and semiconductor devices obtained according to the present disclosure provide several advantages. For example, the method of the present disclosure results in a substantially linear tapered profile of the opening, so that the barrier layer and / or seed layer of the upper contact member formed in the opening is compliant, which improves the reliability level to prevent the metal fill layer from penetrating into the MIM structure, thus avoiding voltage breakdown. In addition, the method of the present disclosure can simultaneously fabricate upper contact members having different dimensions, thereby saving manufacturing time and / or cost.

[0103] One aspect of the present disclosure relates to a method of manufacturing a semiconductor device. The method includes providing a workpiece. The workpiece includes a substrate, a first dielectric layer above the substrate, a lower contact member, vertically extending through the first dielectric layer, a second dielectric layer, above the lower contact member and the first dielectric layer, a third dielectric layer, above the second dielectric layer, a metal-insulator-metal (MIM) structure, above the third dielectric layer, and a fourth dielectric layer, above the metal-insulator-metal structure. The method further includes performing a first etching process to form an opening that extends through the fourth dielectric layer to expose the metal-insulator-metal structure, performing a second etching process to extend the opening through the metal-insulator-metal structure to expose the third dielectric layer, performing a third etching process to further extend the opening into the third dielectric layer, and performing a fourth etching process to further extend the opening through the third dielectric layer and the second dielectric layer to expose the lower contact member. The first etching process includes a first etchant, the second etching process includes a second etchant, and the third etching process and the fourth etching process include a third etchant. The first etchant and the third etchant include fluorine, the second etchant does not include fluorine, and the step of performing the fourth etching process includes applying a non-zero bias power and a non-zero source power to the workpiece.

[0104] In some embodiments, the non-zero bias power ranges from about 200 watts (W) to about 1000 watts, and the non-zero source power ranges from about 200 watts to about 1000 watts. In some embodiments, the method further includes performing a first cleaning process after performing the third etching process, performing a second cleaning process after performing the fourth etching process, and forming a contact via through the opening to directly contact the lower contact member. In some embodiments, the step of performing the second cleaning process includes applying a cleaning solution containing hydrogen peroxide and a copper protectant to the workpiece, and the copper protectant includes an azole compound, an amine compound, or a combination thereof. In some embodiments, the second etchant includes hydrogen chloride (HCl), silicon tetrachloride (SiCl 4 ), carbon tetrachloride (CCl 4 ), chloroform (CHCl 3 ), boron trichloride (BCl 3 ), tungsten pentachloride (WCl 5 ), or a combination thereof. In some embodiments, the lower contact member includes copper. In some embodiments, the steps of performing the first etching process and the second etching process include applying a second bias power and a second source power to the workpiece, the second bias power is greater than the non-zero bias power, and the second bias power ranges from about 1000 watts to about 3000 watts, and the second source power is greater than the non-zero source power, and the second source power ranges from about 1000 watts to about 3000 watts. In some embodiments, the first etchant and the third etchant each include sulfur hexafluoride (SF 6) Nitrogen trifluoride (NF 3 ) Difluoromethane (CH 2 F 2 ) Trifluoromethane (CHF 3 ) Octafluorocyclobutane (C 4 F 8 ) Hexafluoroethane (C 2 F 6 ) Carbon tetrafluoride (CF 4 ) or a combination of the above. In some embodiments, the second dielectric layer comprises silicon carbonitride (SiCN), and the third and fourth dielectric layers comprise silicon nitride (SiN). In some embodiments, the metal-insulator-metal structure comprises a conductor plate layer formed of titanium nitride, tantalum nitride, titanium, or tantalum, and an insulator layer formed of zirconium oxide, hafnium oxide, aluminum oxide, tantalum oxide, silicon oxide, or titanium oxide.

[0105] Another aspect of the present disclosure relates to a method of manufacturing a semiconductor device. The method includes providing a workpiece. The workpiece includes a substrate, a first dielectric layer, a lower contact member above the substrate and horizontally surrounded by the first dielectric layer, a second dielectric layer above the lower contact member and the first dielectric layer, a third dielectric layer above the second dielectric layer, a metal-insulator-metal (MIM) structure above the third dielectric layer, and a fourth dielectric layer above the metal-insulator-metal structure. The metal-insulator-metal structure includes an insulator layer sandwiched between two conductor plate layers. The method further includes performing a first etching process to form an opening that extends through the fourth dielectric layer and the metal-insulator-metal structure and into the third dielectric layer, performing a second etching process to extend the opening through the third dielectric layer and the second dielectric layer to expose the lower contact member, and performing a cleaning process such that after the cleaning process, the insulator layer protrudes from the two conductor plate layers. The first etching process includes a first etchant containing chlorine, the second etching process includes a second etchant without chlorine, and the step of performing the second etching process includes applying a non-zero bias power and a non-zero source power to the workpiece.

[0106] In some embodiments, in the cleaning process, the two conductor plate layers are etched at an etching rate greater than that of the insulator layer. In some embodiments, the steps of performing the cleaning process include laterally expanding the opening. In some embodiments, the lower contact component is the first lower contact component and the opening is the first opening. The workpiece further includes a second lower contact component horizontally surrounded by a first dielectric layer. A second dielectric layer is further located above the second lower contact component. The steps of performing the first etching process further form a second opening that extends through the fourth dielectric layer and the metal-insulator-metal structure and extends into the third dielectric layer. The steps of performing the second etching process further extend the second opening through the third dielectric layer and the second dielectric layer to expose the second lower contact component. The first opening and the second opening have different sizes.

[0107] Another aspect of the present disclosure relates to a semiconductor device including a lower contact component above a substrate, a first dielectric layer above the lower contact component, a metal-insulator-metal (MIM) structure above the first dielectric layer, a second dielectric layer above the metal-insulator-metal structure, and a conductive component that extends through the second dielectric layer, the metal-insulator-metal structure, and the first dielectric layer and is electrically coupled to the lower contact component. The metal-insulator-metal structure includes a first conductor plate layer, a second conductor plate layer, and an insulator layer between the first conductor plate layer and the second conductor plate layer. The conductive component interfaces with the first conductor plate layer at a first interface and interfaces with the second conductor plate layer at a second interface. The insulator layer extends more than about 5 nanometers beyond the first interface and the second interface, and the insulator layer directly contacts the conductive component on the top, bottom, and side surfaces of the insulator layer.

[0108] In some embodiments, the insulator layer includes a high dielectric constant dielectric material. In some embodiments, the first interface and the second interface are respectively curved towards the first conductor plate layer and the second conductor plate layer. In some embodiments, the first conductor plate layer and the second conductor plate layer include titanium nitride (TiN). In some embodiments, the conductive component interfaces with the first dielectric layer at a first sidewall, interfaces with the metal-insulator-metal structure at a second sidewall, and interfaces with the second dielectric layer at a third sidewall. The second sidewall forms a second angle with the bottommost surface of the metal-insulator-metal structure, the third sidewall forms a first angle with the topmost surface of the metal-insulator-metal structure, and the difference between the first angle and the second angle is less than about 10 degrees. In some embodiments, the first sidewall forms a third angle with the top surface of the lower contact component, and the difference between the first angle and the third angle is less than about 5 degrees.

[0109] The foregoing outlines the features of several embodiments so that those skilled in the art to which the present utility model pertains can better understand the viewpoints of the embodiments of the present utility model. Those skilled in the art to which the present utility model pertains should understand that other processes and structures can be easily designed or modified based on the embodiments of the present utility model to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art to which the present utility model pertains should also understand that such equivalent structures do not depart from the spirit and scope of the present utility model, and various changes, substitutions, and replacements can be made without departing from the spirit and scope of the present utility model. Therefore, the protection scope of the present utility model shall be defined by the appended claims.

Claims

1. A semiconductor device, characterized in that: include: a lower contact member on top of a substrate; a first dielectric layer over the lower contact member; a metal-insulator-metal structure over the first dielectric layer; a second dielectric layer over the metal-insulator-metal structure; as well as a conductive member extending through the second dielectric layer, the metal-insulator-metal structure and the first dielectric layer and electrically coupled to the lower contact member, The metal-insulator-metal structure includes a first conductor plate layer, a second conductor plate layer above the first conductor plate layer, and an insulator layer between the first conductor plate layer and the second conductor plate layer. The conductive component intersects with the first conductor plate layer at a first interface, and the conductive component intersects with the second conductor plate layer at a second interface, The insulator layer extends beyond the first interface and the second interface by a distance greater than 5 nanometers, and the insulator layer directly contacts the conductive components on the top, bottom and side surfaces of the insulator layer.

2. The semiconductor device according to claim 1, wherein The first interface and the second interface are bent toward the first conductor plate layer and the second conductor plate layer respectively.

3. The semiconductor device according to claim 1, wherein: The conductive component intersects the first dielectric layer on a first sidewall, the conductive component intersects the metal-insulator-metal structure on a second sidewall, and the conductive component intersects the second dielectric layer on a third sidewall, The second side wall and a bottom surface of the metal-insulator-metal structure form a second angle, the third side wall and a top surface of the metal-insulator-metal structure form a first angle, and the difference between the first angle and the second angle is less than 10 degrees.

4. The semiconductor device according to claim 3, wherein: The first side wall and a top surface of the lower contact component form a third angle, and a difference between the first angle and the third angle is less than 5 degrees.

5. The semiconductor device according to claim 1, wherein: The thickness of the insulator layer ranges from 4 nm to 20 nm.

6. The semiconductor device according to claim 1, wherein: The ratio of the distance that the insulator layer extends beyond the first interface and the second interface to the thickness of the insulator layer is in a range of 0.2 to 5.

7. The semiconductor device according to claim 1, wherein The ratio of the distance that the insulator layer extends beyond the first interface and the second interface to the thickness of the insulator layer is in a range of 0.5 to 2.

8. The semiconductor device according to claim 1, wherein The distance that the insulator layer extends beyond the first interface is greater than or equal to the distance that the insulator layer extends beyond the second interface.

9. The semiconductor device according to claim 1, wherein: The distance that the insulator layer extends beyond the first interface and the second interface ranges from 5 nm to 20 nm.

10. The semiconductor device according to claim 1, wherein The distance that the insulator layer extends beyond the first interface and the second interface ranges from 5 nm to 15 nm.

11. The semiconductor device according to claim 1, wherein The distance that the insulator layer extends beyond the first interface and the second interface ranges from 5 nm to 10 nm.

12. The semiconductor device according to claim 1, wherein In a top view, the conductive component has a circular shape, an elliptical shape, a racetrack shape, or a polygonal shape.

13. The semiconductor device according to claim 1, wherein: In a top view, the conductive component has a square shape or a rectangular shape.

14. The semiconductor device according to claim 1, wherein: An upper portion of the conductive member has straight sidewalls.

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