Semiconductor device

Abstract

Various embodiments of the utility model relate to a semiconductor device and a manufacturing method. In an embodiment, a semiconductor device may include a first semiconductor die; an oxide layer on the first semiconductor die, wherein the first semiconductor die has a first top surface opposite the oxide layer; a first insulating material encapsulating the first semiconductor die and the oxide layer, wherein the first insulating material has a second top surface coplanar with the first top surface; a first polymer buffer is disposed between a sidewall of the first semiconductor die and a sidewall of the oxide layer, wherein the first polymer buffer has a third top surface coplanar with both the first top surface and the second top surface.

Description

Technical Field

[0001] Embodiments of the present utility model relate to a semiconductor device. Background Art

[0002] Due to the continuous increase in the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.), the semiconductor industry has experienced rapid growth. In most cases, the increase in integration density is due to the iterative reduction of the minimum feature size, which allows more components to be integrated into a given area. With the growing demand for shrinking electronic devices, there is also a demand for smaller and more innovative semiconductor die packaging technologies. An example of such a packaging system is the Package-on-Package (PoP) technology. In a PoP device, a top semiconductor package is stacked on top of a bottom semiconductor package to achieve a high level of integration and component density. PoP technology is generally capable of producing semiconductor devices with enhanced functions and occupying less space on a printed circuit board (PCB). Summary of the Utility Model

[0003] According to an embodiment, a semiconductor device includes a first semiconductor die, an oxide layer on the first semiconductor die, wherein the first semiconductor die has a first top surface opposite to the oxide layer, a first insulating material encapsulating the first semiconductor die and the oxide layer, wherein the first insulating material has a second top surface flush with the first top surface, and a first polymer buffer disposed between the sidewall of the first semiconductor die and the sidewall of the first insulating material, wherein the first polymer buffer has a third top surface flush with the first top surface and the second top surface.

[0004] According to an embodiment, a semiconductor device includes a first semiconductor die, a first polymer buffer surrounding the first semiconductor die, and a first insulating layer surrounding the first polymer buffer, wherein the first polymer buffer extends horizontally along the sidewall of the first semiconductor die from a level of a first flat top surface of the first semiconductor die to a level of a flat bottom surface of the first semiconductor die. Description of the Drawings

[0005] Aspects of the present disclosure will be best understood when read in conjunction with the following detailed description with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0006] Figure 1 、 2 3, 4, 5, 6A, 6B, 7, 8, 9, 10, 11, and 12 show various views of intermediate steps of manufacturing a semiconductor package according to some embodiments.

[0007] Figure 13 、 14 Figures 15A, 15B, 16, 17A, 17B, 18, 19, 20, 21, 22, and 23 illustrate cross-sectional and top-down plan views of steps for forming an integrated circuit package in accordance with some embodiments. DETAILED DESCRIPTION

[0008] The following disclosure provides several different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and not limiting. For example, the formation of a first feature over or above a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Further, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments or configurations discussed.

[0009] In addition, for ease of description, spatially relative terms, such as "below", "beneath", "under", "above", "over", and the like, may be used herein to describe one element or feature's relationship to another element(s) or feature(s) as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0010] According to some embodiments, a buffer structure is formed around a semiconductor die in an integrated circuit package to reduce the risk of corner crack propagation due to structural stress induced during integrated circuit package manufacturing. By forming a buffer structure around each semiconductor die, where the buffer structure is less brittle than the gap fill material (also referred to as insulating material) used between semiconductor dies, the risk of corner crack propagation can be reduced, and non-bond stress can be reduced by approximately thirty percent. Incorporating the buffer structure may help improve the functionality and integrity of stacked dies through stress absorption provided by the buffer structure.

[0011] Figure 1A cross-sectional view is shown of one or more first integrated circuit dies 50 bonded to a first bonding layer 101 of a first carrier substrate 100 according to some embodiments. According to some embodiments, the first carrier substrate 100 comprises silicon or the like. The first bonding layer 101 may include oxides, such as silicon oxide, silicon oxynitride, etc. or combinations thereof, and may be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system followed by post-curing to convert it to an oxide), atomic layer deposition (ALD), physical vapor deposition (PVD), etc. or combinations thereof. Other oxide materials formed by any acceptable process may be used to form the first bonding layer 101 on the first carrier substrate 100.

[0012] According to some embodiments, the first integrated circuit die 50 may be a bare chip semiconductor die (e.g., an unpackaged semiconductor die). For example, the first integrated circuit die 50 may be a logic die (e.g., an AP, a central processing unit, a microcontroller, etc.), a memory die (e.g., a Dynamic Random-Access Memory (DRAM) die, a hybrid memory cube (HBC), a wide input / output (wideIO) memory die, a magnetoresistive random access memory (mRAM) die, a resistive random access memory (rRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), a biomedical die, etc.

[0013] The first integrated circuit die 50 can be processed according to an applicable manufacturing process to form an integrated circuit in the first integrated circuit die 50. For example, the first integrated circuit dies 50 can each include an active layer of a first semiconductor substrate 51 (e.g., doped or undoped silicon) or a semiconductor-on-insulator (SOI) substrate. The first semiconductor substrate 51 can include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multi-layer or gradient substrates, can also be used.

[0014] Devices (e.g., transistors, diodes, capacitors, resistors, or the like) can be formed in and / or on the first semiconductor substrate 51 and can be interconnected by a first interconnect structure 53 including first metallization patterns 55 (e.g., wires and vias) in one or more first interconnect dielectric layers 57 to form one or more integrated circuits. The first interconnect dielectric layers 57 can include silicon oxide, silicon nitride, silicon oxynitride, polymers, or the like and are deposited by PVD, CVD, ALD, etc. For example, the first metallization patterns 55 can be conductive features formed in the first interconnect dielectric layers 57 by a damascene process.

[0015] Additionally, the first integrated circuit die 50 may include one or more through silicon vias (TSVs) 59 extending into the first semiconductor substrate 51 of the first integrated circuit die 50 to provide a fast path for data signals. In an embodiment, the TSVs 59 may be formed by first forming TSV openings into the first semiconductor substrate 51 (e.g., before active device formation). The TSV openings may be formed by applying and developing a suitable photoresist (not shown) and removing portions of the first semiconductor substrate 51 exposed to a desired depth. The TSV openings may be formed to extend into the first semiconductor substrate 51 at least further than the active devices formed within and / or on the first semiconductor substrate 51 and may extend to a greater depth than the final desired height of the first semiconductor substrate 51. Once the TSV openings have been formed within the first semiconductor substrate 51, the TSV openings may be lined with a substrate. The substrate may be, for example, silicon nitride or an oxide formed from tetraethylorthosilicate (TEOS), but any suitable dielectric material may alternatively be used. A plasma enhanced chemical vapor deposition (PECVD) process may be used to form the substrate, but other suitable processes, such as physical vapor deposition or thermal processes, may alternatively be used.

[0016] Once a substrate has been formed along the sidewalls and bottom of the TSV openings, a barrier layer (also not shown separately) may be formed and the remaining portions of the TSV openings may be filled with a first conductive material. The first conductive material may include copper, but other suitable materials, such as aluminum, alloys, doped polysilicon, combinations thereof, etc., may alternatively be used. The first conductive material may be formed by electroplating copper onto a seed layer (not shown), filling, and overfilling the TSV openings. Once the TSV openings have been filled, the excess substrate, barrier layer, seed layer, and first conductive material outside the TSV openings may be removed by a planarization process such as chemical mechanical polishing (CMP), although any suitable removal process may be used.

[0017] According to some embodiments, the second bonding layer 103 may be deposited on the so-called active side or the front side of the first integrated circuit die 50. The front side of the active side / first integrated circuit die 50 may refer to the side of the first semiconductor substrate 51 on which active devices are formed. The back side of the first integrated circuit die 50 may refer to the side of the first semiconductor substrate 51 opposite to the active side / front side. In some embodiments, the second bonding layer 103 may be an oxide, such as silicon oxide, silicon oxynitride, etc. or a combination thereof, and may be formed by HDP-CVD, FCVD, CVD, ALD, PVD, etc. or a combination thereof. Other oxide materials formed by any acceptable process may be used to form the second bonding layer 103 on the first integrated circuit die 50.

[0018] In an embodiment, one or more first integrated circuit dies 50 may be bonded to the first carrier substrate 100 through a first dielectric-to-dielectric bonding process (e.g., oxide-to-oxide bonding), forming a first dielectric-to-dielectric bond (e.g., oxide-to-oxide bond). The first dielectric-to-dielectric bond may start by activating the first bonding layer 101 and / or the second bonding layer 103, and then applying pressure, heat, and / or other bonding process steps to connect the first bonding layer 101 to the surface of the second bonding layer 103. Activation of the first bonding layer 101 and the second bonding layer 103 may be performed using, for example, dry processing, wet processing, plasma processing, exposure to H2, exposure to N2, exposure to O2, combinations of these, etc. In an embodiment using wet processing, for example, the RCA cleaning process may be used. Activation helps the first dielectric-to-dielectric bond of the first bonding layer 101 and the second bonding layer 103, for example, allowing the use of lower pressure and temperature in the subsequent first dielectric-to-dielectric bonding process. Through this treatment, the number of OH groups on the surface of the first bonding layer 101 and / or the second bonding layer 103 increases. After the surfaces of the first bonding layer 101 and / or the second bonding layer 103 are activated, the first bonding layer 101 and the second bonding layer 103 may be brought into contact with each other at a relatively low temperature (e.g., room temperature) to form a weak bond. Subsequently, annealing is performed to strengthen the weak bond and form the first dielectric-to-dielectric bond. During annealing, the H of the OH bond is degassed, thereby forming a Si-O-Si bond between the first bonding layer 101 and the second bonding layer 103, thus strengthening the bond.

[0019] Figure 2A cross-sectional view is shown of a first buffer material 201 formed over a first carrier substrate 100 covering one or more first integrated circuit dies 50, in accordance with some embodiments. In an embodiment, the first buffer material 201 may include a polymer, such as a photosensitive polymer, polyimide, etc. In an embodiment, the first buffer material 201 may include HD4100, HD8820, FujiLTC9320-E07, Toray LT-S8300A, HD7100, Asahi BL301, a benzocyclobutene (BCB)-based material, a polybenzoxazoles (PBO)-based material, etc. or a combination thereof. In an embodiment, the first buffer material 201 may be formed by spin coating the first buffer material 201 over the first carrier substrate 100 and one or more first integrated circuit dies 50. However, any suitable material may be used to form the first buffer material 201. According to some embodiments, the first buffer material 201 may have a first toughness in the range of 10 J / m 3 to 1,000 J / m 3 . If the toughness of the first buffer material 201 is less than the first toughness, the first buffer material 201 may be too brittle and have an undue risk of crack propagation. If the toughness of the first buffer material 201 is greater than the first toughness, the first buffer material 201 may not be rigid enough to provide sufficient support for subsequent processing steps performed on the first buffer material 201.

[0020] Figure 3A cross-sectional view of a patterning process 300 of a first buffer material 201 for removing excess portions of the first buffer material 201 around one or more first integrated circuit dies 50 on a first carrier substrate 100 is shown, in accordance with some embodiments. In an embodiment, the first buffer material 201 may be a photosensitive material, such as any of the above materials that can be patterned using a photomask. For example, the first buffer material 201 may be patterned by exposing the first buffer material 201 to light passing through a photomask and developing the first buffer material 201 after exposure to remove the exposed / unexposed portions of the first buffer material 201, depending on whether the first buffer material 201 is a positive photosensitive material or a negative photosensitive material. According to some embodiments, after the patterning process 300, the excess portions of the first buffer material 201 have been removed from above the first carrier substrate 100, while the remaining portions of the first buffer material 201 surround the sidewalls and top surface of the one or more first integrated circuit dies 50. In an embodiment, the patterning process 300 is performed such that the remaining portions of the first buffer material 201 have a first width W1 around the sidewalls of each first integrated circuit die 50 in the range of 1 micron to 30 microns. If the first width W1 of the first buffer material 201 is less than 1 micron, the first buffer material 201 may not be able to sufficiently absorb the stress generated during subsequent manufacturing processes to sufficiently reduce the risk of non-bonding crack propagation (e.g., stress generated due to forming additional devices on the first integrated circuit die 50). If the first width W1 of the first buffer material 201 is greater than 30 microns, the first buffer material 201 may not be able to provide sufficient structural support for the first integrated circuit die 50 during subsequent manufacturing processes.

[0021] Figure 4 A cross-sectional view of the formation of a first barrier layer 401 covering one or more first integrated circuit dies 50 above the first carrier substrate 100 and above the first buffer material 201 is shown, in accordance with some embodiments. In an embodiment, the first barrier layer 401 includes silicon nitride or the like. In an embodiment, a suitable deposition process (such as CVD, ALD, HDPCVD, combinations thereof, etc.) may be used to deposit the first barrier layer 401. However, any suitable material and deposition process may be utilized to form the first barrier layer 401.

[0022] Figure 5A cross-sectional view of a first gap-fill material 501 (also referred to as an insulating material) over a first barrier layer 401 is shown in accordance with some embodiments. According to some embodiments, the first gap-fill material 501 can be an oxide, such as silicon oxide (e.g., silicon dioxide), etc. The first gap-fill material 501 can be formed by spin coating, HDPCVD, etc. In some embodiments, the first gap-fill material 501 is formed to overfill one or more first integrated circuits 50 and fill any gaps between the one or more first integrated circuits 50. According to some embodiments, the first gap-fill material 501 has a second toughness that is less than the first toughness. In such embodiments, the first gap-fill material 501 is more brittle than the first buffer material 201 (e.g., the first buffer material 201 can be more flexible than the first gap-fill material 501 and can absorb more stress before deformation). In some embodiments, the first gap-fill material 501 may also have a greater geometric stiffness than the first buffer material 201. In some embodiments, the geometric stiffness of the first gap-fill material 501 provides structural stability for subsequent processing steps performed over the first gap-fill material 501. In some embodiments, the geometric stiffness of the first gap-fill material 501 is greater than the geometric stiffness of the first buffer material 201, and the geometric stiffness of the first gap-fill material 501 can help provide additional rigidity to compensate for the flexibility of the first buffer material 201.

[0023] Figure 6AA cross-sectional view or is shown of performing a first planarization process 600 on a first gap-fill material 501, a first barrier layer 401, a first buffer material 201, and one or more first integrated circuit dies 50 according to some embodiments. In an embodiment, the first planarization process 600 may be a chemical mechanical polishing (CMP) planarization process. In an embodiment, the first planarization process 600 removes portions of the first gap-fill material 501, portions of the first barrier layer 401, portions of the first buffer material 201, and portions of the first semiconductor substrate 51 of the one or more first integrated circuit dies 50. In some embodiments, the first planarization process 600 further exposes TSVs 59 within the first semiconductor substrate 51 of the one or more first integrated circuit dies 50. Additionally, in an embodiment, after the first planarization process 600, portions of the first buffer material 201 covering each of the one or more first integrated circuit dies 50 are removed, forming first buffer structures 601 that completely surround each of the sidewalls of the first integrated circuit dies 50. In an embodiment, the first buffer structures 601 have a first width W1 and may maintain the same toughness as the first buffer material 201, as toughness is a material property associated with the material of the first buffer structures 601. Additionally, after the first planarization process 600, the first gap-fill material 501, the first barrier layer 401, the first integrated circuit dies 50, and the first buffer structures 601 all share a first planar top surface. Further, the first planarization process 600 that results in the formation of the first buffer structures 601 establishes a first bottom device layer 670 on which subsequent layers, integrated circuit dies, and associated structures may be formed.

[0024] Figure 6B A top-down plan view is shown of after performing a first planarization process 600 on a first gap-fill material 501, a first barrier layer 401, a first buffer material 201, and one or more first integrated circuit dies 50 that results in the formation of the first buffer structures 601 according to some embodiments. As Figure 6B shown, each first buffer structure 601 completely surrounds each first integrated circuit die 50, and each first buffer structure 601 is in direct physical contact with each first integrated circuit die 50. Each first buffer structure 601 also each has a first width W1 measured from the sidewall of the first integrated circuit die 50 to the outer sidewall of the first buffer structure 601. Additionally, each first barrier layer 401 is in direct contact with the sidewalls of each first buffer structure 601 and completely surrounds each first buffer structure 601. The first gap-fill material 501 fills the remaining gaps between different first integrated circuit dies 50 and the associated first buffer structures 601 and the associated first barrier layers 401.

[0025] In an embodiment, by providing a structure that spans the height of integrated circuit die 50 across a corner of adjacent integrated circuit die 50, the advantages of being able to absorb stresses and strains that may occur in subsequent processing steps can be achieved through first buffer structure 601. The increased toughness of first buffer structure 601 surrounding integrated circuit die 50 can allow for strain absorption, thereby reducing the risk of corner crack propagation at the corners of first integrated circuit die 50 or non-bonding formation along the edges of first integrated circuit die 50. The geometric rigidity provided by first gap fill material 501 can effectively support the overlying device layer by providing rigidity to the structure, thereby complementing the absorption ability of first buffer structure 601.

[0026] Figure 7 A cross-sectional view is shown of forming third bonding layer 700 above the first flat top surface of first bottom device layer 670 according to some embodiments. In an embodiment, third bonding layer 700 may include first dielectric layer 701 and first bonding pads 703 embedded within first dielectric layer 701. In some embodiments, first bonding pads 703 may include a conductive material such as copper and the like. Some of first bonding pads 703 may be physically and electrically coupled to TSV 59. In an embodiment, first dielectric layer 701 may include a silicon-containing dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or the like, and first dielectric layer 701 may be deposited using a suitable deposition process such as CVD, PVD, ALD, HDPCVD, a combination of these, or the like. First bonding pads 703 may be formed within first dielectric layer 701 or formed prior to first dielectric layer 701 using any suitable process such as damascene process, electroplating, or the like.

[0027] For example, in an embodiment where first dielectric layer 701 is formed prior to forming first bonding pads 703, openings corresponding to the positions of first bonding pads 703 may be formed in first dielectric layer 701 using a combination of photolithography and etching processes. Once the openings have been formed within first dielectric layer 701, the openings may be filled with a seed layer (not shown separately) and plate metal to form first bonding pads 703 within first dielectric layer 701. The seed layer may be deposited blanketly over the top surface of first dielectric layer 701 and portions of the underlying exposed conductive layer and the sidewalls of the openings. Depending on the desired material, the seed layer may include a copper layer. The seed layer may be deposited using a process such as sputtering, evaporation, or plasma enhanced chemical vapor deposition (PECVD), or the like. The plate metal may be deposited over the seed layer by an electroplating process such as electroplating or electroless plating. The plate metal may include copper, copper alloy, or the like.

[0028] As another example, in an embodiment where the first dielectric layer 701 is formed after the first bonding pad 703 is formed, the seed layer can be deposited conformally over the first integrated circuit die 50, the first buffer structure 601, the first barrier layer 401, and the first gap fill material 501. A photoresist (not shown separately) can be formed and patterned to define the layout of the first bonding pad 703, and an electroplating process can be applied to form the plate metal in the opening of the photoresist. Subsequently, the photoresist and the portions of the seed layer not covered by the plate metal can be removed, and the remaining portion of the seed layer and the plate metal form the first bonding pad 703. Then the first dielectric layer 701 is deposited around the first bonding pad 703.

[0029] Optionally, a planarization step can then be performed to planarize the top surfaces of the first bonding pad 703 and the third bonding layer 700 such that the third bonding layer 700 has a high degree of flatness with the first bonding pad 703. Other materials and formation methods are also possible.

[0030] Figure 8 A cross-sectional view showing the second integrated circuit die 850 bonded to the third bonding layer 700 is shown. In an embodiment, the second integrated circuit die 850 can be substantially similar to the first integrated circuit die 50. In some embodiments, a fourth bonding layer 800 is formed over the active side / front side of the second integrated circuit die 850. The fourth bonding layer 800 can include a second dielectric layer 801 and second bonding pads 803 embedded within the second dielectric layer 801. In an embodiment, the second dielectric layer 801 and the second bonding pads 803 can be formed of materials similar to and in a manner similar to the first dielectric layer 701 and the first bonding pads 703, respectively.

[0031] According to some embodiments, the second integrated circuit die 850 is bonded to the fourth bonding layer 800 through the third bonding layer 700 by a dielectric-to-dielectric and metal-to-metal bonding process performed between the third bonding layer 700 and the fourth bonding layer 800 and is bonded to the first integrated circuit die 50. In some embodiments, the dielectric-to-dielectric bonding process forms a direct bond (e.g., oxide-to-oxide bond) between the first dielectric layer 701 and the second dielectric layer 801. Additionally, the metal-to-metal bonding process can directly bond the first bonding pad 703 of the third bonding layer 700 to the second bonding pad 803 of the fourth bonding layer 800 through direct metal-to-metal bonding. Thus, the electrical connection between the first integrated circuit die 50 and the second integrated circuit die 850 can be provided by the physical connection of the first bonding pad 703 to the second bonding pad 803, where some of the second bonding pads 803 are electrically coupled to the first metallization pattern 55 within the second integrated circuit die 850. The dielectric-to-dielectric bonding process can begin with a surface treatment of one or both of the first dielectric layer 701 and the second dielectric layer 801 to facilitate the dielectric-to-dielectric bonding (e.g., oxide-to-oxide bonding) between the first dielectric layer 701 and the second dielectric layer 801. The surface treatment can include plasma treatment. The plasma treatment can be performed in a vacuum environment. After the plasma treatment, the surface treatment can further include a cleaning process (e.g., rinsing with deionized water or the like) that can be applied to one or both of the first dielectric layer 701 and the second dielectric layer 801. Then, the dielectric-to-dielectric and metal-to-metal bonding process can continue to align the second bonding pad 803 of the fourth bonding layer 800 with the first bonding pad 703 of the third bonding layer 700. Next, the dielectric-to-dielectric and metal-to-metal bonding process includes a pre-bonding step during which the fourth bonding layer 800 of the second integrated circuit die 850 contacts the third bonding layer 700. The pre-bonding can be performed at room temperature (e.g., between about 21°C and about 25°C). The dielectric-to-dielectric and metal-to-metal bonding process continues to perform annealing at a temperature between, for example, about 150°C and about 400°C for a duration between about 0.5 hours and about 3 hours such that the first bonding pad 703 (e.g., copper) and the second bonding pad 803 (e.g., copper) diffuse into each other, thus forming a direct metal-to-metal bond.

[0032] Figure 9A cross-sectional view showing the formation of a second buffer structure 901, a second barrier layer 903, and a second gap-fill material 905 around a second integrated circuit die 850 is shown. According to some embodiments, after forming the second buffer structure 901, the second barrier layer 903, and the second gap-fill material 905, a second planarization process 900 may be performed to expose the TSV 59 of the second integrated circuit die 850 that passes through the first semiconductor substrate 51 of the second integrated circuit die 850. Additionally, in some embodiments, the second planarization process may planarize the top surface of the second integrated circuit die 850, the TSV 59 of the second integrated circuit die 850, the second buffer structure 901, the second barrier layer 903, and the second gap-fill material 905 such that the top surfaces of the features are coplanar. In an embodiment, the formation of the second buffer structure 901, the second barrier layer 903, and the second gap-fill material 905 and the second planarization process 900 may be performed in a substantially similar manner as previously discussed with respect to the first buffer structure 601, the first barrier layer 401, the first gap-fill material 501, and the first planarization process 600, and for simplicity, will not be described herein again. In an embodiment, the processes performed are on a third bonding layer 700 rather than on the first bonding layer 101 or the first carrier substrate 100. Thus, a first intermediate device layer 970 including the second integrated circuit die 850, the second buffer structure 901, the second barrier layer 903, and the second gap-fill material 905 may be formed. Additionally, it should be noted that the cycle of forming the first intermediate device layer 970 may be repeated multiple times to form an expected number of stacked device layers.

[0033] Figure 10 A cross-sectional view showing the formation of a first top device layer 1070 formed above the first intermediate device layer 970 according to some embodiments is shown. In an embodiment, the first top device layer 1070 includes a third integrated circuit die 1050 that is substantially similar to the first integrated circuit die 50, except that the formation of the TSV 59 within the third integrated circuit die 1050 may be omitted in the third integrated circuit die 1050. In an embodiment, the first top device layer 1070 includes a third buffer structure 1001, a third barrier layer 1003, and a third gap-fill material 1005 processed with a third planarization process 1000.

[0034] In an embodiment, the formation of the first top device layer 1070 may be formed in a substantially similar manner as previously discussed with respect to the first intermediate device layer 970. However, during the third planarization process 1000 of the third integrated circuit die 1050, if the TSV 59 is not formed within the third integrated circuit die 1050 or the first semiconductor substrate 51 of the third integrated circuit die 1050 is not thinned, the planarization of the third integrated circuit die 1050 will not expose the TSV 59. It should be noted again that althoughFigure 10 Only one first intermediate device layer 970 below the first top device layer 1070 is shown, but any number of first intermediate device layers 970 can be formed before forming the first top device layer 1070. In some embodiments, the first intermediate device layer 970 can be completely omitted.

[0035] Figure 11 A cross-sectional view is shown of a second carrier substrate 1100 attached to the first top device layer 1070 to remove the first carrier substrate 100 according to some embodiments. In an embodiment, the second carrier substrate 1100 can be attached to the first top device layer 1070 through an attachment layer 1101. In an embodiment, the attachment layer 1101 can be a bonding layer that is bonded to a dielectric material (e.g., a third gap-fill material 1005 or an oxide layer deposited separately above the third gap-fill material 1005) through dielectric-to-dielectric bonding (e.g., oxide-to-oxide bonding). In another embodiment, the attachment layer 1101 can be an attachment film (e.g., an adhesive, a die attach film (DAF), or the like) for attaching the second carrier substrate 1100 to the first top device layer 1070.

[0036] In an embodiment, after attaching the second carrier substrate 1100 to the first top device layer 1070, a fourth planarization process 1130 can be performed to remove the first carrier substrate 100. In some embodiments, the fourth planarization process 1130 can be a CMP planarization process, an etch-back process, a combination thereof, etc. However, any suitable planarization process can be utilized. Additionally, according to some embodiments, the fourth planarization process 1130 further removes the first bonding layer 101 along a horizontal main axis perpendicular to the first intermediate device layer 970, removes a portion of the first buffer structure 601, thins a portion of the second bonding layer 103, and removes a portion of the first barrier layer 401. In another embodiment, the fourth planarization process removes the first carrier substrate 100, removes the first bonding layer 101, thins the first barrier layer 401, and thins the second bonding layer 103.

[0037] In an embodiment, the second carrier substrate 1100 provides structural support during the fourth planarization process 1130. After the fourth planarization process 1130, the first barrier layer 401, the first gap-fill material 501, the first buffer structure 601, and the first integrated circuit die 50 (including the second bonding layer 103) share a first planar bottom surface. Additionally, in an embodiment, the first buffer structure 601 may have a first height H1 in the range between 15 microns and 30 microns (e.g., where the height of the first integrated circuit die 50 including the second bonding layer 103 is in the range between 15 microns and 30 microns). However, the first height of the first buffer structure 601 can be any height suitable for matching the height of the first integrated circuit die 50. Additionally, in some embodiments, the second buffer structure 901 and the third buffer structure 1001 may also have the first height H1. In an embodiment, the first height H1 of each buffer structure can be at least the height of the corresponding integrated circuit die (e.g., the first integrated circuit die 50, the second integrated circuit die 850, and the third integrated circuit die 1050). If the height of any one buffer structure is less than the first height H1 (e.g., less than the height of the corresponding integrated circuit die), the subsequently formed structure may apply strain to other structures (e.g., the corresponding integrated circuit die) before contacting the buffer structure, thereby potentially increasing the risk of corner crack propagation or the risk of non-bonding at the corners of the associated integrated circuit die. If the height of any buffer structure is greater than the first height H1 (e.g., greater than the height of the corresponding integrated circuit die), then the subsequently formed structure may apply excessive strain on the buffer structure, causing the buffer structure to deform.

[0038] Figure 12 A cross-sectional view showing the formation of the redistribution structure 1200 on the first planar bottom surface of the first bottom device layer 670 is presented. In an embodiment, the redistribution structure 1200 is formed on the opposite side of the first integrated circuit die 50 from the first planar bottom surface. Additionally, Figure 12 Also shown is a die connector 1250 formed through the second bonding layer 103 of the first integrated circuit die 50, which allows for physical and electrical coupling of the redistribution structure 1200 to the first integrated circuit die 50. According to some embodiments, the redistribution structure 1200 is electrically coupled to the first integrated circuit die 50, the second integrated circuit die 850, and the third integrated circuit die 1050.

[0039] In an embodiment, an opening (not shown separately) is formed through a thinning portion of the second bonding layer 103, thereby exposing a first metallization pattern 55 within the first integrated circuit die 50. A die connector 1250, such as a conductive pillar (formed of a metal such as copper, for example), extends through the opening in the second bonding layer 103 and is physically and electrically coupled to the first metallization pattern 55 within the first integrated circuit die 50. The die connector 1250 can be formed, for example, by electroplating or the like.

[0040] In addition, in an embodiment, the redistribution structure 1200 includes a redistribution dielectric layer 1201 and a redistribution metallization pattern 1203. The redistribution metallization pattern 1203 can also be referred to as a redistribution layer or redistribution line. The redistribution structure 1200 is shown as an example having one layer of metallization pattern. More dielectric layers and metallization patterns can be formed in the redistribution structure 1200. If more dielectric layers and metallization patterns are to be formed, the steps and processes discussed below can be repeated. In some embodiments, the redistribution structure 1200 can be completely omitted.

[0041] In an embodiment, the redistribution metallization pattern 1203 is then formed. The redistribution metallization pattern 1203 includes conductive elements extending along a main surface of a first flat bottom surface to physically and electrically couple to the die connector 1250. As an example of forming the redistribution metallization pattern 1203, a seed layer is formed above the first flat bottom surface of the first bottom device layer 670. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including sub-layers formed of multiple different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer located above the titanium layer. The seed layer can be formed using, for example, PVD or the like. Then, a photoresist is formed and patterned on the seed layer. The photoresist can be formed by spin coating or the like and can be exposed to light for patterning. The pattern of the photoresist corresponds to the redistribution metallization pattern 1203. The patterning forms openings through the photoresist to expose the seed layer. Then, a conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be formed by plating, such as electroplating or electroless plating, etc. The conductive material can include metals such as copper, titanium, tungsten, aluminum, etc. The combination of the conductive material and the underlying portions of the seed layer forms the redistribution metallization pattern 1203. The photoresist and the portions of the seed layer on which the conductive material is not formed are removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma or the like. Once the photoresist is removed, the exposed portions of the seed layer are removed, for example, by using an acceptable etching process, such as wet or dry etching.

[0042] In an embodiment, a redistribution dielectric layer 1201 is deposited over the redistribution metallization pattern 1203 and along a first flat bottom surface. In some embodiments, the redistribution dielectric layer 1201 is formed of a photosensitive material such as PBO, polyimide, BCB, or the like, which can be patterned using a photolithography mask. The redistribution dielectric layer 1201 can be formed by spin coating, lamination, CVD, etc., or a combination thereof. Then, the redistribution dielectric layer 1201 is patterned. The patterning forms openings that expose portions of the redistribution metallization pattern 1203. Such patterning can be performed by an acceptable process. For example, when the redistribution dielectric layer 1201 is a photosensitive material, it can be patterned by exposing and developing the redistribution dielectric layer 1201, or by etching using a method such as anisotropic etching.

[0043] After patterning of the redistribution dielectric layer 1201, an under bump metallization (UBM) 1205 is formed for external connection to the redistribution structure 1200 and the integrated circuit dies 50, 850, and 1050 thereon. The UBM 1205 has a bump portion on and extending along a major surface of the redistribution dielectric layer 1201, and has a via portion extending through the redistribution dielectric layer 1201 to physically and electrically couple to the redistribution metallization pattern 1203. This electrically couples the UBM 1205 to the first integrated circuit die 50. The UBM 1205 can be formed of the same material as the redistribution metallization pattern 1203. In some embodiments, the UBM 1205 has a different size from the redistribution metallization pattern 1203.

[0044] In addition, in an embodiment, the conductive connection member 1207 is formed on the UBM 1205. The conductive connection member 1207 can be a ball grid array (BGA) connector, solder ball, metal pillar, controlled collapse chip connection (C4) bump, micro-bump, bump formed by electroless nickel - electroless palladium - immersion gold technique (ENEPIG), etc. The conductive connection member 1207 can include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc. or a combination thereof. In some embodiments, the conductive connection member 1207 is formed by a solder layer formed first through evaporation plating, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer is formed structurally, tempering can be performed to shape the material into a desired bump shape. In another embodiment, the conductive connection member 1207 includes a metal pillar (such as a copper pillar) formed by sputtering, printing, electroplating, electroless plating, CVD, etc. The metal pillar can be solderless and have substantially vertical sidewalls. In some embodiments, a metal capping layer is formed on top of the metal pillar. The metal capping layer can include nickel, tin, tin - lead, gold, silver, palladium, indium, nickel - palladium - gold, nickel - gold, etc. or a combination thereof, and can be formed by a plating process.

[0045] In addition, in an embodiment, a singulation process 1270 can be performed along a saw street 1271 in a related first bottom device layer 670, and the related first intermediate device layer 970 and the related first top device layer 1070 can be encapsulated in subsequent processing to form an integrated circuit package (not shown separately). According to some embodiments, the singulation process can be a sawing process, however, any suitable singulation process can be utilized. Additionally, in some embodiments, the second carrier substrate 1100 can optionally also be removed.

[0046] Figures 13 to 23 Another embodiment is shown, in which a barrier layer is directly deposited above the integrated circuit die before forming the buffer structure, such that the buffer structure is disposed between the gap - filling material and the barrier layer. In Figures 13 to 23 this document, unless otherwise specified, like reference numerals denote like elements formed by processes similar to Figures 1 to 12 those.

[0047] Figure 13 A cross - sectional view is shown, in which one or more first integrated circuit dies 50 are bonded to a first carrier substrate 100 and a first barrier layer 401 is deposited. In an embodiment, the bonding of one or more first integrated circuit dies 50 to the first carrier substrate 100 can be performed in a manner similar to that described above with respect to Figure 1performed in a similar manner as discussed. In an embodiment, after bonding one or more first integrated circuit dies 50 to the first carrier substrate 100, a first barrier layer 401 may be formed over one or more first integrated circuit dies 50 and the first bonding layer 101 of the first carrier substrate 100. In an embodiment, the formation of the first barrier layer 401 may be performed in a similar manner as with the similar materials discussed above with respect to Figure 4 except that the first barrier layer 401 is formed before the formation of the first buffer material 201 (see Figure 14 ). It should be noted that, Figure 13 in the structure shown, for example, the first integrated circuit die 50, may include similar components and be formed of similar materials and by similar processes as discussed above.

[0048] Figure 14 A cross-sectional view is shown in which the first buffer material 201 is formed over the first barrier layer 401. In the embodiment, the first buffer material 201 may be formed of similar materials and by similar methods as those discussed above with respect to Figure 2 except that the first buffer material 201 is formed over the first barrier layer 401 and is in direct contact with the first barrier layer 401. In an embodiment, the first buffer material 201 may include a polymer, such as a photosensitive polymer, polyimide, etc. In an embodiment, the first buffer material 201 may include HD4100, HD8820, Fuji LTC9320-E07, Toray LT-S8300A, HD7100, Asahi BL301, benzocyclobutene (BCB)-based materials, polybenzoxazole (PBO)-based materials, etc. or a combination thereof. According to some embodiments, the first buffer material 201 may have a first toughness. If the toughness of the first buffer material 201 is less than the first toughness, the first buffer material 201 may be too brittle and have an undue risk of crack propagation. If the toughness of the first buffer material 201 is greater than the first toughness, the rigidity of the first buffer material 201 may not be sufficient to provide adequate support for subsequent processing steps performed on the first buffer material 201.

[0049] Figure 15A A cross-sectional view of the patterning process 300 of the first buffer material 201 is shown to remove the excess portions of the first buffer material 201 around one or more first integrated circuit dies 50 over the first carrier substrate 100. In an embodiment, the patterning process 300 of the first buffer material 201 may be performed in a similar manner as discussed above with respect to Figure 3 The first width W1 of the first buffer material 201 may be measured from the sidewall of the first barrier layer 401 to the outer sidewall of the first buffer material 201.

[0050] Figure 15BShows a top-down plan view after the patterning process 300 of the first buffer material 201. In an embodiment, after the patterning process 300, the first barrier layer 401 covers the top surface of the first integrated circuit die 50 (not shown in Figure 15B ), and the main surface of the first bonding layer 101 that is not covered by the first integrated circuit die 50 (not shown in Figure 15B ). In this embodiment, the first buffer material 201 covers the top surface of the first integrated circuit die 50 that is covered by the first barrier layer 401. In an embodiment, the first buffer material also covers a portion of the first barrier layer 401 located on the first bonding layer 101 by a first width W1, which extends from one side of the sidewall of the first barrier layer 401, and this side is on the other side where the first barrier layer 401 covers the first integrated circuit chip 50.

[0051] Figure 16 Shows a cross-sectional view of the first gap-fill material 501 above the first buffer material 201 and the exposed portion of the first barrier layer 401. In an embodiment, the first gap-fill material 501 can be formed in a similar manner with a similar material as discussed above regarding Figure 5 . In some embodiments, the first gap-fill material 501 may also have greater geometric rigidity than the first buffer material 201. In some embodiments, the geometric rigidity of the first gap-fill material 501 provides structural stability for subsequent processing steps performed above the first gap-fill material 501. In some embodiments, the geometric rigidity of the first gap-fill material 501 is greater than that of the first buffer material 201, and the geometric rigidity of the first gap-fill material 501 can help provide additional rigidity to compensate for the flexibility of the first buffer material 201.

[0052] Figure 17A Shows a cross-sectional view of performing the first planarization process 600 on the first gap-fill material 501, the first barrier layer 401, the first buffer material 201, and one or more first integrated circuit dies 50. In an embodiment, the first planarization process 600 is performed in a manner similar to that discussed above regarding Figure 6A , and makes the top surface of the first gap-fill material 501, the top surface of the first barrier layer 401, and the top surface of the resulting first buffer structure 601 substantially flat. In addition, the first planarization process 600 establishes the second bottom device layer 1770, on which subsequent layers and associated structures of the integrated circuit die can be formed.

[0053] Figure 17BA top-down plan view of a first buffer structure 601 is shown after a first planarization process 600 is performed on a first gap-fill material 501 (not shown separately), a first barrier layer 401, a first buffer material 201, and one or more first integrated circuit dies 50, all of which are on a first carrier substrate 100. In this embodiment, each first barrier layer 401 completely surrounds each first integrated circuit die 50, and each first barrier layer 401 is in direct physical contact with each first integrated circuit die 50. The first buffer structure 601 then completely surrounds each first barrier layer 401, and each first barrier layer 401 surrounds each of the one or more first integrated circuit dies 50. The first buffer structure 601 also each has a first width W1 extending from the sidewall of the first barrier layer 401 opposite the first integrated circuit die 50. The first gap-fill material 501 fills the remaining gaps between different first integrated circuit dies 50 and the associated first buffer structure 601 and the associated first barrier layer 401.

[0054] Figure 18 A cross-sectional view is shown of a third bonding layer 700 formed over a first planar top surface of a second bottom device layer 1770. In an embodiment, the third bonding layer 700 can include a first dielectric layer 701 and a first bonding pad 703 embedded within the first dielectric layer 701. In this embodiment, the first dielectric layer 701 and the first bonding pad 703 can be formed of similar materials and in a similar manner as discussed above with respect to Figure 7 discussed.

[0055] Figure 19 A cross-sectional view is shown of the bonding of a second integrated circuit die 850 to the third bonding layer 700. In an embodiment, the second integrated circuit die 850 can be substantially similar to the first integrated circuit die 50. In some embodiments, a fourth bonding layer 800 is formed over the active side / front side of the second integrated circuit die 850. The fourth bonding layer 800 can include a second dielectric layer 801 and a second bonding pad 803 embedded within the second dielectric layer 801. In an embodiment, the second dielectric layer 801 and the second bonding pad 803 can be formed of similar materials and in a similar manner as the first dielectric layer 701 and the first bonding pad 703, respectively. In an embodiment, the second integrated circuit die 850 can be bonded to the second bottom device layer 1770 in a similar manner as discussed above with respect to Figure 8 discussed, thereby resulting in similar features.

[0056] Figure 20A cross-sectional view showing the formation of a second buffer structure 901, a second barrier layer 903, and a second gap-fill material 905 around a second integrated circuit die 850 is shown. According to some embodiments, after the formation of the second buffer structure 901, the second barrier layer 903, and the second gap-fill material 905, a second planarization process 900 may be performed. In an embodiment, the formation of the second buffer structure 901, the second barrier layer 903, and the second gap-fill material 905 and the second planarization process 900 may be performed in a substantially similar manner as discussed with reference to Figures 13 to 17B the previously discussed first buffer structure 601, first barrier layer 401, first gap-fill material 501, and first planarization process 600. Additionally, it should be noted that the cycle of forming the second intermediate device layer 2070 may be repeated a suitable number of times to form a desired number of stacked device layers.

[0057] Figure 21 A cross-sectional view showing the formation of a second top device layer 2170 formed over the second intermediate device layer 2070 is shown. In an embodiment, the second top device layer 2170 includes a third integrated circuit die 1050 that is substantially similar to the first integrated circuit die 50, except that the formation of the TSVs 59 within the third integrated circuit die 1050 may be omitted. Additionally, the first top device layer 1070 includes a third buffer structure 1001, a third barrier layer 1003, and a third gap-fill material 1005 that are processed with a third planarization process 1000. The formation of the first top device layer 1070 may be formed in a substantially similar manner as discussed previously with respect to Figures 13 to 20 the second intermediate device layer 2070 in, and in a manner similar to the formation of the first top device layer 1070.

[0058] In addition, in an embodiment, the first buffer structure 601 may have a first height H1 in the range between 15 microns and 30 microns (e.g., the height of the first integrated circuit die 50 including the second bonding layer 103 is in the range between 15 microns and 30 microns). However, the first height H1 of the first buffer structure 601, the second buffer structure 901, and the third buffer structure 1001 may be a height such that the top surface in the buffer structure is flush with the top surface of the corresponding integrated circuit die. In an embodiment, considering that the buffer structure may be formed above the barrier layer, the first height H1 of each buffer structure may be at least the height of the corresponding integrated circuit die (e.g., the first integrated circuit die 50, the second integrated circuit die 850, and the third integrated circuit die 1050). If the height of any one buffer structure is less than the first height H1 (e.g., the height is less than the corresponding integrated circuit die), the subsequently formed structure may apply strain to other structures (e.g., the corresponding integrated circuit die) before contacting the buffer structure, thereby potentially increasing the risk of corner crack propagation or the risk of non-bonding at the corners of the relevant integrated circuit die. If any buffer structure has a height greater than the first height H1 (e.g., greater than the height of the corresponding integrated circuit die), then the subsequently formed structure may apply excessive strain on the buffer structure, causing the buffer structure to deform.

[0059] Figure 22 A cross-sectional view is shown of the second carrier substrate 1100 attached to the second top device layer 2170 to facilitate the removal of the first carrier substrate 100. In an embodiment, the second carrier substrate 1100 may be attached in a similar manner as previously discussed with respect to Figure 11 discussed. Figure 23 Also shown is a fourth planarization process 1130 in a similar manner as previously discussed with respect to Figure 11 discussed.

[0060] Figure 23 A cross-sectional view is shown of the formation of the redistribution structure 1200 above the first flat bottom surface of the second bottom device layer 1770 and the formation of the die connector 1250. In an embodiment, the die connector 1250 may be formed in a similar manner using similar materials as previously discussed with respect to Figure 12 discussed. In an embodiment, the redistribution structure 1200 includes a redistribution dielectric layer 1201 and a redistribution metallization pattern 1203, which may be formed in a similar manner using similar materials as previously discussed with respect to Figure 12 discussed. In an embodiment, the UBM 1205 and the conductive connector 1207 may be formed in a similar manner using similar materials as previously discussed with respect to Figure 12 discussed.

[0061] In addition, in an embodiment, a singulation process 1270 may be performed along a saw street 1271, and each integrated circuit die in the associated second bottom device layer 1770, the associated second intermediate device layer 2070, and the associated second top device layer 2170 may be encapsulated in a subsequent process to form an integrated circuit package (not shown separately) in a manner similar to that discussed previously with respect to Figure 12 As discussed. According to some embodiments, the singulation process 1270 may be a sawing process, although any suitable singulation process may be utilized. Additionally, in some embodiments, the second carrier substrate 1100 may optionally also be removed.

[0062] Other features and processes may also be included. For example, test structures may be included to assist in the verification testing of 3D packages or 3DIC components. The test structures may include, for example, test pads formed in the redistribution layer or on the substrate, which allow for the testing, probing, and / or use of a probe card of the 3D package or 3DIC component and the like. Verification testing may be performed on the intermediate structure as well as the final structure. Additionally, the structures and methods disclosed herein may be used in combination with test methods including intermediate verification of known good dies to improve yield and reduce cost.

[0063] Advantages may be achieved in embodiments. According to some embodiments, including a first buffer structure 601 may allow for the absorption of stress that may be caused by strain from an additional semiconductor die (e.g., a second integrated circuit die 850) added above another semiconductor die (e.g., a first integrated circuit die 50) surrounded by the first buffer structure 601. The stress reduced due to the inclusion of the first buffer structure 601 may also reduce the risk of non-bonding at the corners of the die during smiling die fabrication. An additional buffer structure surrounding the overlying die (e.g., a second buffer structure 901 surrounding the second integrated circuit die 850) may additionally help reduce the risk of stress on a subsequently stacked die (e.g., a third integrated circuit die 1050). Absorbing the stress generated due to the inclusion of the buffer structure may help improve manufacturing integrity and device functionality.

[0064] According to an embodiment, a semiconductor device includes a first semiconductor die, an oxide layer on the first semiconductor die, wherein the first semiconductor die has a first top surface opposite the oxide layer, a first insulating material encapsulating the first semiconductor die and the oxide layer, wherein the first insulating material has a second top surface flush with the first top surface, and a first polymer buffer disposed between the sidewall of the first semiconductor die and the sidewall of the first insulating material, wherein the first polymer buffer has a third top surface flush with the first top surface and the second top surface. In an embodiment, a silicon nitride layer is further included between the sidewall of the first semiconductor die and the sidewall of the first polymer buffer, wherein the silicon nitride layer has a fourth top surface flush with both the first top surface and the third top surface. In an embodiment, a silicon nitride layer is further included between the sidewall of the first insulating material and the sidewall of the first polymer buffer, wherein the silicon nitride layer has a fourth top surface flush with both the second top surface and the third top surface. In an embodiment, the first polymer buffer has a first width, and the first width is in the range of 1 micron to 30 microns. In an embodiment, the first polymer buffer includes polyimide having a first toughness, and the first insulating material includes an oxide having a second toughness less than the first toughness. In an embodiment, a first bonding layer is further included above the first top surface, the second top surface, and the third top surface, a second bonding layer bonded to the first bonding layer by metal-to-metal and dielectric-to-dielectric bonding, a second semiconductor die above the second bonding layer, a second insulating material encapsulating the second semiconductor die, and a second polymer buffer between the sidewall of the second insulating material and the sidewall of the second semiconductor die. In an embodiment, conductive features within the oxide layer and a redistribution structure opposite the first semiconductor die above the oxide layer are further included, wherein the redistribution structure is electrically coupled to the first semiconductor die through the conductive features.

[0065] According to an embodiment, a method of manufacturing a semiconductor device includes forming a dielectric-to-dielectric bond between a first oxide layer of a first semiconductor die and a second oxide layer of a carrier substrate, spin-coating a photosensitive polymer over the carrier substrate, the photosensitive polymer covering the first semiconductor die, patterning the photosensitive polymer to form a buffer layer from the photosensitive polymer, wherein the buffer layer surrounds the first semiconductor die, depositing an oxide material over the buffer layer, and performing a first planarization process over the oxide material and the buffer layer to expose the first semiconductor die, wherein after the planarization process the first semiconductor die, the buffer layer, and the oxide material share a planar top surface. In an embodiment, a second planarization process is also included, wherein the second planarization process removes portions of the carrier substrate and the first oxide layer. In an embodiment, a second semiconductor die is also included that is bonded to the planar top surface, wherein the second semiconductor die is electrically coupled to the first semiconductor die. In an embodiment, a support substrate is also included that is attached above the second semiconductor die opposite the first semiconductor die. In an embodiment, a silicon nitride layer is also included that is deposited along a sidewall of the first semiconductor die over the carrier substrate before spin-coating the photosensitive polymer. In an embodiment, a silicon nitride layer is further included that is deposited along a sidewall of the buffer layer over the carrier substrate before depositing the oxide material. In an embodiment, a first toughness of the buffer layer is greater than a second toughness of the oxide material.

[0066] According to an embodiment, a semiconductor device includes a first semiconductor die, a first polymer buffer surrounding the first semiconductor die, and a first insulating layer surrounding the first polymer buffer, wherein the first polymer buffer extends horizontally from a level of a first planar top surface of the first semiconductor die along a sidewall of the first semiconductor die to a level of a planar bottom surface of the first semiconductor die. In an embodiment, a second semiconductor die bonded to the first semiconductor die, a second polymer buffer surrounding the second semiconductor die, and a second insulating layer surrounding the second polymer buffer are also included, wherein the second insulating layer, the second polymer buffer, and the second semiconductor die share a second planar top surface that is parallel to the first planar top surface. In an embodiment, the first polymer buffer includes a photosensitive polyimide. In an embodiment, the first polymer buffer is less brittle than the first insulating layer. In an embodiment, a silicon nitride layer is also included that is disposed between the first polymer buffer and the first insulating layer, wherein the silicon nitride layer surrounds the first semiconductor die. In an embodiment, a silicon nitride layer is also included that is disposed between the first semiconductor die and the first polymer buffer, wherein the silicon nitride layer surrounds the first semiconductor die.

[0067] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other methods and structures for achieving the same purposes and / or attaining the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent configurations do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: include: a first semiconductor die; an oxide layer on the first semiconductor die, wherein the first semiconductor die has a first top surface opposite the oxide layer; a first insulating material encapsulating the first semiconductor die and the oxide layer, wherein the first insulating material has a second top surface flush with the first top surface; as well as A first polymer buffer is disposed between a sidewall of the first semiconductor die and a sidewall of the first insulating material, wherein the first polymer buffer has a third top surface flush with both the first top surface and the second top surface.

2. The semiconductor device according to claim 1, further comprising A silicon nitride layer is disposed between the sidewall of the first semiconductor die and the sidewall of the first polymer buffer, wherein the silicon nitride layer has a fourth top surface flush with both the first top surface and the third top surface.

3. The semiconductor device according to claim 1, further comprising A silicon nitride layer is disposed between the sidewall of the first insulating material and the sidewall of the first polymer buffer, wherein the silicon nitride layer has a fourth top surface flush with the second top surface and the third top surface. 4 . The semiconductor device of claim 1 , wherein the first polymer buffer comprises a polyimide having a first toughness, and wherein the first insulating material comprises an oxide having a second toughness less than the first toughness.

5. The semiconductor device according to claim 1, further comprising: a first bonding layer over the first top surface, the second top surface, and the third top surface; a second bonding layer bonded to the first bonding layer via metal-to-metal and dielectric-to-dielectric bonding; a second semiconductor die over the second bonding layer; a second insulating material encapsulating the second semiconductor die; as well as A second polymer buffer is between the sidewalls of the second insulating material and the sidewalls of the second semiconductor die.

6. The semiconductor device according to claim 1, further comprising: conductive features within the oxide layer; as well as A redistribution structure is above the oxide layer and opposite the first semiconductor die, wherein the redistribution structure is electrically coupled to the first semiconductor die through the conductive features.

7. A semiconductor device, characterized in that: include: a first semiconductor die; a first polymer buffer surrounding said first semiconductor die; as well as A first insulating layer surrounds the first polymer buffer, wherein the first polymer buffer extends along the sidewalls of the first semiconductor die from the level of a first planar top surface of the first semiconductor die to the level of a bottom surface of the first semiconductor die.

8. The semiconductor device according to claim 7, further comprising: a second semiconductor die bonded to the first semiconductor die; a second polymer buffer surrounding the second semiconductor die; as well as A second insulating layer surrounds the second polymer buffer, wherein the second insulating layer, the second polymer buffer and the second semiconductor die share a second flat top surface, and the second flat top surface is parallel to the first flat top surface. 9 . The semiconductor device of claim 7 , further comprising a silicon nitride layer disposed between the first polymer buffer and the first insulating layer, wherein the silicon nitride layer surrounds the first semiconductor die. 10 . The semiconductor device of claim 7 , further comprising a silicon nitride layer disposed between the first semiconductor die and the first polymer buffer, wherein the silicon nitride layer surrounds the first semiconductor die.

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