Oscillator

Abstract

The utility model provides an oscillator. The oscillator comprises a first capacitor; a second capacitor; the oscillation comparator comprises a first input end coupled to a node A, a second input end for receiving a reference voltage and an output end; the oscillation logic circuit comprises a control end coupled with the output end of the oscillation comparator, a first output end for outputting a first control signal and a second output end for outputting a second control signal; the current source is used for injecting current into the node A; the first switch combination comprises a first switch and a second switch; the first switch is coupled between the node A and a first connecting end of the first capacitor; the second switch is coupled between a first connecting end of the second capacitor and a grounding end; and the second switch combination comprises a third switch coupled between the node A and the first connecting end of the second capacitor and a fourth switch coupled between the first connecting end of the first capacitor and the grounding end. The first control signal is used for controlling the first switch and the second switch to be switched on or off synchronously, and the second control signal is used for controlling the third switch and the fourth switch to be switched on or off synchronously. Therefore, a more accurate oscillation signal can be obtained.

Description

Technical Field

[0001] The utility model relates to the field of circuit design, in particular to an oscillator.

Background Art

[0002] Many electronic circuits require the frequency f or the reference time (T = 1 / f) of the oscillator to remain stable during process, voltage, and temperature (PVT) variations.

[0003] For low-cost solutions, on-chip components (transistors, resistors, capacitors) are preferred instead of using off-chip time / reference frequencies such as crystal resonators or oscillators. Figure 1 An oscillator that generates an oscillation signal is shown, which includes a current source I1, a capacitor C, a switch S1, an oscillation comparator 110, and a flip-flop 120. The current source I1 is formed based on a voltage source V cs and a resistor R, and the current I it provides is I = V cs / R. The oscillation frequency of the oscillator mainly depends on two components, a resistor (the resistor forming the current source I1) and a capacitor C. Figure 2 Shown is Figure 1 the waveform diagram of the signals at each node of the oscillator in

[0004] The period T PER of this oscillator is:

[0005] where V REF is the voltage value of the reference voltage received at one input terminal of the oscillation comparator 110, V cs is the voltage value of the voltage source forming the current source I1, T RESET is the width of the high level of the comparison signal output by the oscillation comparator, and the T RESET is the reset time, during which the electric energy of the capacitor C can be completely released by using the switch S1.

[0006] Further note: The oscillation frequency generated by the oscillator is: f OSC = 1 / T PEE . When V CAP intersects with V REF , the rising edge generated by the comparator triggers the flip-flop 120, causing the oscillation signal V OSC to flip. The oscillation signal V OSC is the output signal of the oscillator and has a duty cycle of 50%.

[0007] The ratio within the chip can be set to be precise and temperature-independent, for example, by using matched resistors to generate V REF and Vcs , or V can also be selected REF and V CS are equal, and this α is 1.

[0008] Reset time (T RESET ) is determined by the speed of the oscillation comparator and the time required to discharge the capacitor. The oscillation comparator can be a hysteresis comparator, such that after the comparison signal flips to a high level, it can remain high for a period of time before flipping to a low level, which is the reset time. This reset time can vary with temperature, thus reducing the accuracy of the oscillation frequency. Especially for oscillators with a relatively high oscillation frequency, since the reset time accounts for a larger proportion of the total cycle time T PER (= 1 / f OSC ), it is more difficult to ensure its accuracy.

[0009] Therefore, there is an urgent need to propose a new technical solution to solve the above problems.

Utility Model Content

[0010] One object of the present utility model is to provide an oscillator whose oscillation signal has higher accuracy.

[0011] According to one aspect of the present utility model, the present utility model provides an oscillator, which includes: a first capacitor; a second capacitor; an oscillation comparator, which includes a first input terminal coupled to node A, a second input terminal receiving a reference voltage, and an output terminal; an oscillation logic circuit, which includes a control terminal coupled to the output terminal of the oscillation comparator, a first output terminal outputting a first control signal, and a second output terminal outputting a second control signal; a current source injecting current into node A; a first switch combination, which includes a first switch coupled between node A and the first connection end of the first capacitor and a second switch coupled between the first connection end of the second capacitor and the ground terminal; a second switch combination, which includes a third switch coupled between node A and the first connection end of the second capacitor and a fourth switch coupled between the first connection end of the first capacitor and the ground terminal; the first control signal is used to control the first switch and the second switch to conduct or cut off synchronously, the second control signal is used to control the third switch and the fourth switch to conduct or cut off synchronously, when the first switch and the second switch are conducting, the third switch and the fourth switch are cut off, and when the third switch and the fourth switch are conducting, the first switch and the second switch are cut off.

[0012] In one embodiment, the oscillator further includes an unlocking circuit. The unlocking circuit includes: a lock comparator, which includes a first input terminal coupled to node A, a second input terminal receiving a locking threshold voltage, and an output terminal. When the voltage at the first input terminal is higher than the locking threshold voltage, the lock comparator outputs a valid illegal signal; otherwise, it outputs an invalid illegal signal; an unlocking logic circuit, which generates an unlocking signal according to the illegal signal output by the lock comparator and outputs it to the reset terminal or the set terminal of the oscillation logic circuit to unlock the oscillation logic circuit.

[0013] In one embodiment, when the illegal signal is valid, a valid unlocking signal is generated and sent to the reset terminal or the set terminal of the oscillation logic circuit to unlock the oscillation logic circuit, so that the first control signal and the second control signal are flipped. When the illegal signal is invalid, an invalid unlocking signal is generated and sent to the reset terminal or the set terminal of the oscillation logic circuit.

[0014] Compared with the prior art, the present utility model uses the first switch combination and the second switch combination to charge and discharge two capacitors respectively, so that the voltage of node A can be instantaneously reduced from the reference voltage to the initial value. Therefore, the time required to discharge the capacitor (reset time) is no longer part of the oscillation period, thus improving the accuracy of the oscillation signal.

[0015] Furthermore, an unlocking circuit is added to the vibrator in the present utility model. When the oscillator is locked, it is forced to unlock, so that the oscillator starts oscillating again.

Description of the Drawings

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present utility model. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts. Among them:

[0017] Figure 1 It is a schematic circuit diagram of a typical oscillator for generating an oscillation signal;

[0018] Figure 2 For Figure 1 the waveform diagram of the signals of each node of the oscillator in

[0019] Figure 3 It is a schematic circuit diagram of the oscillator in the first embodiment of the present utility model;

[0020] Figure 4 For Figure 3 the waveform diagram of the signals of each node of the oscillator in

[0021] Figure 5 This is a schematic diagram of the circuit structure of the oscillator in the second embodiment of the present utility model.

Specific Embodiments

[0022] To make the above objects, features, and advantages of the present utility model more obvious and understandable, the present utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0023] As used herein, the term "one embodiment" or "embodiment" refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present utility model. The phrase "in one embodiment" that appears in different places in this specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment that is mutually exclusive with other embodiments. Unless otherwise specified, the terms indicating electrical connection such as "connected", "coupled", and "joined" in this article all mean direct or indirect electrical connection.

[0024] In the present utility model, unless otherwise clearly defined and limited, terms such as "connected", "coupled", and "joined" should be understood in a broad sense; for example, it may be a direct connection or an indirect connection through an intermediate medium, and the intermediate medium may be electronic components, functional circuits, etc. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific circumstances.

[0025] Figure 3 This is a schematic diagram of the circuit structure of the oscillator in the first embodiment of the present utility model. Figure 4 For Figure 3 the waveform diagram of the signals of each node of the oscillator in. As Figure 3 shown, the oscillator includes a first capacitor C1, a second capacitor C2, an oscillation comparator 310, an oscillation logic circuit 320, a current source I1, a first switch combination, and a second switch combination.

[0026] The oscillation comparator 310 includes a first input terminal coupled to node A, a second input terminal receiving a reference voltage V REF , and an output terminal. The voltage of node A is V CAP , and the comparison signal output by the oscillation comparator is V COMP . The oscillation comparator may be a hysteresis comparator. After the comparison signal V COMP output by the oscillation comparator undergoes a jump (such as a low level to a high level), it usually remains for a period of time and then jumps back to the initial state (such as a low level).

[0027] The oscillation logic circuit 320 includes a control terminal coupled to the output terminal of the oscillation comparator 310, a first output terminal for outputting a first control signal P1, and a second output terminal for outputting a second control signal P2.

[0028] The current source I1 injects current into the node A. In one embodiment, the current source I1 is formed based on a voltage source V cs and a resistor R, and the current I it provides is I = V cs / R.

[0029] The first switch combination includes a first switch S1 coupled between the node A and the first connection end of the first capacitor C1, and a second switch S2 coupled between the first connection end of the second capacitor C2 and the ground terminal. The second connection end of the first capacitor C1 is coupled to the ground terminal. The second switch combination includes a third switch S3 coupled between the node A and the first connection end of the second capacitor C2, and a fourth switch S4 coupled between the first connection end of the first capacitor C1 and the ground terminal. The second connection end of the second capacitor C2 is coupled to the ground terminal.

[0030] The first control signal P1 is used to control the first switch S1 and the second switch S2 to conduct or cut off synchronously, and the second control signal P2 is used to control the third switch S3 and the fourth switch S4 to conduct or cut off synchronously. When the first switch S1 and the second switch S2 are conducting, the third switch S3 and the fourth switch S4 are cut off. When the third switch S3 and the fourth switch S4 are conducting, the first switch S1 and the second switch S2 are cut off.

[0031] In one embodiment, the first control signal P1 and the second control signal P2 are in anti-phase (i.e., the phase difference between the two is 180 degrees). At the transition edge of the comparison signal output by the oscillation comparator 310, the first control signal P1 and the second control signal P2 flip, and the transition edge is a rising edge or a falling edge. Preferably, the oscillation logic circuit 320 includes a flip-flop. The clock terminal of the flip-flop is coupled to the output terminal of the oscillation comparator 310, its input terminal D is coupled to its inverted output terminal (i.e., the second output terminal), its non-inverted output terminal (i.e., the first output terminal) outputs the first control signal P1, and its inverted output terminal outputs the second control signal P2. The flip-flop can be a D flip-flop, and of course, it can also be other types of flip-flops that can achieve the same function.

[0032] As Figure 4 shown, when the first switch S1 and the second switch S2 are conducting simultaneously and the third switch S3 and the fourth switch S4 are cut off simultaneously, the first connection end of the first capacitor C1 is connected to the node A. Initially, the voltage of the node A is the initial value (for example, 0V. Previously, the first capacitor C1 has been discharged by the fourth switch S4), and the current source I1 charges the first capacitor C1 through the first switch S1, and the voltage V of the node ACAP gradually increases, and the second switch S2 completely discharges the electrical energy of the second capacitor C2 (i.e., the voltage V at the first connection end of the second capacitor C2 C2 is discharged to 0). When the voltage at node A rises to the reference voltage V REF , the comparison signal V output by the oscillation comparator 310 COMP undergoes a jump (a rising edge appears). At this time, the first control signal P1 and the second control signal P2 output by the oscillation logic circuit 320 are inverted (i.e., a high level jumps to a low level, or a low level jumps to a high level), thereby controlling the first switch S1 and the second switch S2 to be cut off simultaneously, and the third switch S3 and the fourth switch S4 to be turned on simultaneously.

[0033] As Figure 4 shown, when the first switch S1 and the second switch S2 are cut off simultaneously, and the third switch S3 and the fourth switch S4 are turned on simultaneously, the first connection end of the second capacitor C2 is connected to the node A. Initially, the voltage at the node A is the initial value (for example, 0V. Previously, the second capacitor C2 has been discharged by the second switch S2), and the current source I1 charges the second capacitor C2 through the third switch S3. The voltage at the node A gradually increases, and the fourth switch S4 completely discharges the electrical energy of the first capacitor C1 (i.e., the voltage V at the first connection end of the first capacitor C1 C1 is discharged to 0). When the voltage at node A rises to the reference voltage V REF , the comparison signal V output by the oscillation comparator 310 COMP undergoes a jump (a rising edge appears). At this time, the first control signal P1 and the second control signal P2 output by the oscillation logic circuit 320 are inverted, thereby controlling the first switch S1 and the second switch S2 to be turned on simultaneously, and the third switch S3 and the fourth switch S4 to be cut off simultaneously.

[0034] By continuously repeating the above process, an oscillation signal can be continuously generated. The output of the oscillator, which is the first control signal P1 or the second control signal P2, is a good oscillation signal with a duty cycle of 50%.

[0035] In the first embodiment of the present invention, due to the switching of the first switch S1 and the third switch S3, the voltage V at node A CAP can directly jump to 0V from the reference voltage V REF . The first control signal P1 and the second control signal P2 output by the flip-flop can take effect immediately at the rising edge of the comparison signal of the oscillation comparator. The time required to discharge the capacitor (reset time T RESET ) is no longer part of the oscillation period, thus improving the accuracy of the oscillation signal.

[0036] However, in some rare cases of the oscillator in the first embodiment, the pulses of the comparison signal (which can also be called reset pulses) issued by the comparator may be missed by the flip-flop (i.e., the oscillation logic circuit). The first control signal P1 and the second control signal P2 issued by the flip-flop will continuously maintain their original states and continuously charge the capacitor connected to node A until it becomes close to the power supply voltage. At this time, the oscillation comparator will never (again) generate a reset pulse, so the oscillator enters a locked state.

[0037] To prevent potential locking situations, it is necessary to improve the oscillator in the first embodiment.

[0038] Figure 5 Schematic diagram of the circuit structure of the oscillator in the second embodiment of the present invention. Relative to Figure 3 the oscillator in Figure 5 the difference of the oscillator in

[0039] The unlocking circuit includes: a lock-up comparator 330 and an unlocking logic circuit 340.

[0040] The lock-up comparator 330 includes a first input terminal coupled to node A, a second input terminal receiving a locking threshold voltage V LOCK and an output terminal. When the voltage at the first input terminal is higher than the locking threshold V LOCK voltage, the lock-up comparator 330 outputs a valid illegal signal V ILLEGAL indicating that the oscillator has entered a locked state (or an illegal state). Otherwise, it outputs an invalid illegal signal V ILLEGAL indicating that it has not entered a locked state. Note that the locking threshold V LOCK is higher than the reference voltage V REF .

[0041] The unlocking logic circuit 340 generates an unlocking signal according to the illegal signal V ILLEGAL output by the lock-up comparator 330 and outputs it to the reset terminal or the set terminal of the oscillation logic circuit 320 to unlock the oscillation logic circuit. Specifically, when the illegal signal V ILLEGAL is valid, it generates a valid unlocking signal to the reset terminal or the set terminal of the oscillation logic circuit 320 to unlock the oscillation logic circuit, so that the first control signal P1 and the second control signal P2 are flipped. When the illegal signal V ILLEGAL is invalid, it generates an invalid unlocking signal to the reset terminal or the set terminal of the oscillation logic circuit 320. At this time, the first control signal P1 and the second control signal P2 maintain their original levels.

[0042] As Figure 5As shown, the unlocking logic circuit 340 includes: a first unlocking logic unit 341 and a second unlocking logic unit 342.

[0043] A first input terminal of the first unlocking logic unit 341 receives the illegal signal V ILLEGAL , its second input terminal receives a first control signal P1, and its output terminal is coupled to the reset terminal (RESET) of the oscillation logic circuit 320. When the illegal signal is valid (i.e., enters the locked state) and the first control signal is valid, a valid first unlocking signal is output to the reset terminal of the oscillation logic circuit 320, forcing the oscillation logic circuit 320 out of the locked state, that is, forcing the first control signal P1 and the second control signal P2 to flip, so that the control signals P1 and P2 start oscillating again, otherwise an invalid second unlocking signal is output.

[0044] A first input terminal of the second unlocking logic unit 342 receives the illegal signal, its second input terminal receives a second control signal P2, and its output terminal is coupled to the set terminal (SET) of the oscillation logic circuit. When the illegal signal is valid and the second control signal P2 is valid, a valid second unlocking signal is output to the set terminal of the oscillation logic circuit 320, forcing the oscillation logic circuit 320 out of the locked state, that is, forcing the first control signal P1 and the second control signal P2 to flip, so that the control signals P1 and P2 start oscillating again, otherwise an invalid second unlocking signal is output.

[0045] In one embodiment, when the first control signal is valid (such as high-level valid), the first switch S1 and the second switch S2 are turned on, and when the second control signal is valid, the third switch S3 and the fourth switch S4 are turned on.

[0046] As Figure 5 shown, the first unlocking logic unit 341 includes: a first logic gate 3411 and a first delay unit 3412. The first logic gate 3411 includes a first input terminal, a second input terminal and an output terminal. Its first input terminal is coupled to the output terminal of the lock comparator 330 to receive the illegal signal. The output terminal of the first logic gate is coupled to the reset terminal of the oscillation logic circuit 320, and the output terminal of the first logic gate outputs a first unlocking signal. The input terminal of the first delay unit 3412 receives the first control signal P1, and its output terminal is coupled to the second input terminal of the first logic gate 3411.

[0047] The second unlocking logic unit 342 includes: a second logic gate 3421 and a second delay unit 3422. The second logic gate 3421 includes a first input terminal, a second input terminal, and an output terminal. Its first input terminal is coupled to the output terminal of the locking comparator 330 to receive the illegal signal. The output terminal of the second logic gate 3421 is coupled to the SET terminal of the oscillation logic circuit 320. The output terminal of the first logic gate outputs a second unlocking signal. The input terminal of the second delay unit 3422 receives a second control signal P2, and its output terminal is coupled to the first input terminal of the second logic gate 3421.

[0048] The first delay unit 3412 delays the first control signal P1 for a predetermined time. The second delay unit 3422 delays the second control signal P2 for a predetermined time. This is to ensure that the set signal (second unlocking signal) or the reset signal (first unlocking signal) of the oscillation logic circuit 320 has a minimum pulse width and is long enough to implement the setting or resetting of the oscillation logic circuit 320.

[0049] Specifically, the first logic gate is a NAND gate, and the second logic gate is a NAND gate. Both the first unlocking signal and the second unlocking signal are active low and inactive high. The first control signal P1 and the second control signal P2 are active high. When the first unlocking signal is valid and the second unlocking signal is invalid, the oscillation logic circuit 320 controls its first control signal P1 to become low level and the second control signal P2 to become high level. When the second unlocking signal is valid and the first unlocking signal is invalid, the oscillation logic circuit 320 controls its first control signal P1 to become high level and the second control signal P2 to become low level.

[0050] In this way, by adding the unlocking circuit, when the oscillator enters the locked state, it can actively break away from the locked state, so that the oscillator can always generate a reliable output, thus solving the problem that the oscillation usually stops after the oscillator enters the locked state.

[0051] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification.

[0052] Although the embodiments of the present utility model have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present utility model. Those of ordinary skill in the art can make changes, modifications, and variations to the above embodiments within the scope of the present utility model.

Claims

1. An oscillator, characterized in that: It includes: a first capacitor; A second capacitor; an oscillating comparator comprising a first input terminal coupled to node A, a second input terminal receiving a reference voltage, and an output terminal; an oscillation logic circuit, comprising a control terminal coupled to the output terminal of the oscillation comparator, a first output terminal outputting a first control signal, and a second output terminal outputting a second control signal; a current source for injecting current into the node A; a first switch combination, comprising a first switch coupled between the node A and a first connection terminal of the first capacitor and a second switch coupled between the first connection terminal of the second capacitor and a ground terminal; a second switch combination, comprising a third switch coupled between the node A and the first connection terminal of the second capacitor and a fourth switch coupled between the first connection terminal of the first capacitor and a ground terminal; The first control signal is used to control the first switch and the second switch to be turned on or off synchronously, and the second control signal is used to control the third switch and the fourth switch to be turned on or off synchronously. When the first switch and the second switch are turned on, the third switch and the fourth switch are turned off, and when the third switch and the fourth switch are turned on, the first switch and the second switch are turned off.

2. The oscillator according to claim 1, characterized in that The first control signal and the second control signal are inverted, and at the transition edge of the comparison signal output by the oscillation comparator, the first control signal and the second control signal are flipped, and the transition edge is a rising edge or a falling edge. The oscillation logic circuit includes a trigger, a clock terminal of the trigger is coupled to the output terminal of the oscillation comparator, an input terminal D of the trigger is coupled to its inverting output terminal, a positive output terminal of the trigger outputs a first control signal, and an inverting output terminal of the trigger outputs a second control signal. The second connection terminal of the first capacitor is coupled to the ground terminal, and the second connection terminal of the second capacitor is coupled to the ground terminal.

3. The oscillator according to claim 1, characterized in that When the first switch and the second switch are turned on at the same time, and the third switch and the fourth switch are turned off at the same time, the voltage of the node A is initially the initial value, the current source charges the first capacitor through the first switch, the voltage of the node A gradually increases, and the second switch completely releases the electric energy of the second capacitor. When the voltage of the node A increases to the reference voltage, the comparison signal output by the oscillation comparator jumps, and at this time, the first control signal and the second control signal output by the oscillation logic circuit are flipped, so as to control the first switch and the second switch to be turned off at the same time, and the third switch and the fourth switch to be turned on at the same time. When the first switch and the second switch are turned off at the same time, and the third switch and the fourth switch are turned on at the same time, the voltage of the node A is initially the initial value, the current source charges the second capacitor through the third switch, and the voltage of the node A gradually increases. The fourth switch completely releases the electric energy of the first capacitor. When the voltage of the node A increases to the reference voltage, the comparison signal output by the oscillation comparator jumps, and at this time, the first control signal and the second control signal output by the oscillation logic circuit are flipped, thereby controlling the first switch and the second switch to be turned on at the same time, and the third switch and the fourth switch to be turned off at the same time.

4. The oscillator according to claim 3, characterized in that The comparison signal output by the oscillation comparator changes and then stays for a period of time before changing back to the initial state.

5. The oscillator according to claim 1, characterized in that It also includes an unlocking circuit, which includes: A locking comparator, comprising a first input terminal coupled to node A, a second input terminal receiving a locking threshold voltage, and an output terminal, wherein when the voltage at the first input terminal is higher than the locking threshold voltage, the locking comparator outputs a valid illegal signal, otherwise, an invalid illegal signal is output; The unlocking logic circuit generates an unlocking signal according to the illegal signal output by the locking comparator, and outputs the unlocking signal to the reset terminal or the setting terminal of the oscillation logic circuit to unlock the oscillation logic circuit.

6. The oscillator according to claim 5, characterized in that When the illegal signal is valid, a valid unlocking signal is generated to the reset end or the setting end of the oscillation logic circuit to unlock the oscillation logic circuit and force the first control signal and the second control signal to flip. When the illegal signal is invalid, an invalid unlocking signal is generated to the reset end or the setting end of the oscillation logic circuit.

7. The oscillator according to claim 6, characterized in that The unlocking logic circuit comprises: a first unlocking logic unit, wherein a first input terminal thereof receives the illegal signal, a second input terminal thereof receives the first control signal, and an output terminal thereof is coupled to a reset terminal of the oscillation logic circuit, and when the illegal signal is valid and the first control signal is valid, a valid first unlocking signal is output to the reset terminal of the oscillation logic circuit, so that the first control signal and the second control signal are flipped, otherwise an invalid second unlocking signal is output; a second unlocking logic unit, a first input terminal of which receives the illegal signal, a second input terminal of which receives the second control signal, and an output terminal of which is coupled to the setting terminal of the oscillation logic circuit, and when the illegal signal is valid and the second control signal is valid, outputs a valid second unlocking signal to the setting terminal of the oscillation logic circuit, so that the first control signal and the second control signal are flipped, otherwise outputs an invalid second unlocking signal; When the first control signal is valid, the first switch and the second switch are turned on, and when the second control signal is valid, the third switch and the fourth switch are turned on.

8. The oscillator according to claim 6, characterized in that The first unlocking logic unit comprises: A first logic gate, comprising a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the output terminal of the lock comparator to receive the illegal signal, the output terminal of the first logic gate is coupled to the reset terminal of the oscillation logic circuit, and the output terminal of the first logic gate outputs a first unlocking signal; A first delay unit, an input terminal of which receives a first control signal, and an output terminal of which is coupled to a second input terminal of the first logic gate; The second unlocking logic unit comprises: A second logic gate, comprising a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the output terminal of the lock comparator to receive the illegal signal, the output terminal of the second logic gate is coupled to the setting terminal of the oscillation logic circuit, and the output terminal of the first logic gate outputs a second unlocking signal; The second delay unit has an input terminal receiving a second control signal and an output terminal coupled to the first input terminal of the second logic gate.

9. The oscillator according to claim 8, characterized in that The first logic gate is a NAND gate, and the second logic gate is a NAND gate. The first unlock signal and the second unlock signal are effective at low level, and the first control signal and the second control signal are effective at high level. When the first unlock signal is valid and the second unlock signal is invalid, the oscillation logic circuit controls its first control signal to become a low level and the second control signal to become a high level. When the second unlock signal is valid and the first unlock signal is invalid, the oscillation logic circuit controls its first control signal to become a high level and the second control signal to become a low level.

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