Control circuit of switch matrix
By adding a single-pole single-throw switch chip to the unit link of the switch array and using the control unit to control its on and off, the problem of insufficient phase consistency and isolation in high-frequency and large broadband applications in the prior art is solved, and high isolation and small phase consistency are achieved.
Patent Information
- Application Number
- CN202422017792.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-19
- Publication Date
- 2025-06-17
- Estimated Expiration
- 2034-08-19
AI Technical Summary
In high-frequency and large broadband applications, existing switching arrays have poor phase consistency and isolation, making it difficult to meet the on and off requirements of complex signal links.
A control circuit of a switch matrix is designed. By adding a single-pole single-throw switch chip to each unit link, and using a control unit to connect it between a one-point four-point single-throw switch and a single-pole single-throw switch, the on and off of four single-pole single-throw switches.
By adding a single-pole single-throw switch chip, the isolation is increased to ≥60dB and the phase consistency is less than 10°, meeting the communication requirements for high-frequency and large broadband applications.
Smart Images
Figure CN222996535U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of switches, and particularly relates to a control circuit for a switch matrix. Background Art
[0002] With the development of information technology, the signal link of communication devices has become increasingly complex. The connection and disconnection of the signal link are generally realized by a switch matrix, and the performance requirements for the switch matrix are particularly high. Often in applications with high frequency and large bandwidth, the phase consistency and isolation of the switch matrix are very poor.
[0003] In related technologies, generally, a one-to-four switch is connected to corresponding components to realize the function of the switch array. However, the phase of the signal is determined by the wavelength and the path length of the signal passing through; the higher the signal frequency, the shorter the wavelength, and it is not easy to control the physical length of the signal link. At the same time, when using a large bandwidth, the wavelength of a high-frequency signal is shorter than that of a low-frequency signal, and it is not easy to control the consistency of the physical lengths of multiple links, often resulting in a large phase consistency deviation within a part of the bandwidth. Summary of the Utility Model
[0004] The utility model provides a control circuit for a switch matrix, aiming to solve the problems of poor control effect and poor consistency of the existing switch array.
[0005] An embodiment of the utility model provides a control circuit for a switch matrix, which includes 6 groups of unit links. Each unit link includes a one-to-four switch, 4 single-pole single-throw switches connected to the one-to-four switch, and a control unit; the control unit is connected between the one-to-four switch and the single-pole single-throw switches and is used to control the on / off of the 4 single-pole single-throw switches;
[0006] The control unit includes a decoder, a first in-phase comparator, a second in-phase comparator, a first anti-phase comparator, a second anti-phase comparator, a first AND gate chip, and a second AND gate chip; the input ends of the first AND gate chip and the second AND gate chip are used to connect a power supply, and the input end of the decoder is respectively connected to the output ends of the first AND gate chip and the second AND gate chip; the output end of the decoder is respectively connected to the input ends of the first in-phase comparator and the second in-phase comparator, the output ends of the first in-phase comparator and the second in-phase comparator are respectively connected to the control ends of the single-pole single-throw switches, and the output ends of the single-pole single-throw switches are used to connect an external load;
[0007] The output end of the decoder is respectively connected to the input ends of the first anti-phase comparator and the second anti-phase comparator, and the output ends of the first anti-phase comparator and the second anti-phase comparator are respectively connected to the control ends of the single-pole single-throw switches.
[0008] Preferably, the control circuit of the switch matrix further includes a first resistor, a second resistor, and a first capacitor. The first end of the first resistor is connected to the input end of the first AND gate chip, the second end of the first resistor is connected to the first end of the second resistor, and the second end of the second resistor is grounded; the first capacitor is connected to the power supply end of the first AND gate chip and grounded.
[0009] Preferably, the control circuit of the switch matrix further includes a third resistor, a fourth resistor, and a second capacitor. The first end of the third resistor is connected to the input end of the second AND gate chip, the second end of the third resistor is connected to the first end of the fourth resistor, and the second end of the fourth resistor is grounded; the second capacitor is connected to the power supply end of the second AND gate chip and grounded.
[0010] Preferably, the one-to-four switch includes a one-to-four switch chip, a third capacitor, a fourth capacitor, a fifth capacitor, and a sixth capacitor. The first ends of the third capacitor, the fourth capacitor, the fifth capacitor, and the sixth capacitor are respectively connected to the pins of the one-to-four switch chip, and the second ends of the third capacitor, the fourth capacitor, the fifth capacitor, and the sixth capacitor are respectively grounded; the first end of the third capacitor also serves as the first control pin of the one-to-four switch chip, and the first end of the fourth capacitor also serves as the second control pin of the one-to-four switch chip; the first control pin is connected to the input end of the single-pole single-throw switch, and the second control pin is connected to the output end of the single-pole single-throw switch.
[0011] Preferably, the 4 single-pole single-throw switches include a first single-pole single-throw switch, a second single-pole single-throw switch, a third single-pole single-throw switch, and a fourth single-pole single-throw switch; the first single-pole single-throw switch, the second single-pole single-throw switch, the third single-pole single-throw switch, and the fourth single-pole single-throw switch have the same structure.
[0012] Preferably, the single-pole single-throw switch includes a single-pole single-throw switch chip, a seventh capacitor, an eighth capacitor, a ninth capacitor, and a tenth capacitor;
[0013] The first end of the seventh capacitor is connected to the first control pin of the single-pole single-throw switch chip, the first end of the eighth capacitor is connected to the second control pin of the single-pole single-throw switch chip, and the second ends of the seventh capacitor and the eighth capacitor are respectively grounded;
[0014] The ninth capacitor is connected to the output end of the single-pole single-throw switch chip, and the tenth capacitor is connected to the input end of the single-pole single-throw switch.
[0015] Compared with the prior art, the beneficial effects of the present utility model are as follows. The control unit is connected between the one-to-four switch and the single-pole single-throw switch, and is used to control the on / off of 4 single-pole single-throw switches. The input ends of the first AND gate chip and the second AND gate chip are used to connect to the power supply. The input ends of the decoder are respectively connected to the output ends of the first AND gate chip and the second AND gate chip. The output ends of the decoder are respectively connected to the input ends of the first non-inverting comparator and the input ends of the second non-inverting comparator. The output ends of the first non-inverting comparator and the output ends of the second non-inverting comparator are respectively connected to the control ends of the single-pole single-throw switches. The output ends of the single-pole single-throw switches are used to connect to external loads. The output ends of the decoder are respectively connected to the input ends of the first inverting comparator and the input ends of the second inverting comparator. The output ends of the first inverting comparator and the output ends of the second inverting comparator are respectively connected to the control ends of the single-pole single-throw switches. In this way, the isolation degree of the one-to-four switch can only barely reach 50 dB, but by adding a single-pole single-throw switch chip to each link, the isolation degree increases to ≥ 60 dB. High isolation degree is obtained in the frequency range of 7.725 GHz to 8.5 GHz, and the phase consistency is less than 10°, meeting the equipment communication requirements of customers. Brief Description of the Drawings
[0016] The present utility model will be described in detail below with reference to the drawings. Through the detailed description in combination with the following drawings, the above or other aspects of the present utility model will become clearer and easier to understand. In the drawings:
[0017] Figure 1 is a module diagram of the control circuit of the switch matrix according to an embodiment of the present utility model;
[0018] Figure 2 is a circuit diagram of the one-to-four switch according to an embodiment of the present utility model;
[0019] Figure 3 is a circuit diagram of 4 single-pole single-throw switches according to an embodiment of the present utility model;
[0020] Figure 4 is a circuit diagram of the decoder according to an embodiment of the present utility model;
[0021] Figure 5 is a circuit diagram of the first AND gate chip according to an embodiment of the present utility model;
[0022] Figure 6 is a circuit diagram of the second AND gate chip according to an embodiment of the present utility model;
[0023] Figure 7 is a circuit diagram of the comparator according to an embodiment of the present utility model.
[0024] Among them, 1 is the one-to-four switch, 2 is the single-pole single-throw switch, and 3 is the control unit. Detailed Embodiment
[0025] In order to make the objectives, technical solutions and advantages of the present utility model clearer and more understandable, the present utility model will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present utility model and are not used to limit the present utility model.
[0026] Combined with the attached Figures 1-7 As shown, the control circuit 100 of a switch matrix provided by an embodiment of the present utility model includes 6 groups of unit links. Each unit link includes a one-to-four switch 1, 4 single-pole single-throw switches 2 connected to the one-to-four switch 1, and a control unit 3. The control unit 3 is connected between the one-to-four switch 1 and the single-pole single-throw switches 2 and is used to control the on / off of the 4 single-pole single-throw switches 2. In this way, the isolation degree of the one-to-four switch 1 can only barely reach 50 dB. However, by adding a single-pole single-throw switch chip U1 to each link, the isolation degree increases to ≥60 dB. High isolation degree is obtained in the frequency range of 7.725 GHz to 8.5 GHz, and the phase consistency is less than 10°, meeting the equipment communication requirements of customers.
[0027] The control unit 3 includes a decoder U33, a first in-phase comparator U34, a second in-phase comparator U37, a first anti-phase comparator U35, a second anti-phase comparator U36, a first AND gate chip U31, and a second AND gate chip U32. The input ends of the first AND gate chip U31 and the second AND gate chip U32 are used to connect to a power supply. The input end of the decoder U33 is respectively connected to the output ends of the first AND gate chip U31 and the second AND gate chip U32. The output end of the decoder U33 is respectively connected to the input end of the first in-phase comparator U34 and the input end of the second in-phase comparator U37. The output ends of the first in-phase comparator U34 and the second in-phase comparator U37 are respectively connected to the control ends of the single-pole single-throw switches 2, and the output ends of the single-pole single-throw switches 2 are used to connect to an external load.
[0028] The output end of the decoder U33 is respectively connected to the input end of the first anti-phase comparator U35 and the input end of the second anti-phase comparator U36. The output ends of the first anti-phase comparator U35 and the second anti-phase comparator U36 are respectively connected to the control ends of the single-pole single-throw switches 2.
[0029] In this embodiment, the control circuit 100 of the switch matrix further includes a first resistor R1, a second resistor R2, and a first capacitor C1. The first end of the first resistor R1 is connected to the input end of the first AND gate chip U31. The second end of the first resistor R1 is connected to the first end of the second resistor R2, and the second end of the second resistor R2 is grounded. The first capacitor C1 is connected to the power supply end of the first AND gate chip U31 and is grounded.
[0030] In this embodiment, the control circuit 100 of the switch matrix further includes a third resistor R3, a fourth resistor R4, and a second capacitor C2. The first end of the third resistor R3 is connected to the input end of the second AND gate chip U32. The second end of the third resistor R3 is connected to the first end of the fourth resistor R4, and the second end of the fourth resistor R4 is grounded. The second capacitor C2 is connected to the power supply end of the second AND gate chip U32 and grounded.
[0031] In this embodiment, the one-to-four switch 1 includes a one-to-four switch chip U1, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, and a sixth capacitor C6. The first ends of the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, and the sixth capacitor C6 are respectively connected to the pins of the one-to-four switch chip U1. The second ends of the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, and the sixth capacitor C6 are respectively grounded. The first end of the third capacitor C3 also serves as the first control pin of the one-to-four switch chip U1, and the first end of the fourth capacitor C4 also serves as the second control pin of the one-to-four switch chip U1. The first control pin is connected to the input end of the single-pole single-throw switch 2, and the second control pin is connected to the output end of the single-pole single-throw switch 2.
[0032] In this embodiment, the 4 single-pole single-throw switches 2 include a first single-pole single-throw switch array A, a second single-pole single-throw switch array B, a third single-pole single-throw switch array C, and a fourth single-pole single-throw switch array D. The first single-pole single-throw switch array A, the second single-pole single-throw switch array B, the third single-pole single-throw switch array C, and the fourth single-pole single-throw switch array D have the same structure.
[0033] In this embodiment, the single-pole single-throw switch 2 includes a single-pole single-throw switch chip U1, a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9, and a tenth capacitor C10. The first end of the seventh capacitor C7 is connected to the first control pin of the single-pole single-throw switch chip U1. The first end of the eighth capacitor C8 is connected to the second control pin of the single-pole single-throw switch chip U1. The second ends of the seventh capacitor C7 and the eighth capacitor C8 are respectively grounded. The ninth capacitor C9 is connected to the output end of the single-pole single-throw switch chip U1, and the tenth capacitor C10 is connected to the input end of the single-pole single-throw switch 2.
[0034] In this embodiment, U1 is a one-to-four switch chip, U7, U8, U9, and U10 are single-pole single-throw switch chips, C1 to C12 are filter capacitors, and C13 to C20 are coupling capacitors. V1 and V2 are the control pins of the one-to-four switch chip, and VC1 and VC2 are the control pins of the single-pole single-throw chip. The control logic of the switch matrix is shown in Table 1 below (logic 0 represents low level, and logic 1 represents high level). For example, when V1, V2, and VC2 are at low level and VC1 is at high level, array A is opened, and the signal link direction is RFC-1, RF1-OUT-A, RF1-A.
[0035] Table 1 - Control Logic of the Switch Matrix
[0036]
[0037] To ensure the isolation between links, each link is shielded with a cavity or a septum. When laying out the layout, the physical lengths of the 6 signals of the same array passing through the link should be the same. Since impedance matching will be performed on the layout during debugging, which often destroys the phase consistency, the length of the coaxial cable between the signal output end on the layout and the external output interface of the product should be adjusted to compensate for the phase difference.
[0038] In this embodiment, L1 to L6 are bead inductors, which mainly prevent the control signal from generating spike voltage. The AND gate mainly protects the switch chip and provides a safe and stable power supply for the chip. Table 2 is the logic truth table of decoder U33.
[0039] Table 2 - Logic Truth Table of Decoder U33
[0040] B A Y0 Y1 Y2 Y3 0 0 0 1 1 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 0
[0041] In this embodiment, taking the conduction of array A as an example, when the control logics C1-1 and C2-2 of the customer are both at low level, the outputs C1-1A and C1-1B of decoder U33 are at low level, and the rest of the outputs are at high level. In the in-phase comparator, the output VC2-RFA is at low level, and VC2-RFB, VC2-RFC, and VC2-RFD are at high level. In the anti-phase comparator, the output VC1-RFA is at high level, and VC1-RFB, VC1-RFC, and VC1-RFD are at low level. Then, the single-pole single-throw switch 2 in array A will conduct, and the single-pole single-throw switches 2 in arrays B, C, and D will turn off. The outputs V1 and V2 of the AND gate are both at low level, and RF-OUT-A of the one-to-four switch 1 will output a signal, while the other three paths RF-OUT-B, RF-OUT-C, and RF-OUT-D will cut off the signal output. At this time, the signal link on array A of the product is fully conducted and allows the signal to pass through, while the signal links on arrays B, C, and D will be all disconnected to block the signal from passing through.
[0042] It should be noted that in this text, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, such that a process, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, article or device comprising such element.
[0043] The embodiments of the present utility model have been described above in conjunction with the accompanying drawings. What is disclosed is only the preferred embodiments of the present utility model. However, the present utility model is not limited to the above specific embodiments. The above specific embodiments are merely illustrative rather than restrictive. Under the inspiration of the present utility model, those of ordinary skill in the art can also make many equivalent changes in form without departing from the purpose of the present utility model and the scope protected by the claims, and all of them fall within the protection scope of the present utility model.
Claims
1. A control circuit of a switch matrix, characterized in that: It comprises 6 groups of unit links, each of which comprises a one-to-four switch, four single-pole single-throw switches connected to the one-to-four switch, and a control unit; the control unit is connected between the one-to-four switch and the single-pole single-throw switch, and is used to control the on and off of the four single-pole single-throw switches; The control unit includes a decoder, a first in-phase comparator, a second in-phase comparator, a first inverting comparator, a second inverting comparator, a first AND gate chip and a second AND gate chip; the input ends of the first AND gate chip and the second AND gate chip are used to connect to a power supply, and the input end of the decoder is respectively connected to the output end of the first AND gate chip and the second AND gate chip; the output end of the decoder is respectively connected to the input end of the first in-phase comparator and the input end of the second in-phase comparator, the output end of the first in-phase comparator and the output end of the second in-phase comparator are respectively connected to the control end of the single-pole single-throw switch, and the output end of the single-pole single-throw switch is used to connect to an external load; The output end of the decoder is connected to the input end of the first inverting comparator and the input end of the second inverting comparator respectively, and the output end of the first inverting comparator and the output end of the second inverting comparator are connected to the control end of the single-pole single-throw switch respectively.
2. The control circuit of the switch matrix according to claim 1, characterized in that: The control circuit of the switch matrix also includes a first resistor, a second resistor and a first capacitor, wherein the first end of the first resistor is connected to the input end of the first AND gate chip, the second end of the first resistor is connected to the first end of the second resistor, and the second end of the second resistor is grounded; the first capacitor is connected to the power supply end of the first AND gate chip and is grounded.
3. The control circuit of the switch matrix according to claim 1, characterized in that: The control circuit of the switch matrix also includes a third resistor, a fourth resistor and a second capacitor, wherein the first end of the third resistor is connected to the input end of the second AND gate chip, the second end of the third resistor is connected to the first end of the fourth resistor, and the second end of the fourth resistor is grounded; the second capacitor is connected to the power supply end of the second AND gate chip and is grounded.
4. The control circuit of the switch matrix according to claim 1, characterized in that: The one-to-four switch includes a one-to-four switch chip, a third capacitor, a fourth capacitor, a fifth capacitor and a sixth capacitor, wherein a first end of the third capacitor, a first end of the fourth capacitor, a first end of the fifth capacitor and a first end of the sixth capacitor are respectively connected to pins of the one-to-four switch chip, and a second end of the third capacitor, a second end of the fourth capacitor, a second end of the fifth capacitor and a second end of the sixth capacitor are respectively grounded; the first end of the third capacitor also serves as a first control pin of the one-to-four switch chip, and the first end of the fourth capacitor also serves as a second control pin of the one-to-four switch chip; the first control pin is connected to an input end of the single-pole single-throw switch, and the second control pin is connected to an output end of the single-pole single-throw switch.
5. The control circuit of the switch matrix according to claim 4, characterized in that: The four single-pole single-throw switches include a first single-pole single-throw switch, a second single-pole single-throw switch, a third single-pole single-throw switch and a fourth single-pole single-throw switch; the first single-pole single-throw switch, the second single-pole single-throw switch, the third single-pole single-throw switch and the fourth single-pole single-throw switch have the same structure.
6. The control circuit of the switch matrix according to claim 5, characterized in that: The single-pole single-throw switch comprises a single-pole single-throw switch chip, a seventh capacitor, an eighth capacitor, a ninth capacitor and a tenth capacitor; The first end of the seventh capacitor is connected to the first control pin of the single-pole single-throw switch chip, the first end of the eighth capacitor is connected to the second control pin of the single-pole single-throw switch chip, and the second end of the seventh capacitor and the second end of the eighth capacitor are grounded respectively; The ninth capacitor is connected to the output end of the single-pole single-throw switch chip, and the tenth capacitor is connected to the input end of the single-pole single-throw switch.