Power supply circuit for high-efficiency image acquisition equipment

Abstract

The utility model provides a power supply circuit for high-efficiency image acquisition equipment, which comprises a temperature sensor, a microcontroller, a power supply module, a CPU (central processing unit), an FPGA (field programmable gate array), a camera and a network switch, wherein the power output end of the power supply module is respectively connected with the power ends of the temperature sensor, the microcontroller and the network switch; the power supply supplies power to the temperature sensor, the microcontroller and the network switch; the data transmission end of the temperature sensor is connected with the data transmission end of the microcontroller, the temperature sensor is used for monitoring whether the temperatures of the CPU and the FPGA are abnormal or not, and the power supply control end of the microcontroller is connected with the operation control end of the power supply module; the CPU is connected with the FPGA through a PCIE interface, and the data output end of the camera is connected with the data input end of the FPGA. According to the utility model, the stability of the image acquisition equipment is improved, the safety and reliability of the system are enhanced, and the requirements of modern high-speed image processing application are met.

Description

Technical Field

[0001] The utility model relates to a power supply circuit, in particular to a power supply circuit for a high-efficiency image acquisition device. Background Art

[0002] In modern electronic systems, especially in applications that need to process a large amount of high-speed image data, such as video surveillance, industrial automation, medical imaging and other fields, higher requirements are put forward for the power supply circuit of image acquisition devices. These requirements include high efficiency, high stability, and real-time monitoring and control of the device temperature to ensure the reliability and safety of the system. However, there is currently no power supply circuit for high-efficiency image acquisition devices. Content of the Utility Model

[0003] The utility model aims to at least solve the technical problems existing in the prior art, and particularly innovatively provides a power supply circuit for a high-efficiency image acquisition device.

[0004] To achieve the above object of the utility model, the utility model provides a power supply circuit for a high-efficiency image acquisition device, including a temperature sensor, a microcontroller, a power supply module, a CPU, an FPGA, a camera and a network switch:

[0005] The power output terminals of the power supply module are respectively connected to the power supply terminals of the temperature sensor, the microcontroller and the network switch to supply power to the temperature sensor, the microcontroller and the network switch;

[0006] The data transmission terminal of the temperature sensor is connected to the data transmission terminal of the microcontroller. The temperature sensor is used to monitor whether the temperatures of the CPU and the FPGA are abnormal. The power control terminal of the microcontroller is connected to the operation control terminal of the power supply module; The temperature sensor is installed near the CPU and the FPGA to monitor their temperatures in real time. The temperature data detected by the temperature sensor is transmitted to the microcontroller through a connection line. After receiving the temperature data, the microcontroller will analyze it according to a preset temperature threshold. When it is monitored that the temperatures of the CPU and the FPGA are higher than the set temperature value, that is, there is an abnormal temperature; once the microcontroller detects an abnormal temperature, it will execute a preset control logic. At this time, the microcontroller sends a power-down signal by controlling the operation control terminal of the power supply module. The power-down operation can be to disconnect the power supply, or to make the CPU and the FPGA enter a low-power or off state to protect the hardware from high-temperature damage.

[0007] In addition, the microcontroller can also notify the system administrator or trigger an alarm about the abnormal situation by connecting to the network switch.

[0008] The CPU is connected to the FPGA through a PCIe interface, and the data output end of the camera is connected to the data input end of the FPGA through a Camera Link interface; since the FPGA is particularly suitable for processing high-speed and multi-channel signal data transmission, compared with the CPU, it has obvious advantages in parallel processing and low latency. Although the CPU can also connect to the camera through a USB or Ethernet interface, when a large amount of high-speed image data needs to be processed, the solution with the FPGA cooperating with the Camera Link interface can often provide a faster data transmission speed.

[0009] Furthermore, the power supply module includes:

[0010] The internal regulator output terminal INTVCC of the buck converter D17 is connected to the first end of the capacitor C500, the first end of the resistor R223, and the first end of the resistor R222.

[0011] The temperature terminal TEMP of the buck converter D17 is connected to the first end of the resistor R224. The second end of the resistor R224, the first end of the resistor R221, the first end of the resistor R135, the first end of the resistor R218, and the first end of the resistor R217 are connected to the power supply VCC12V.

[0012] The frequency setting terminal FSET of the buck converter D17 is connected to the first end of the resistor R225. The second end of the resistor R225, the mode selection terminal MODE_PLLIN of the buck converter D17, the phase modulation terminal PHASEMD of the buck converter D17, and the second end of the capacitor C500 are connected to the power supply ground.

[0013] The output voltage normal indication terminal PGOOD1 of the buck converter D17 is connected to the second end of the resistor R223.

[0014] The output voltage normal indication terminal PGOOD2 of the buck converter D17 is connected to the second end of the resistor R222.

[0015] The operation control terminal RUN1 of the buck converter D17 is connected to the second end of the resistor R221, the second end of the zener diode VD2, and the power supply control terminal of the microcontroller U21.

[0016] The operation control terminal RUN2 of the buck converter D17 is connected to the second end of the resistor R135, the first end of the resistor R220, and the second end of the zener diode VD1.

[0017] The output voltage tracking terminal TRACK1 of the buck converter D17 is connected to the second end of the resistor R218 and the first end of the capacitor C299.

[0018] The soft start input terminal TRACK2 of the buck converter D17 is connected to the second terminal of the resistor R217 and the first terminal of the capacitor C298;

[0019] The first terminal of the capacitor C299, the first terminal of the capacitor C298, the first terminal of the resistor R220, the first terminal of the zener diode VD1, and the first terminal of the zener diode VD2 are connected to the power ground;

[0020] The power input terminal VIN_15 of the buck converter D17, the first terminal of the polarized capacitor C497, the first terminal of the capacitor C498, the first terminal of the capacitor C499, the first terminal of the capacitor C501, and the first terminal of the capacitor C502 are connected to the power supply VCC12V; the second terminal of the polarized capacitor C497, the second terminal of the capacitor C498, the second terminal of the capacitor C499, the second terminal of the capacitor C501, and the second terminal of the capacitor C502 are connected to the power ground;

[0021] The positive input terminal DIFFP of the remote sensing amplifier of the buck converter D17 is connected to the power supply VCC1.2V;

[0022] The negative input terminal DIFFN of the remote sensing amplifier of the buck converter D17 is connected to the power ground;

[0023] The internal remote sensing amplifier output terminal DIFFOUT of the buck converter D17 is connected to the VOUT2S of the buck converter D17;

[0024] The negative input terminal VFB1 of the error amplifier of the buck converter D17 is connected to the first terminal of the resistor R229, the first terminal of the resistor R230, and the first terminal of the resistor R226;

[0025] The current control threshold / error amplifier compensation terminal COMP1 of the buck converter D17 is connected to the first terminal of the resistor R228, and the second terminal of the resistor R228, the second terminal of the resistor R229, and the second terminal of the resistor R230 are connected to the power ground;

[0026] The power output terminal VOUT1S of the buck converter D17 is connected to the first terminal of the capacitor C505, the first terminal of the polarized capacitor C506, and the second terminal of the resistor R226, and the power output of the buck converter D17 is the power supply VCC3.3V; the second terminal of the capacitor C505 and the second terminal of the polarized capacitor C506 are connected to the power ground;

[0027] The negative input terminal VFB2 of the error amplifier of the buck converter D17 is connected to the first terminal of the resistor R136, and the second terminal of the resistor R136 is connected to the power ground;

[0028] The power output terminal VOUT2_14 of the buck converter D17, the first terminal of the capacitor C503, and the first terminal of the polarized capacitor C504 are connected. The power output terminal VOUT2_14 of the buck converter D17 outputs the power supply VCC1.2V; the second terminal of the capacitor C503 and the second terminal of the polarized capacitor C504 are connected to the power ground;

[0029] The ground terminal SGND and GND of the buck converter D17 are connected to the power ground.

[0030] Among them, the voltage-regulating diodes VD1 and VD2 have a voltage-regulating effect. The 3.3V power supply output by the buck converter D17 is used to supply power to the microcontroller and the temperature sensor; the 1.2V power supply output by the buck converter D17 is used to supply power to the network switch; the model of the buck converter D17 is LTM4620EV.

[0031] Further, the microcontroller includes:

[0032] The data transmission terminal PB9 of the microcontroller U21 is connected to the first terminal of the resistor R154; the second terminal of the resistor R154 is connected to the data sending terminal of the UART (Universal Asynchronous Receiver-Transmitter); the data transmission terminal PB10 of the microcontroller U21 is connected to the first terminal of the resistor R155; the second terminal of the resistor R155 is connected to the data receiving terminal of the UART;

[0033] The data transmission terminal PC6 of the microcontroller U21 is connected to the first terminal of the resistor R156; the second terminal of the resistor R156 is connected to the data sending terminal of the UART; the data transmission terminal PC7 of the microcontroller U21 is connected to the first terminal of the resistor R157; the second terminal of the resistor R157 is connected to the data receiving terminal of the UART;

[0034] The reset signal transmission terminals PB0, PB1, PB2, and PB3 of the microcontroller U21 are respectively connected to the reset terminals of the FPGA, CPU, and Ethernet switch chip;

[0035] To prevent signal reflection, the data transmission terminal PB0 of the microcontroller U21 is connected to the first terminal of the resistor R164 and the reset terminal of the FPGA; the data transmission terminal PB1 of the microcontroller U21 is connected to the first terminal of the resistor R165 and the reset terminal of the CPU; the data transmission terminal PB2 of the microcontroller U21 is connected to the first terminal of the resistor R167 and the reset terminal of the Ethernet switch chip; the data transmission terminal PB3 of the microcontroller U21 is connected to the first terminal of the resistor R178 and the reset terminal of the GPS; the second terminals of the resistor R164, resistor R165, resistor R167, and resistor R178 are connected to the power supply VCC3.3V;

[0036] The external capacitor terminal VCAP1 of the microcontroller U21 is connected to the first terminal of the capacitor C156, and the second terminal of the capacitor C156 is connected to the power ground;

[0037] The data transmission terminal PC9 of the microcontroller U21 is connected to the first terminal of the resistor R168 and the software reset terminal of the Ethernet switch chip. The second terminal of the resistor R168 is connected to the power supply VCC3.3V.

[0038] The operation indication terminal PC14 / OSC32_IN of the microcontroller U21 is connected to the first terminal of the resistor R166. The second terminal of the resistor R166 is connected to the positive electrode of the light-emitting diode HL1, and the negative electrode of the light-emitting diode HL1 is connected to the power ground;

[0039] The crystal oscillator input terminal PH0 / OSC_IN of the microcontroller U21 is connected to the third terminal of the crystal oscillator G1, the first terminal of the resistor R171, and the first terminal of the capacitor C158;

[0040] The crystal oscillator output terminal PH1 / OSC_OUT of the microcontroller U21 is connected to the first terminal of the crystal oscillator G1, the first terminal of the resistor R157, and the first terminal of the capacitor C157;

[0041] The second terminal of the capacitor C157 and the second terminal of the capacitor C158 are connected to the power ground; the second terminal and the fourth terminal of the crystal oscillator G1 are connected to the power ground;

[0042] The battery power terminal VBAT of the microcontroller U21, the power supply terminal VDD of the microcontroller U21, the first terminal of the capacitor C159, the first terminal of the capacitor C160, the first terminal of the capacitor C161, and the first terminal of the capacitor C163 are connected to the power supply VCC3.3V; the second terminal of the capacitor C159, the second terminal of the capacitor C160, the second terminal of the capacitor C161, and the second terminal of the capacitor C163 are connected to the power ground;

[0043] Connecting the power supply in parallel with multiple capacitors and then inputting it to the power supply terminal of the microcontroller can effectively remove high-frequency noise and transient fluctuations on the power line, provide a more stable and clean power supply voltage, thereby ensuring the reliable operation of the microcontroller and reducing faults and performance degradation caused by unstable power supply. In addition, this configuration can also provide transient load current, improve the dynamic response of the power supply, and filter out electromagnetic interference that may interfere with the normal operation of the microcontroller.

[0044] The reference voltage terminal VREF+ of the microcontroller U21 and the first terminal of the capacitor C164 are connected to the power supply VCC3.3V, and the second terminal of the capacitor C164 is connected to the power ground;

[0045] The BOOT0 of the microcontroller U21 is connected to the power ground; the ground terminals VSS and VSSA of the microcontroller U21 are connected to the power ground;

[0046] Among them, the model of the microcontroller U21 is stm32f411ret6.

[0047] Furthermore, the reset of the microcontroller U21 is achieved through the reset chip D12: the reset terminal NRST of the microcontroller U21 is connected to the reset signal output terminal RESET* of the reset chip D12, the first terminal of the resistor R163, and the first terminal of the capacitor C155; the second terminal of the resistor R163 is connected to the power supply VCC3.3V, the second terminal of the capacitor C155, and the ground terminal GND of the reset chip D12 are connected to the power ground; the manual reset terminal MR* of the reset chip D12, the monitoring terminal SENSE, the power supply terminal VDD, and the first terminal of the capacitor C153 are connected to the power supply VCC3.3V; the clock frequency modulation terminal CT is connected to the first terminal of the capacitor C154, and the second terminal of the capacitor C154 and the second terminal of the capacitor C153 are connected to the power ground.

[0048] Using a reset chip to provide a reset signal for the microcontroller provides a more robust and flexible reset mechanism, which can significantly improve the stability and reliability of the system. The reset chip has an internal voltage detection and stability enhancement circuit, which can prevent accidental resets caused by power fluctuations; it has an internal voltage detection and stability enhancement circuit, which can prevent accidental resets caused by power fluctuations. Among them, the model of the reset chip D12 is TPS3808G33DBVT.

[0049] Furthermore, there are several temperature sensors, and the circuit connection of the temperature sensors is as follows:

[0050] The data transmission terminal SDA of the temperature sensor D13 is connected to the first terminal of the resistor R169 and the data terminal of the microcontroller U21, the clock signal terminal SCL of the temperature sensor D13 is connected to the first terminal of the resistor R170 and the clock signal terminal of the microcontroller U21, the second terminals of the resistor R169 and the resistor R170 are connected to the power supply VCC3.3V; the ground terminal GND of the temperature sensor D13 is connected to the power ground; the power supply terminal VSS, the address selection terminal A0, the address selection terminal A1, and the first terminal of the capacitor C162 of the temperature sensor D13 are connected to the power supply VCC3.3V; the address selection terminal A2 of the temperature sensor D13 is connected to the power ground. The models of the temperature sensors D13 and D14 are LM75CIMM-3.

[0051] Further, the data output terminal of the camera is connected to the data input terminal of the FPGA through a Camera Link interface; the Camera Link interface circuit has an LVDS buffer, and the Camera Link interface circuit includes:

[0052] The positive differential input terminal IN+ and the negative differential input terminal IN- of the LVDS buffer are connected to the differential signal output terminal of the connector J1;

[0053] The configuration terminal EQ0 of the LVDS buffer is connected to the first end of the first resistor and the first end of the second resistor. The second end of the first resistor and the first end of the third resistor are connected to the power supply VCC3.3V; the second end of the third resistor and the first end of the fourth resistor are connected to the configuration terminal EQ1 of the LVDS buffer; the second end of the fourth resistor and the second end of the second resistor are connected to the power supply ground;

[0054] The positive differential output terminal OUT+ and the negative differential output terminal OUT- of the LVDS buffer are connected to the data transmission terminal of the FPGA;

[0055] The power supply terminal of the LVDS buffer, the first end of the first capacitor, and the first end of the second capacitor are connected to the power supply VCC3.3V; the ground terminal of the LVDS buffer, the second end of the first capacitor, and the second end of the second capacitor are connected to the power supply ground.

[0056] The LVDS buffer is mainly used for the conditioning and transmission of high-speed signals. It can optimize the input high-speed signals, such as enhancing the signal strength, improving the signal edge slope, etc., so as to ensure the integrity and reliability of the signal during transmission.

[0057] During data transmission, the signal may be distorted due to various reasons (such as line loss, electromagnetic interference, etc.). The LVDS buffer can shape the received signal to restore it to the original signal form, thus ensuring the accuracy of the data. In addition, the LVDS technology can transmit data at a high speed to meet the requirements of high-speed data transmission applications.

[0058] The model of the LVDS buffer is DS25BR110TSD, and the signal of the connector J1 is CAMERALINK CJ-SDR.

[0059] Further, there are multiple LVDS buffers.

[0060] Further, the data input terminal of the camera is connected to the data output terminal of the CPU, and the data transmission terminal of the camera is connected to the data transmission terminal of the CPU through a driver chip, including:

[0061] The data transmission terminal D of the driving chip is connected to the data input terminal of the CPU. The data enable terminal DE of the driving chip is connected to the first terminal of the resistor R78, and the second terminal of the resistor R78 is connected to the power supply VCC3.3V.

[0062] The row clock terminal R of the driving chip is connected to the data output terminal of the CPU, and the row enable negative logic terminal RE_N of the driving chip is connected to the power ground.

[0063] The output data terminal Y, data transmission indication terminal Z, address terminal A, and output data terminal B of the driving chip are all connected to the connector J1, and the connector J1 is connected to the camera.

[0064] The power supply terminal VCC1 of the driving chip, the power supply terminal VCC2 of the driving chip, the first terminal of the capacitor C14, and the first terminal of the capacitor C15 are connected to the power supply VCC3.3V. The second terminal of the capacitor C14 and the second terminal of the capacitor C15 are connected to the power ground.

[0065] The grounding terminal GND1 of the driving chip and the grounding terminal GND2 of the driving chip are connected to the power ground.

[0066] The camera is connected to the CPU through the connector J1, LVDS buffer, and driving chip, forming a complete data transmission and control link. This connection method allows the image data captured by the camera to be transmitted to the FPGA for preliminary processing, then further processed or converted by the driving chip, and finally sent to the CPU for final processing or analysis. At the same time, the CPU can also send control signals to the camera through the driving chip to adjust its settings or configurations.

[0067] The model of the driving chip is SN65LVDS180PW.

[0068] Furthermore, the data output terminal of the camera is connected to the data input terminal of the CPU through the USB interface, including:

[0069] The primary differential positive signal terminal USB2_DP of the common mode transformer and the primary differential negative signal terminal USB2_DM of the common mode transformer are respectively connected to the differential signal input terminal and the differential signal output terminal of the CPU. The secondary differential positive signal terminal DUSB2_L_D+ of the common mode transformer and the secondary differential negative signal terminal DUSB2_L_D- of the common mode transformer are respectively connected to the data terminal D+ of the USB connector and the data terminal D- of the USB connector.

[0070] The data output terminal of the ESD anti-static protection device is connected to the data input terminal of the USB connector, and the data input terminal of the ESD anti-static protection device is connected to the data output terminal of the USB connector.

[0071] The power supply terminal VBUS of the USB connector is connected to the first end of the bead and the first end of the third capacitor. The second end of the third capacitor is connected to the power ground. The second end of the bead is connected to the power supply USB1_P1_PWR.

[0072] The data terminal D- of the USB connector is connected to the anode of the first TVS diode, and the data terminal D+ of the USB connector is connected to the anode of the second TVS diode. The cathodes of the first TVS diode and the second TVS diode are connected to the power ground.

[0073] The connector type identification terminal ID of the USB connector is connected to the first end of the fifth resistor, and the second end of the fifth resistor is connected to the power ground.

[0074] The USB 3.0 data transmission negative terminal SSTX- of the USB connector, the USB 3.0 data transmission positive terminal SSTX+ of the USB connector, the USB 3.0 data reception negative terminal SSRX- of the USB connector, and the USB 3.0 data reception positive terminal SSRX+ of the USB connector are all connected to the ESD anti-static protection device.

[0075] The ground terminal GND_DRAIN of the USB connector is connected to the power ground.

[0076] The FPGA is responsible for collecting and preprocessing images, and then transmitting the data to the CPU through the USB interface. To ensure that the data transmission process is not affected by electromagnetic interference, a common-mode transformer is added before the USB connector for filtering. The main advantage of using a common-mode transformer for filtering is its excellent high-frequency noise suppression ability, which is crucial for maintaining the signal integrity of high-speed data transmission. The common-mode transformer effectively isolates the noise between the FPGA and the CPU through electrical isolation, protecting the USB interface from the noise and transients on the power line. In addition, it helps to meet the strict electromagnetic compatibility (EMC) requirements, improve the reliability of data transmission, and reduce errors and packet loss.

[0077] Furthermore, the camera connected to the FPGA through the Camera Link interface is a high-definition camera.

[0078] In summary, due to the adoption of the above technical solutions, the data output end of the camera of the present utility model is connected to the data input end of the FPGA, allowing image data to be directly transmitted to the FPGA for processing. This direct connection reduces the delay and loss during data transmission, improves the speed of image processing, and thus realizes high-efficiency image acquisition. On this basis, the microcontroller is connected to the power control end of the power supply module, allowing fine control of the power output. This intelligent control can be based on the feedback of the temperature sensor or automatically adjust the power output according to the usage of the device to improve energy efficiency. Also, the power supply end of the network switch is also powered by the power supply module. Through centralized power supply, power management can be simplified and the complexity of the system can be reduced. In addition, since the FPGA and CPU are the main heat sources, the temperature sensor can ensure the normal operation of the high-efficiency image acquisition device by monitoring the temperatures of the FPGA and CPU; if the power supply module is outside the normal operating range, power problems can be detected and prevented in a timely manner. Therefore, the power supply circuit for the high-efficiency image acquisition device proposed by the present utility model not only improves the stability of the image acquisition device, but also enhances the security and reliability of the system.

[0079] Additional aspects and advantages of the present utility model will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of the present utility model. Brief Description of the Drawings

[0080] The above and / or additional aspects and advantages of the present utility model will become apparent and be readily understood from the description of the embodiments in conjunction with the following drawings, where:

[0081] Figure 1 is a connection schematic diagram of the present utility model.

[0082] Figure 2 is a connection schematic diagram of the power supply circuit of the present utility model.

[0083] Figure 3 is a circuit connection schematic diagram of the microcontroller of the present utility model.

[0084] Figure 4 is a circuit connection schematic diagram of the temperature sensor of the present utility model.

[0085] Figure 5 is a circuit schematic diagram of the power-on reset generator of the present utility model.

[0086] Figure 6 is a circuit connection schematic diagram of the Ethernet switch chip of the present utility model.

[0087] Figure 7 is a circuit connection schematic diagram of the power-on reset generator of the present utility model.

[0088] Figure 8 It is a schematic diagram of the connection between the CPU and FPGA of the present utility model. Detailed implementation manners

[0089] The embodiments of the present utility model will be described in detail below. The examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements with the same or similar functions throughout. The embodiments described below by referring to the accompanying drawings are exemplary and are only used to explain the present utility model and should not be construed as a limitation to the present utility model.

[0090] The connection schematic diagram of the present utility model is as Figure 1 shown. It includes a temperature sensor, a microcontroller, a power supply module, a CPU, an FPGA, a camera, and a network switch:

[0091] The power output terminals of the power supply module are respectively connected to the power supply terminals of the temperature sensor, the microcontroller, and the network switch to supply power to the temperature sensor, the microcontroller, and the network switch; the data transmission terminal of the temperature sensor is connected to the data transmission terminal of the microcontroller. The temperature sensor is used to monitor whether the temperatures of the CPU and FPGA are abnormal. The power control terminal of the microcontroller is connected to the operation control terminal of the power supply module; the temperature sensor is installed near the CPU and FPGA to monitor their temperatures in real time. The temperature data detected by the temperature sensor is transmitted to the microcontroller through a connection line. After receiving the temperature data, the microcontroller will analyze it according to a preset temperature threshold. When it is monitored that the temperatures of the CPU and FPGA are higher than the set temperature value, that is, there is an abnormal temperature; once the microcontroller detects an abnormal temperature, it will execute a preset control logic. At this time, the microcontroller sends a power-off signal by controlling the operation control terminal of the power supply module. The power-off operation can be to disconnect the power supply or to make the CPU and FPGA enter a low-power or off state to protect the hardware from high-temperature damage. In addition, the microcontroller can also notify the system administrator or trigger an alarm about the abnormal situation by connecting to the network switch.

[0092] The CPU is connected to the FPGA through a PCIE interface, and the data output end of the camera is connected to the data input end of the FPGA through a Camera Link interface; the FPGA chip can achieve efficient interaction with the CPU through the PCIE interface. The PCIE uses the pcie2.0 IP core of xilinx, and the theoretical rate reaches 20 Gbps. Due to the 8b / 10b encoding method of PCIE, the actual transmission rate reaches 16 Gbps. Because the FPGA is particularly suitable for processing high-speed and multi-channel signal data transmission, compared with the CPU, it has obvious advantages in parallel processing and low latency. Although the CPU can also connect to the camera through a USB or Ethernet interface, when a large amount of high-speed image data needs to be processed, the solution of the FPGA cooperating with the Camera Link interface can often provide a faster data transmission speed.

[0093] The schematic diagram of the power supply circuit connection of the utility model is as Figure 2 shown.

[0094] The output end INTVCC of the internal voltage regulator of the buck converter D17 is connected to the first end of the capacitor C500, the first end of the resistor R223, and the first end of the resistor R222.

[0095] The temperature end TEMP of the buck converter D17 is connected to the first end of the resistor R224, and the second end of the resistor R224, the first end of the resistor R221, the first end of the resistor R135, the first end of the resistor R218, and the first end of the resistor R217 are connected to the power supply VCC12V.

[0096] The frequency setting end FSET of the buck converter D17 is connected to the first end of the resistor R225, and the second end of the resistor R225, the mode selection end MODE_PLLIN of the buck converter D17, the phase modulation end PHASEMD of the buck converter D17, and the second end of the capacitor C500 are connected to the power supply ground.

[0097] The output voltage normal indication end PGOOD1 of the buck converter D17 is connected to the second end of the resistor R223.

[0098] The output voltage normal indication end PGOOD2 of the buck converter D17 is connected to the second end of the resistor R222.

[0099] The operation control end RUN1 of the buck converter D17 is connected to the second end of the resistor R221, the second end of the zener diode VD2, and the power supply control end of the microcontroller U21.

[0100] The operation control end RUN2 of the buck converter D17 is connected to the second end of the resistor R135, the first end of the resistor R220, and the second end of the zener diode VD1.

[0101] The output voltage tracking terminal TRACK1 of the buck converter D17 is connected to the second terminal of the resistor R218 and the first terminal of the capacitor C299;

[0102] The soft start input terminal TRACK2 of the buck converter D17 is connected to the second terminal of the resistor R217 and the first terminal of the capacitor C298;

[0103] The first terminal of the capacitor C299, the first terminal of the capacitor C298, the first terminal of the resistor R220, the first terminal of the zener diode VD1, and the first terminal of the zener diode VD2 are connected to the power supply ground;

[0104] The power input terminal VIN_15 of the buck converter D17, the first terminal of the polarized capacitor C497, the first terminal of the capacitor C498, the first terminal of the capacitor C499, the first terminal of the capacitor C501, and the first terminal of the capacitor C502 are connected to the power supply VCC12V; the second terminal of the polarized capacitor C497, the second terminal of the capacitor C498, the second terminal of the capacitor C499, the second terminal of the capacitor C501, and the second terminal of the capacitor C502 are connected to the power supply ground;

[0105] The positive input terminal DIFFP of the remote sensing amplifier of the buck converter D17 is connected to the power supply VCC1.2V;

[0106] The negative input terminal DIFFN of the remote sensing amplifier of the buck converter D17 is connected to the power supply ground;

[0107] The internal remote sensing amplifier output terminal DIFFOUT of the buck converter D17 is connected to the VOUT2S of the buck converter D17;

[0108] The negative input terminal VFB1 of the error amplifier of the buck converter D17 is connected to the first terminal of the resistor R229, the first terminal of the resistor R230, and the first terminal of the resistor R226;

[0109] The current control threshold / error amplifier compensation terminal COMP1 of the buck converter D17 is connected to the first terminal of the resistor R228, and the second terminal of the resistor R228, the second terminal of the resistor R229, and the second terminal of the resistor R230 are connected to the power supply ground;

[0110] The power output terminal VOUT1S of the buck converter D17 is connected to the first terminal of the capacitor C505, the first terminal of the polarized capacitor C506, and the second terminal of the resistor R226. The power output terminal VOUT1S of the buck converter D17 outputs the power supply VCC3.3V; the second terminal of the capacitor C505 and the second terminal of the polarized capacitor C506 are connected to the power supply ground;

[0111] The negative input terminal VFB2 of the error amplifier of the buck converter D17 is connected to the first end of the resistor R136, and the second end of the resistor R136 is connected to the power ground;

[0112] The power output terminal VOUT2_14 of the buck converter D17, the first end of the capacitor C503, and the first end of the polarized capacitor C504 are connected. The power output terminal VOUT2_14 of the buck converter D17 outputs the power supply VCC1.2V; the second end of the capacitor C503 and the second end of the polarized capacitor C504 are connected to the power ground;

[0113] The grounding terminal SGND and GND of the buck converter D17 are connected to the power ground.

[0114] Among them, the zener diodes VD1 and VD2 have a voltage stabilizing effect. The 3.3V power supply output by the buck converter D17 is used to supply power to the microcontroller and the temperature sensor; the 1.2V power supply output by the buck converter D17 is used to supply power to the network switch; the model of the buck converter D17 is LTM4620EV.

[0115] Figure 3 It is a circuit connection schematic diagram of the microcontroller of the present utility model. The data transmission terminal PB9 of the microcontroller U21 is connected to the first end of the resistor R154; the second end of the resistor R154 is connected to the data sending end of the UART (Universal Asynchronous Receiver / Transmitter); the data transmission terminal PB10 of the microcontroller U21 is connected to the first end of the resistor R155; the second end of the resistor R155 is connected to the data receiving end of the UART;

[0116] The data transmission terminal PC6 of the microcontroller U21 is connected to the first end of the resistor R156; the second end of the resistor R156 is connected to the data sending end of the UART; the data transmission terminal PC7 of the microcontroller U21 is connected to the first end of the resistor R157; the second end of the resistor R157 is connected to the data receiving end of the UART;

[0117] The reset signal transmission terminals PB0, PB1, PB2, and PB3 of the microcontroller U21 are respectively connected to the reset terminals of the FPGA, CPU, and Ethernet switch chip;

[0118] To prevent signal reflection, the data transmission terminal PB0 of microcontroller U21 is connected to the first end of resistor R164 and the reset terminal of FPGA; the data transmission terminal PB1 of microcontroller U21 is connected to the first end of resistor R165 and the reset terminal of CPU; the data transmission terminal PB2 of microcontroller U21 is connected to the first end of resistor R167 and the reset terminal of the Ethernet switch chip; the data transmission terminal PB3 of microcontroller U21 is connected to the first end of resistor R178 and the reset terminal of GPS; the second ends of resistor R164, resistor R165, resistor R167, and resistor R178 are connected to the power supply VCC3.3V;

[0119] The external capacitor terminal VCAP1 of microcontroller U21 is connected to the first end of capacitor C156, and the second end of capacitor C156 is connected to the power supply ground;

[0120] The data transmission terminal PC9 of microcontroller U21 is connected to the first end of resistor R168 and the software reset terminal of the Ethernet switch chip, and the second end of resistor R168 is connected to the power supply VCC3.3V,

[0121] The operation indication terminal PC14 / OSC32_IN of microcontroller U21 is connected to the first end of resistor R166, the second end of resistor R166 is connected to the positive electrode of light-emitting diode HL1, and the negative electrode of light-emitting diode HL1 is connected to the power supply ground;

[0122] The crystal oscillator input terminal PH0 / OSC_IN of microcontroller U21 is connected to the third end of crystal oscillator G1, the first end of resistor R171, and the first end of capacitor C158;

[0123] The crystal oscillator output terminal PH1 / OSC_OUT of microcontroller U21 is connected to the first end of crystal oscillator G1, the first end of resistor R157, and the first end of capacitor C157;

[0124] The second ends of capacitor C157 and capacitor C158 are connected to the power supply ground; the second end and the fourth end of crystal oscillator G1 are connected to the power supply ground;

[0125] The battery power terminal VBAT of microcontroller U21, the power supply terminal VDD of microcontroller U21, the first end of capacitor C159, the first end of capacitor C160, the first end of capacitor C161, and the first end of capacitor C163 are connected to the power supply VCC3.3V; the second ends of capacitor C159, capacitor C160, capacitor C161, and capacitor C163 are connected to the power supply ground;

[0126] Connect the power supply in parallel with multiple capacitors and then input it to the power supply terminal of the microcontroller, which can effectively remove high-frequency noise and transient fluctuations on the power line, provide a more stable and clean power supply voltage, thus ensuring the reliable operation of the microcontroller and reducing faults and performance degradation caused by unstable power supply. In addition, this configuration can also provide transient load current, improve the dynamic response of the power supply, and filter out electromagnetic interference that may interfere with the normal operation of the microcontroller.

[0127] The reference voltage terminal VREF+ of the microcontroller U21, the first terminal of the capacitor C164 are connected to the power supply VCC3.3V, and the second terminal of the capacitor C164 is connected to the power supply ground.

[0128] The boot mode terminal BOOT0 of the microcontroller U21 is connected to the power supply ground; the ground terminals VSS and VSSA of the microcontroller U21 are connected to the power supply ground.

[0129] Among them, the model of the microcontroller U21 is stm32f411ret6.

[0130] The reset of the microcontroller U21 is achieved through the reset chip D12. As Figure 5 shown: The reset terminal NRST of the microcontroller U21 is connected to the reset signal output terminal RESET* of the reset chip D12, the first terminal of the resistor R163, and the first terminal of the capacitor C155; the second terminal of the resistor R163 is connected to the power supply VCC3.3V, and the second terminal of the capacitor C155 and the ground terminal GND of the reset chip D12 are connected to the power supply ground; the manual reset terminal MR* of the reset chip D12, the monitoring terminal SENSE, the power supply terminal VDD, and the first terminal of the capacitor C153 are connected to the power supply VCC3.3V; the clock frequency modulation terminal CT is connected to the first terminal of the capacitor C154, and the second terminal of the capacitor C154 and the second terminal of the capacitor C153 are connected to the power supply ground.

[0131] Using a reset chip to provide a reset signal for the microcontroller provides a more robust and flexible reset mechanism, which can significantly improve the stability and reliability of the system. The reset chip has an internal voltage detection and stability enhancement circuit, which can prevent accidental reset caused by power supply fluctuations; it has an internal voltage detection and stability enhancement circuit, which can prevent accidental reset caused by power supply fluctuations. Among them, the model of the reset chip D12 is

[0132] In addition, the microcontroller U21 is also connected to the temperature sensors D13 and D14 to detect the temperatures of the FPGA and CPU; if the temperatures of the FPGA and CPU are too high, the microcontroller U21 powers down the device to achieve protection. The connection methods of the temperature sensors D13 and D14 are the same, and only the connection relationship of the temperature sensor D13 is described here.

[0133] Figure 4 It is a schematic diagram of the circuit connection of the temperature sensor of the present utility model. The data transmission terminal SDA of the temperature sensor D13 is connected to the first end of the resistor R169 and the data terminal of the microcontroller U21. The clock signal terminal SCL of the temperature sensor D13 is connected to the first end of the resistor R170 and the clock signal terminal of the microcontroller U21. The second ends of the resistor R169 and the resistor R170 are connected to the power supply VCC3.3V. The ground terminal GND of the temperature sensor D13 is connected to the power ground. The power supply terminal VSS, the address selection terminal A0, the address selection terminal A1 of the temperature sensor D13, and the first end of the capacitor C162 are connected to the power supply VCC3.3V. The address selection terminal A2 of the temperature sensor D13 is connected to the power ground. The temperature sensors D13 and D14 are respectively placed near the CPU and the FPGA, and their models are LM75CIMM-3. In addition, only one temperature sensor can also be used and placed at a suitable position.

[0134] Figure 6 It is a schematic diagram of the circuit connection of the Ethernet switch chip of the present utility model. The Ethernet switch chip U1 is connected to the memory D6, and the memory provides the necessary data storage and processing capabilities to support the various functions of the switch. Among them, the model of the Ethernet switch chip U1 is RTL8370N-VB (LQFP128).

[0135] And, the Ethernet switch chip is reset through a power-on reset generator, which can monitor the power supply voltage to ensure that it is within the operating range of the Ethernet switch chip. The circuit connection of the power-on reset generator D6 is as Figure 7 shown, and its connection method and chip model are the same as those of the reset chip D12, which is TPS3808G33DBVT.

[0136] The connection between the CPU and the FPGA is as Figure 8 shown. The chip of the CPU is LS1046, and the chip of the FPGA is XC7Z045. The CPU can also be connected to a camera through a network port and a USB interface. The high-definition camera is connected to the FPGA through a Camera Link interface. Because the FPGA is particularly suitable for processing the data transmission of high-speed and multi-channel signals, compared with the CPU, it has obvious advantages in parallel processing and low latency. Although the CPU can also be connected to a camera through a USB or Ethernet interface, when a large amount of high-speed image data needs to be processed, the solution of the FPGA cooperating with the Camera Link interface can often provide a faster data transmission speed, so it becomes an ideal choice for processing high-definition video data.

[0137] The utility model realizes real-time temperature monitoring of key components by installing temperature sensors near the CPU and FPGA. The microcontroller receives the data from the temperature sensors and analyzes them according to the preset thresholds. Once abnormal temperature is detected, it immediately performs a power-down operation by controlling the operation control terminal of the power supply module to protect the hardware. The CPU is connected to the FPGA through a PCIE interface, and the data of the camera is connected to the FPGA through a Camera Link interface. By utilizing the high-speed parallel processing ability of the FPGA, fast transmission and processing of high-speed image data are achieved. The microcontroller can also notify the system administrator or trigger an alarm about the abnormal situation by connecting to a network switch, improving the monitoring and maintenance capabilities of the system.

[0138] Although the embodiments of the present utility model have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present utility model. The scope of the present utility model is defined by the claims and their equivalents.

Claims

1. A power supply circuit for a high-efficiency image acquisition device, characterized in that: Including temperature sensor, microcontroller, power supply module, CPU, FPGA, camera and network switch: The power output end of the power supply module is respectively connected to the power supply ends of the temperature sensor, microcontroller and network switch to supply power to the temperature sensor, microcontroller and network switch; the data transmission end of the temperature sensor is connected to the data transmission end of the microcontroller, and the temperature sensor is used to monitor whether the temperature of the CPU and FPGA is abnormal. The power control end of the microcontroller is connected to the operation control end of the power supply module; the CPU and FPGA are connected through the PCIE interface, and the data output end of the camera is connected to the data input end of the FPGA.

2. The power supply circuit for a high-efficiency image acquisition device according to claim 1, characterized in that: The power supply module comprises: The internal regulator output terminal INTVCC of the buck converter D17 is connected to the first end of the capacitor C500, the first end of the resistor R223, and the first end of the resistor R222. The temperature terminal TEMP of the buck converter D17 is connected to the first end of the resistor R224, and the second end of the resistor R224, the first end of the resistor R221, the first end of the resistor R135, the first end of the resistor R218, and the first end of the resistor R217 are connected to the power supply VCC12V; The frequency setting terminal FSET of the buck converter D17 is connected to the first terminal of the resistor R225, and the second terminal of the resistor R225, the mode selection terminal MODE_PLLIN of the buck converter D17, the phase modulation terminal PHASEMD of the buck converter D17, and the second terminal of the capacitor C500 are connected to the power ground; The output voltage normal indication terminal PGOOD1 of the buck converter D17 is connected to the second terminal of the resistor R223; The output voltage normal indication terminal PGOOD2 of the buck converter D17 is connected to the second end of the resistor R222; The operation control terminal RUN1 of the buck converter D17 is connected to the second end of the resistor R221, the second end of the voltage stabilizing diode VD2, and the power control terminal of the microcontroller U21; The operation control terminal RUN2 of the buck converter D17 is connected to the second end of the resistor R135, the first end of the resistor R220, and the second end of the voltage stabilizing diode VD1; The output voltage tracking terminal TRACK1 of the buck converter D17 is connected to the second end of the resistor R218 and the first end of the capacitor C299; The soft start input terminal TRACK2 of the buck converter D17 is connected to the second end of the resistor R217 and the first end of the capacitor C298; A first end of the capacitor C299, a first end of the capacitor C298, a first end of the resistor R220, a first end of the voltage zener diode VD1, and a first end of the voltage zener diode VD2 are connected to a power ground; The power input terminal VIN_15 of the buck converter D17, the first end of the polar capacitor C497, the first end of the capacitor C498, the first end of the capacitor C499, the first end of the capacitor C501, and the first end of the capacitor C502 are connected to the power supply VCC12V; the second end of the polar capacitor C497, the second end of the capacitor C498, the second end of the capacitor C499, the second end of the capacitor C501, and the second end of the capacitor C502 are connected to the power ground; The positive input terminal DIFFP of the remote sensing amplifier of the step-down converter D17 is connected to the power supply VCC1.2V; The negative input terminal DIFFN of the remote sensing amplifier of the buck converter D17 is connected to the power ground; The internal remote sensing amplifier output terminal DIFFOUT of the buck converter D17 is connected to VOUT2S of the buck converter D17; The negative input terminal VFB1 of the error amplifier of the buck converter D17 is connected to the first end of the resistor R229, the first end of the resistor R230, and the first end of the resistor R226; The current control threshold / error amplifier compensation terminal COMP1 of the buck converter D17 is connected to the first end of the resistor R228, and the second end of the resistor R228, the second end of the resistor R229, and the second end of the resistor R230 are connected to the power ground; The power output terminal VOUT1S of the buck converter D17 is connected to the first end of the capacitor C505, the first end of the polarized capacitor C506, and the second end of the resistor R226, and the power output terminal VOUT1S of the buck converter D17 outputs the power supply VCC3.3V; the second end of the capacitor C505 and the second end of the polarized capacitor C506 are connected to the power ground; A negative input terminal VFB2 of the error amplifier of the buck converter D17 is connected to a first end of a resistor R136, and a second end of the resistor R136 is connected to a power ground; The power output terminal VOUT2_14 of the buck converter D17, the first end of the capacitor C503, and the first end of the polarized capacitor C504 are connected, and the power output terminal VOUT2_14 of the buck converter D17 outputs the power supply VCC1.2V; the second end of the capacitor C503 and the second end of the polarized capacitor C504 are connected to the power ground; The ground terminals SGND and GND of the buck converter D17 are connected to the power ground.

3. The power supply circuit for a high-efficiency image acquisition device according to claim 1, characterized in that: The microcontroller comprises: The data transmission terminal PB9 of the microcontroller U21 is connected to the first end of the resistor R154; the second end of the resistor R154 is connected to the data transmitting end of the UART; the data transmission terminal PB10 of the microcontroller U21 is connected to the first end of the resistor R155; the second end of the resistor R155 is connected to the data receiving end of the UART; The data transmission terminal PC6 of the microcontroller U21 is connected to the first end of the resistor R156; the second end of the resistor R156 is connected to the data transmitting end of the UART; the data transmission terminal PC7 of the microcontroller U21 is connected to the first end of the resistor R157; the second end of the resistor R157 is connected to the data receiving end of the UART; The reset signal transmission terminal PB0 of the microcontroller U21, the reset signal transmission terminal PB1 of the microcontroller U21, the reset signal transmission terminal PB2 of the microcontroller U21, and the reset signal transmission terminal PB3 of the microcontroller U21 are respectively connected to the reset terminals of the FPGA, the CPU, and the Ethernet switch chip; The data transmission terminal PB0 of the microcontroller U21 is connected to the first end of the resistor R164 and the reset end of the FPGA; the data transmission terminal PB1 of the microcontroller U21 is connected to the first end of the resistor R165 and the reset end of the CPU; the data transmission terminal PB2 of the microcontroller U21 is connected to the first end of the resistor R167 and the reset end of the Ethernet switch chip; the data transmission terminal PB3 of the microcontroller U21 is connected to the first end of the resistor R178 and the reset end of the GPS; the second end of the resistor R164, the second end of the resistor R165, the second end of the resistor R167, and the second end of the resistor R178 are connected to the power supply VCC3.3V; The external capacitor terminal VCAP1 of the microcontroller U21 is connected to the first terminal of the capacitor C156, and the second terminal of the capacitor C156 is connected to the power ground; The data transmission terminal PC9 of the microcontroller U21 is connected to the first end of the resistor R168 and the software reset end of the Ethernet switch chip, and the second end of the resistor R168 is connected to the power supply VCC3.3V. The operation indication terminal PC14 / OSC32_IN of the microcontroller U21 is connected to the first end of the resistor R166, the second end of the resistor R166 is connected to the positive electrode of the light emitting diode HL1, and the negative electrode of the light emitting diode HL1 is connected to the power ground; The crystal oscillator input terminal PH0 / OSC_IN of the microcontroller U21 is connected to the third terminal of the crystal oscillator G1, the first terminal of the resistor R171, and the first terminal of the capacitor C158; The crystal oscillator output terminal PH1 / OSC_OUT of the microcontroller U21 is connected to the first end of the crystal oscillator G1, the first end of the resistor R157, and the first end of the capacitor C157; The second end of the capacitor C157 and the second end of the capacitor C158 are connected to the power ground; the second end and the fourth end of the crystal oscillator G1 are connected to the power ground; The battery power terminal VBAT of the microcontroller U21, the power terminal VDD of the microcontroller U21, the first end of the capacitor C159, the first end of the capacitor C160, the first end of the capacitor C161, and the first end of the capacitor C163 are connected to the power supply VCC3.3V; the second end of the capacitor C159, the second end of the capacitor C160, the second end of the capacitor C161, and the second end of the capacitor C163 are connected to the power ground; The reference voltage terminal VREF+ of the microcontroller U21 and the first end of the capacitor C164 are connected to the power supply VCC3.3V, and the second end of the capacitor C164 is connected to the power supply ground; The boot mode terminal BOOT0 of the microcontroller U21 is connected to the power ground; the ground terminals VSS and VSSA of the microcontroller U21 are connected to the power ground.

4. The power supply circuit for a high-efficiency image acquisition device according to claim 3, characterized in that: The reset of the microcontroller U21 is achieved through the reset chip D12: the reset terminal NRST of the microcontroller U21 is connected to the reset signal output terminal RESET* of the reset chip D12, the first end of the resistor R163, and the first end of the capacitor C155; the second end of the resistor R163 is connected to the power supply VCC3.3V, and the second end of the capacitor C155 and the ground terminal GND of the reset chip D12 are connected to the power ground; the manual reset terminal MR*, the monitoring terminal SENSE, the power supply terminal VDD, and the first end of the capacitor C153 of the reset chip D12 are connected to the power supply VCC3.3V; the clock frequency modulation terminal CT is connected to the first end of the capacitor C154, and the second end of the capacitor C154 and the second end of the capacitor C153 are connected to the power ground.

5. The power supply circuit for a high-efficiency image acquisition device according to claim 1, characterized in that: There are several temperature sensors, and the circuit connection of the temperature sensors is as follows: The data transmission terminal SDA of the temperature sensor D13 is connected to the first end of the resistor R169 and the data end of the microcontroller U21, the clock signal terminal SCL of the temperature sensor D13 is connected to the first end of the resistor R170 and the clock signal end of the microcontroller U21, the second end of the resistor R169 and the second end of the resistor R170 are connected to the power supply VCC3.3V; the ground terminal GND of the temperature sensor D13 is connected to the power ground; the power supply terminal VSS, the address selection terminal A0, the address selection terminal A1, and the first end of the capacitor C162 of the temperature sensor D13 are connected to the power supply VCC3.3V; the address selection terminal A2 of the temperature sensor D13 is connected to the power ground.

6. The power supply circuit for a high-efficiency image acquisition device according to claim 1, characterized in that: The data output end of the camera is connected to the data input end of the FPGA through a Camera Link interface; the Camera Link interface circuit has an LVDS buffer, and the Camera Link interface circuit includes: The differential input positive terminal IN+ and the differential input negative terminal IN- of the LVDS buffer are connected to the differential signal output terminal of the connector J1; The configuration terminal EQ0 of the LVDS buffer is connected to the first end of the first resistor and the first end of the second resistor, the second end of the first resistor and the first end of the third resistor are connected to the power supply VCC3.3V; the second end of the third resistor and the first end of the fourth resistor are connected to the configuration terminal EQ1 of the LVDS buffer; the second end of the fourth resistor and the second end of the second resistor are connected to the power supply ground; The differential output positive terminal OUT+ of the LVDS buffer and the differential output negative terminal OUT- of the LVDS buffer are connected to the data transmission terminal of the FPGA; The power supply end of the LVDS buffer, the first end of the first capacitor, and the first end of the second capacitor are connected to the power supply VCC3.3V; the ground end of the LVDS buffer, the second end of the first capacitor, and the second end of the second capacitor are connected to the power ground.

7. The power supply circuit for a high-efficiency image acquisition device according to claim 6, characterized in that: There are multiple LVDS buffers.

8. The power supply circuit for a high-efficiency image acquisition device according to claim 1, characterized in that: The data input end of the camera is connected to the data output end of the CPU, and the data transmission end of the camera is connected to the data transmission end of the CPU through the driver chip, including: The data transmission terminal D of the driver chip is connected to the data input terminal of the CPU, the data enable terminal DE of the driver chip is connected to the first end of the resistor R78, and the second end of the resistor R78 is connected to the power supply VCC3.3V; The row clock terminal R of the driver chip is connected to the data output terminal of the CPU, and the row enable negative logic terminal RE_N of the driver chip is connected to the power ground; The output data terminal Y, data transmission indication terminal Z, address terminal A, and output data terminal B of the driver chip are all connected to the connector J1, and the connector J1 is connected to the camera; The power supply terminal VCC1 of the driving chip, the power supply terminal VCC2 of the driving chip, the first end of the capacitor C14, and the first end of the capacitor C15 are connected to the power supply VCC3.3V; the second end of the capacitor C14 and the second end of the capacitor C15 are connected to the power ground; The ground terminal GND1 of the driving chip and the ground terminal GND2 of the driving chip are connected to the power ground.

9. The power supply circuit for a high-efficiency image acquisition device according to claim 1, characterized in that: The data output end of the camera is connected to the data input end of the CPU through the USB interface, including: The primary differential positive signal terminal USB2_DP of the common mode transformer and the primary differential negative signal terminal USB2_DM of the common mode transformer are respectively connected to the differential signal input terminal and the differential signal output terminal of the CPU; the secondary differential positive signal terminal DUSB2_L_D+ of the common mode transformer and the secondary differential negative signal terminal DUSB2_L_D- of the common mode transformer are respectively connected to the data terminal D+ of the USB connector and the data terminal D- of the USB connector; The data output end of the ESD anti-static protection device is connected to the data input end of the USB connector, and the data input end of the ESD anti-static protection device is connected to the data output end of the USB connector; The power terminal VBUS of the USB connector is connected to the first end of the magnetic bead and the first end of the third capacitor, and the second end of the third capacitor is connected to the power ground; the second end of the magnetic bead is connected to the power supply USB1_P1_PWR; The data terminal D- of the USB connector is connected to the anode of the first TVS diode, and the data terminal D+ of the USB connector is connected to the anode of the second TVS diode; the cathode of the first TVS diode and the cathode of the second TVS diode are connected to the power ground; The connector type identification terminal ID of the USB connector is connected to the first end of the fifth resistor, and the second end of the fifth resistor is connected to the power ground; The USB 3.0 data transmission negative terminal SSTX- of the USB connector, the USB 3.0 data transmission positive terminal SSTX+ of the USB connector, the USB 3.0 data receiving negative terminal SSRX- of the USB connector, and the USB 3.0 data receiving positive terminal SSRX+ of the USB connector are all connected to the ESD anti-static protection device; The ground terminal GND_DRAIN of the USB connector is connected to the power ground.

10. The power supply circuit of a high-efficiency image acquisition device according to claim 1, characterized in that: The camera connected to the FPGA through the Camera Link interface is a high-definition camera.

Images