Metering device and system comprising inverter and metering device

Abstract

The utility model relates to a metering device and a system comprising an inverter and the metering device. The metering device comprises two independent metering modules, the circuit topology structures of the two metering modules are the same, each metering module is integrated with a current sampling unit, a voltage sampling unit and a metering chip, and the current sampling unit and the voltage sampling unit are respectively connected with the metering chip; wherein one metering module is used for being connected with an A-phase line, a B-phase line, a C-phase line and a zero line on the inverter side, and the other metering module is used for being connected with an A-phase line, a B-phase line, a C-phase line and a zero line on the power grid side. Through the energy monitoring method and device, the technical problem of high component cost of an energy monitoring scheme in the prior art is solved, and the technical effect of reducing the component cost while energy monitoring is realized is achieved.

Description

Technical Field

[0001] This application relates to the technical field of energy monitoring. Specifically, it relates to a metering device and a system including an inverter and a metering device. Background Art

[0002] Energy monitoring technology not only serves for electricity charge metering, but is also a core link for achieving energy efficiency optimization, power grid stability improvement, and energy management automation. Especially for energy monitoring of photovoltaic inverter grid connection, traditional energy monitoring systems mostly rely on discrete metering devices, including current transformers, voltage transformers, data acquisition modules, and independent data processing units, but face challenges in terms of integration, cost control, and data processing capabilities. For example, traditional discrete design solutions require a large number of external components, such as separate current transformers, voltage transformers, and complex signal conditioning circuits, which not only increase the hardware cost, but also raise the complexity and cost of installation and maintenance; the use of discrete components limits the integration and compactness of the system, is not conducive to deployment in space-constrained scenarios, and increases the energy consumption of the system.

[0003] Regarding the problem of high component costs in the existing energy monitoring solutions, no effective solution has been proposed yet. Summary of the Utility Model

[0004] A metering device and a system including an inverter and a metering device provided by an embodiment of this application are used to at least solve the technical problem of high component costs in the existing energy monitoring solutions.

[0005] According to one aspect of the embodiment of this application, a metering device is provided, including: two independent metering modules, and the circuit topologies of the two metering modules are the same. The metering module is integrated with a current sampling unit, a voltage sampling unit, and a metering chip. The current sampling unit and the voltage sampling unit are respectively connected to the metering chip; one of the metering modules is used to be connected to the A-phase line, B-phase line, C-phase line, and neutral line on the inverter side, and the other metering module is used to be connected to the A-phase line, B-phase line, C-phase line, and neutral line on the grid side.

[0006] Optionally, the metering module further includes a current mutual inductance unit, the current mutual inductance unit includes a plurality of current transformers, the current sampling unit includes an A-phase current sampling circuit, a B-phase current sampling circuit, and a C-phase current sampling circuit, and the voltage sampling unit includes an A-phase voltage sampling circuit, a B-phase voltage sampling circuit, and a C-phase voltage sampling circuit; wherein: a plurality of the current transformers are respectively connected in series to the A-phase line, the B-phase line, and the C-phase line, the input ends of the A-phase current sampling circuit, the B-phase current sampling circuit, and the C-phase current sampling circuit are respectively connected to the corresponding current transformers, and the output ends of the A-phase current sampling circuit, the B-phase current sampling circuit, and the C-phase current sampling circuit are respectively connected to the corresponding pins of the metering chip; the input ends of the A-phase voltage sampling circuit, the B-phase voltage sampling circuit, and the C-phase voltage sampling circuit are respectively connected to the A-phase line, the B-phase line, and the C-phase line, and the output ends of the A-phase voltage sampling circuit, the B-phase voltage sampling circuit, and the C-phase voltage sampling circuit are respectively connected to the corresponding pins of the metering chip.

[0007] Optionally, the circuit topologies of the three-phase current sampling circuits in the current sampling unit are all the same, and each phase current sampling circuit includes a symmetric differential amplification circuit composed of a plurality of TVS tubes, a plurality of resistors, and a plurality of capacitors.

[0008] Optionally, the current sampling circuit includes a first TVS tube, a second TVS tube, a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, and a second capacitor; wherein: the first ends of the first TVS tube, the first resistor, and the second resistor are connected together and used as the first input end of the current sampling circuit, and the second end of the first resistor is connected to the first end of the first capacitor and used as the first output end of the current sampling circuit; the first ends of the second TVS tube, the third resistor, and the fourth resistor are connected together and used as the second input end of the current sampling circuit, and the second end of the fourth resistor is connected to the first end of the second capacitor and used as the second output end of the current sampling circuit; the second ends of the first TVS tube and the second TVS tube are connected together and grounded, the second ends of the second resistor and the third resistor are connected together and grounded, and the second ends of the first capacitor and the second capacitor are connected together and grounded.

[0009] Optionally, the circuit topologies of the three-phase voltage sampling circuits in the voltage sampling unit are all the same, and each phase voltage sampling circuit includes a voltage dividing circuit composed of a plurality of resistors connected in series and a filtering circuit composed of a plurality of resistors and a plurality of capacitors.

[0010] Optionally, the voltage sampling circuit includes a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a third capacitor, and a fourth capacitor; wherein: the fifth resistor, the sixth resistor, the seventh resistor, the eighth resistor, the ninth resistor, the tenth resistor, and the eleventh resistor are connected in series in sequence to form a voltage division circuit; a first end of the voltage division circuit serves as an input end of the voltage sampling circuit, a second end of the voltage division circuit is connected to a first end of the twelfth resistor and a first end of the thirteenth resistor, a second end of the twelfth resistor is connected to a first end of the third capacitor and then serves as a first output end of the voltage sampling circuit; a second end of the fourteenth resistor is connected to a first end of the fifteenth resistor, a second end of the fifteenth resistor is connected to a first end of the fourth capacitor and then serves as a second output end of the voltage sampling circuit; a second end of the thirteenth resistor is connected to a first end of the fourteenth resistor and then grounded, and a second end of the third capacitor is connected to a second end of the fourth capacitor and then grounded.

[0011] Optionally, the metering module further includes an isolation unit connected to the metering chip, and the isolation unit includes an isolation circuit composed of a plurality of resistors, a plurality of capacitors, and an isolation chip.

[0012] Optionally, the metering module further includes a reset unit connected to the metering chip, and the reset unit includes a reset circuit composed of a plurality of resistors, a plurality of capacitors, and a reset chip.

[0013] Optionally, the metering module further includes a crystal oscillator unit connected to the metering chip, and the crystal oscillator unit includes a crystal oscillator circuit composed of a resistor, a plurality of capacitors, and a crystal oscillator.

[0014] According to one aspect of the embodiments of the present application, a system including an inverter and a metering device is provided, and the system includes the metering device described above.

[0015] In the embodiments of the present application, by designing two independent and identical metering modules, which are respectively applied to the inverter side and the grid side, the metering module integrates functions such as current and voltage metering, signal conditioning, and data processing, reducing the number of external components, and thus solving the technical problem of high component cost in the existing energy monitoring solutions, achieving the technical effect of reducing component costs while realizing energy monitoring. Description of the Drawings

[0016] The accompanying drawings described herein are used to provide a further understanding of the present application and form a part of the present application. The schematic embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation of the present application. In the drawings:

[0017] Figure 1 Schematic diagram of a metering device provided by an embodiment of the present application;

[0018] Figure 2 Schematic diagram of a metering module provided by an embodiment of the present application;

[0019] Figure 3 Schematic diagram of a metering chip provided by an embodiment of the present application;

[0020] Figure 4 Schematic diagram of the circuit topology of a current sampling circuit provided by an embodiment of the present application;

[0021] Figure 5 Schematic diagram of the circuit topology of a voltage sampling circuit provided by an embodiment of the present application;

[0022] Figure 6 Schematic diagram of the circuit topology of an isolation unit provided by an embodiment of the present application;

[0023] Figure 7 Schematic diagram of the circuit topology of a reset unit provided by an embodiment of the present application;

[0024] Figure 8 Schematic diagram of the circuit topology of a crystal oscillator unit provided by an embodiment of the present application;

[0025] Figure 9 Schematic diagram of the circuit topology of a filtering unit provided by an embodiment of the present application.

[0026] Among them, the above-mentioned drawings include the following reference numerals:

[0027] L1, A-phase line; L2, B-phase line; L3, C-phase line; N, neutral line; 10, current mutual inductance unit; 20, current sampling unit; 30, voltage sampling unit; U1, metering chip; U2, isolation chip; U3, reset chip; 101, first current transformer; 102, second current transformer; 103, third current transformer; 201, A-phase current sampling circuit; 202, B-phase current sampling circuit; 203, C-phase current sampling circuit; 301, A-phase voltage sampling circuit; 302, B-phase voltage sampling circuit; 303, C-phase voltage sampling circuit; D1, first TVS tube; D2, second TVS tube; R1, first resistor; R2, second resistor; R3, third resistor; R4, fourth resistor; R5, fifth resistor; R6, sixth resistor; R7, seventh resistor; R8, eighth resistor; R9, ninth resistor; R10, tenth resistor; R11, eleventh resistor; R12, twelfth resistor; R13, thirteenth resistor; R14, fourteenth resistor; R15, fifteenth resistor; R16, sixteenth resistor; R17, seventeenth resistor; R18, eighteenth resistor; R19, nineteenth resistor; R20, twentieth resistor; R21, twenty-first resistor; R22, twenty-second resistor; R23, twenty-third resistor; R24, twenty-fourth resistor; R25, twenty-fifth resistor; R26, twenty-sixth resistor; R27, twenty-seventh resistor; R28, twenty-eighth resistor; R29, twenty-ninth resistor; R30, thirtieth resistor; R31, thirty-first resistor; R32, thirty-second resistor; R33, thirty-third resistor; R34, thirty-fourth resistor; R35, thirty-fifth resistor; C1, first capacitor; C2, second capacitor; C3, third capacitor; C4, fourth capacitor; C5, fifth capacitor; C6, sixth capacitor; C7, seventh capacitor; C8, eighth capacitor; C9, ninth capacitor; C10, tenth capacitor; C11, eleventh capacitor; C12, twelfth capacitor; C13, thirteenth capacitor; C14, fourteenth capacitor; C15, fifteenth capacitor; C16, sixteenth capacitor; C17, seventeenth capacitor; C18, eighteenth capacitor; C19, nineteenth capacitor; C20, twentieth capacitor; C21, twenty-first capacitor; C22, twenty-second capacitor; C23, twenty-third capacitor; C24, twenty-fourth capacitor; C25, twenty-fifth capacitor; C26, twenty-sixth capacitor; C27, twenty-seventh capacitor; C28, twenty-eighth capacitor; Y, crystal oscillator. Detailed implementation

[0028] It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments may be combined with each other. The following will describe the present application in detail with reference to the drawings and in combination with the embodiments.

[0029] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0030] Unless otherwise specifically stated, the relative arrangements of the components and steps set forth in these embodiments, numerical expressions, and numerical values do not limit the scope of the present application. At the same time, it should be understood that, for the convenience of description, the sizes of the various parts shown in the drawings are not drawn in actual proportional relationships. Technologies, methods, and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and devices should be regarded as part of the authorization specification. In all the examples shown and discussed here, any specific value should be interpreted as merely exemplary and not as a limitation. Therefore, other examples of the exemplary embodiments may have different values. It should be noted that like reference numerals and letters denote like items in the following drawings, and thus, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0031] According to one aspect of the embodiments of the present application, a metering device is provided. Figure 1 It is a schematic diagram of a metering device provided by the embodiments of the present application. As Figure 1 shown, the metering device includes: two independent metering modules, and the circuit topologies of the two metering modules are the same. The metering module integrates a current sampling unit 20, a voltage sampling unit 30, and a metering chip U1. The current sampling unit 20 and the voltage sampling unit 30 are respectively connected to the metering chip U1. One of the metering modules is used to connect to the A-phase line L1, B-phase line L2, C-phase line L3, and neutral line N on the inverter side, and the other metering module is used to connect to the A-phase line L1, B-phase line L2, C-phase line L3, and neutral line N on the grid side.

[0032] In the embodiments of the present application, by designing two independent and identical metering modules, which are respectively applied to the inverter side and the grid side, the metering module integrates functions such as current and voltage metering, signal conditioning, and data processing, reducing the number of external components, and thus solving the technical problem of high component costs in the existing energy monitoring solutions, achieving the technical effect of reducing component costs while realizing energy monitoring.

[0033] Due to the possible differences in electrical characteristics between the inverter side and the grid side, a single metering module may be difficult to simultaneously meet the different requirements of both sides. Therefore, it is necessary to design two independent but structurally identical metering modules, which can not only ensure the best performance in their respective specific environments but also facilitate unified maintenance and management.

[0034] Figure 2 A schematic diagram of a metering module provided by an embodiment of the present application is shown as Figure 2 shown. The metering module includes: a current mutual inductance unit 10, a current sampling unit 20, a voltage sampling unit 30, and a metering chip U1. The current mutual inductance unit 10 includes a first current transformer 101, a second current transformer 102, and a third current transformer 103. The current sampling unit 20 includes an A-phase current sampling circuit 201, a B-phase current sampling circuit 202, and a C-phase current sampling circuit 203. The voltage sampling unit 30 includes an A-phase voltage sampling circuit 301, a B-phase voltage sampling circuit 302, and a C-phase voltage sampling circuit 303. Among them:

[0035] The first current transformer 101 is connected in series to the A-phase line L1. The first end of the first current transformer 101 is connected to the first input end of the A-phase current sampling circuit 201. The first output end of the A-phase current sampling circuit 201 is connected to the first pin of the metering chip U1. The second end of the first current transformer 101 is connected to the second input end of the A-phase current sampling circuit 201. The second output end of the A-phase current sampling circuit 201 is connected to the second pin of the metering chip U1.

[0036] The second current transformer 102 is connected in series to the B-phase line L2. The first end of the second current transformer 102 is connected to the first input end of the B-phase current sampling circuit 202. The first output end of the B-phase current sampling circuit 202 is connected to the fourth pin of the metering chip U1. The second end of the second current transformer 102 is connected to the second input end of the B-phase current sampling circuit 202. The second output end of the B-phase current sampling circuit 202 is connected to the fifth pin of the metering chip U1.

[0037] The third current transformer 103 is connected in series to the C-phase line L3. The first end of the third current transformer 103 is connected to the first input end of the C-phase current sampling circuit. The first output end of the C-phase current sampling circuit is connected to the seventh pin of the metering chip U1. The second end of the third current transformer 103 is connected to the second input end of the C-phase current sampling circuit. The second output end of the C-phase current sampling circuit is connected to the eighth pin of the metering chip U1.

[0038] The input terminal of the A-phase voltage sampling circuit is connected to the A-phase line L1. The first output terminal of the A-phase voltage sampling circuit is connected to the ninth pin of the metering chip U1, and the second output terminal of the A-phase voltage sampling circuit is connected to the tenth pin of the metering chip U1.

[0039] The input terminal of the B-phase voltage sampling circuit is connected to the B-phase line L2. The first output terminal of the B-phase voltage sampling circuit is connected to the eleventh pin of the metering chip U1, and the second output terminal of the B-phase voltage sampling circuit is connected to the twelfth pin of the metering chip U1.

[0040] The input terminal of the C-phase voltage sampling circuit 303 is connected to the C-phase line L3. The first output terminal of the C-phase voltage sampling circuit 303 is connected to the thirteenth pin of the metering chip U1, and the second output terminal of the C-phase voltage sampling circuit 303 is connected to the fourteenth pin of the metering chip U1.

[0041] In the embodiments of the present application, the metering module can comprehensively monitor three-phase alternating current (A-phase, B-phase, C-phase). The core of the metering module is a highly integrated metering chip U1, which is directly connected to the current sampling unit and the voltage sampling unit through multiple pins. The current mutual inductance unit consists of three independent current transformers, which are respectively connected in series to the A, B, and C phase lines, ensuring the directness and accuracy of current measurement. The current sampling circuit and the voltage sampling circuit are responsible for converting the current transformer and the voltage signal after voltage division into electrical signals suitable for processing by the metering chip. This design not only simplifies the circuit structure, improves the reliability of signal transmission, but also reduces the dependence on external complex conditioning circuits through direct pin connection, reducing the system cost and complexity.

[0042] Through the current transformers directly connected in series to each phase line and the voltage sampling circuit, the metering module can achieve high-precision measurement of three-phase electric energy, reduce the loss and interference in the signal transmission process, and improve the overall metering accuracy.

[0043] The multiple pins of the metering chip U1 are directly connected to each sampling circuit, reducing the intermediate links, improving the system integration degree, and making the whole module more compact, easy to install and maintain.

[0044] By reducing the number of external components and optimizing the circuit design, this solution effectively reduces the material cost and assembly cost.

[0045] Figure 3 A schematic diagram of a metering chip provided for the embodiments of the present application is as Figure 3 shown. The metering chip includes multiple pins, and the specific description for each pin is as follows:

[0046] The first pin (IAP) is the positive analog input pin of the A-phase current sampling circuit; the second pin (IAN) is the negative analog input pin of the A-phase current sampling circuit; the third pin (AGND) is the analog ground pin; the fourth pin (IBP) is the positive analog input pin of the B-phase current sampling circuit; the fifth pin (IBN) is the negative analog input pin of the B-phase current sampling circuit; the sixth pin (AVCC) is the analog power supply pin; the seventh pin (ICP) is the positive analog input pin of the C-phase current sampling circuit; the eighth pin (ICN) is the negative analog input pin of the C-phase current sampling circuit; the ninth pin (VAP) is the positive analog input pin of the A-phase voltage sampling circuit; the tenth pin (VAN) is the negative analog input pin of the A-phase voltage sampling circuit; the eleventh pin (VBP) is the positive analog input pin of the B-phase voltage sampling circuit; the twelfth pin (VBN) is the negative analog input pin of the B-phase voltage sampling circuit; the thirteenth pin (VCP) is the positive analog input pin of the C-phase voltage sampling circuit; the fourteenth pin (VCN) is the negative analog input pin of the C-phase voltage sampling circuit; the fifteenth pin (INP) is the positive analog input pin of the neutral line current sampling; the sixteenth pin (INN) is the negative analog input pin of the neutral line current sampling; the seventeenth pin (CF3), the eighteenth pin (CF2), and the nineteenth pin (CF1) are all power calibration pulse outputs and can be flexibly configured as fundamental wave / full wave, active / reactive / apparent any combined phase pulse or high-frequency combined phase pulse output pins through the CFCFG register; the twentieth pin (RSTN) is the reset pin; the twenty-first pin (DVCC) and the thirty-first pin (DVCC) are both digital power supply pins; the twenty-second pin (INTN) is the interrupt output pin; the twenty-third pin (SDO) is the SPI serial data output pin; the twenty-fourth pin (SCLK) is the SPI serial clock input pin; the twenty-fifth pin (SCSN) is the SPI select signal pin; the twenty-sixth pin (SDI) is the SPI serial data input pin or the data input pin of the serial interface; the twenty-seventh pin (XO) is the output pin of the clock crystal; the twenty-eighth pin (XI) is the input pin of the clock crystal or the external injected system clock input pin; the twenty-ninth pin (VO) is the output pin of the built-in voltage regulator module; the thirtieth pin (DGND) is the digital ground pin; the thirty-second pin (REFV) is the built-in reference voltage output or the external REFV input pin.

[0047] Figure 4 The circuit topology diagram of a current sampling circuit provided by an embodiment of the present application is shown as Figure 4 shown. The current sampling circuit includes: a first TVS tube D1, a second TVS tube D2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first capacitor C1, and a second capacitor C2; where:

[0048] The first end of the first TVS tube D1, the first end of the first resistor R1, and the first end of the second resistor R2 are connected together and used as the first input end of the current sampling circuit. The second end of the first resistor R1 is connected to the first end of the first capacitor C1 and used as the first output end of the current sampling circuit.

[0049] The first end of the second TVS tube D2, the first end of the third resistor R3, and the first end of the fourth resistor R4 are connected together and used as the second input end of the current sampling circuit. The second end of the fourth resistor R4 is connected to the first end of the second capacitor C2 and used as the second output end of the current sampling circuit.

[0050] The second end of the first TVS tube D1 is connected to the second end of the second TVS tube D2 and used for grounding. The second end of the second resistor R2 is connected to the second end of the third resistor R3 and grounded. The second end of the first capacitor C1 is connected to the second end of the second capacitor C2 and grounded.

[0051] It should be noted that the circuit topologies of the current sampling circuits corresponding to the A-phase line, B-phase line, and C-phase line in the current sampling unit are all the same.

[0052] In the embodiment of the present application, the current sampling circuit uses two bidirectional transient voltage suppression diodes (TVS tubes D1 and D2) as protection elements, and four precision resistors (R1 to R4) and two decoupling capacitors (C1 and C2) to construct a set of symmetric differential amplifier circuits. It can not only effectively suppress transient voltages and protect the subsequent metering chip from overvoltage damage, but also improve the signal quality through resistor voltage division and capacitor filtering, ensuring the accuracy and stability of current measurement.

[0053] The introduction of the TVS tube provides transient overvoltage protection for the circuit, can quickly respond and clamp potential voltage spikes, effectively avoids damage to sensitive electronic components caused by external electrical surges, and enhances the robustness of the system in a harsh power grid environment.

[0054] Through resistor voltage division (R1 - R4) and capacitor filtering (C1 and C2), the circuit can preliminarily process the sampled current signal, filter out high-frequency noise, ensure that the current signal sent to the metering chip is clean and stable, and improve the measurement accuracy.

[0055] All three-phase (A-phase, B-phase, C-phase) current sampling circuits adopt a unified circuit topology, which simplifies the design complexity, reduces the production cost, and is convenient for standardized production and maintenance, improving the versatility and interchangeability of the system.

[0056] The symmetric differential amplifier design helps to cancel common-mode noise, reduce temperature drift and bias error.

[0057] Figure 5 Schematic diagram of the circuit topology of a voltage sampling circuit provided by an embodiment of the present application, as Figure 5 shown. The voltage sampling circuit includes: a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a third capacitor C3, and a fourth capacitor C4; where:

[0058] The fifth resistor R5, the sixth resistor R6, the seventh resistor R7, the eighth resistor R8, the ninth resistor R9, the tenth resistor R10, and the eleventh resistor R11 are connected in series in sequence to form a voltage dividing circuit.

[0059] The first end of the voltage dividing circuit serves as the input end of the voltage sampling circuit, and the second end of the voltage dividing circuit is connected to the first ends of the twelfth resistor R12 and the thirteenth resistor R13. The second end of the twelfth resistor R12 is connected to the first end of the third capacitor C3 and then serves as the first output end of the voltage sampling circuit.

[0060] The second end of the fourteenth resistor R14 is connected to the first end of the fifteenth resistor R15, and the second end of the fifteenth resistor R15 is connected to the first end of the fourth capacitor C4 and then serves as the second output end of the voltage sampling circuit.

[0061] The second end of the thirteenth resistor R13 is connected to the first end of the fourteenth resistor R14 and then grounded, and the second ends of the third capacitor C3 and the fourth capacitor C4 are connected to each other and then grounded.

[0062] It should be noted that the circuit topologies of the voltage sampling circuits corresponding to the A-phase line, B-phase line, and C-phase line in the voltage sampling unit are all the same.

[0063] In the embodiment of the present application, this structure realizes the accurate measurement of the grid voltage through a voltage dividing network and a filtering component. The circuit mainly consists of a voltage dividing circuit composed of a series of precision resistors (R5 to R15) and two decoupling capacitors (C3 and C4), forming a stable and reliable voltage sampling circuit. This design can convert the line voltage on the high-voltage side into a low-voltage signal suitable for processing by the metering chip in proportion, while ensuring the purity of the signal, improving the measurement accuracy and system safety.

[0064] The series-connected resistor network (R5 to R11) constitutes an accurate voltage divider, which can flexibly adjust the voltage division ratio according to the grid voltage level and the input requirements of the metering chip, realizing the accurate proportional reduction of the high-voltage signal and ensuring the high precision of voltage measurement.

[0065] The filter network formed by R12, R13 and C3, as well as R14, R15 and C4 effectively filters out high-frequency noise and ripples in the power grid, stabilizes the sampling voltage, reduces measurement errors, and improves system stability.

[0066] This circuit design avoids directly introducing high-voltage signals into sensitive electronic components. Through voltage division and protection measures, it ensures the safe operation of the entire system and reduces the risk of electrical fires and equipment damage.

[0067] The voltage sampling circuits for the three phases A, B, and C adopt the same circuit topology, simplifying the design and maintenance work, facilitating mass production and standardized installation, and reducing costs.

[0068] As an alternative embodiment, the above metering module further includes an isolation unit. Figure 6 Schematic diagram of the circuit topology of an isolation unit provided by an embodiment of the present application, as Figure 6 shown, the isolation unit includes: the sixteenth resistor R16, the seventeenth resistor R17, the eighteenth resistor R18, the nineteenth resistor R19, the twentieth resistor R20, the twenty-first resistor R21, the twenty-second resistor R22, the twenty-third resistor R23, the twenty-fourth resistor R24, the twenty-fifth resistor R25, the twenty-sixth resistor R26, the twenty-seventh resistor R27, the twenty-eighth resistor R28, the twenty-ninth resistor R29, the fifth capacitor C5, the sixth capacitor C6, the seventh capacitor C7, the eighth capacitor C8, the ninth capacitor C9, the tenth capacitor C10, the eleventh capacitor C11, the twelfth capacitor C12, the thirteenth capacitor C13, the fourteenth capacitor C14, and the isolation chip U2; wherein:

[0069] The first end of the sixteenth resistor R16, the first end of the fifth capacitor C5 are connected to the first pin of the isolation chip U2 and then used to connect to the twenty-first pin of the metering chip U1. The second end of the sixteenth resistor R16 is connected to the sixth pin of the isolation chip U2. The second end of the fifth capacitor C5 is connected to the sixth pin of the isolation chip U2 and then grounded.

[0070] The first end of the seventeenth resistor R17 is connected to the twenty-sixth pin of the metering chip U1. The second end of the seventeenth resistor R17 is connected to the second pin of the isolation chip U2. The first end of the eighteenth resistor R18 is connected to the twenty-fifth pin of the metering chip U1. The second end of the eighteenth resistor R18 is connected to the third pin of the isolation chip U2.

[0071] The first end of the nineteenth resistor R19 is connected to the twenty-fourth pin of the metering chip U1, and the second end of the nineteenth resistor R19 is connected to the fourth pin of the isolation chip U2; the first end of the twentieth resistor R20 is connected to the twenty-third pin of the metering chip U1, and the second end of the twentieth resistor R20 is connected to the sixth pin of the isolation chip U2.

[0072] The first end of the twenty-first resistor R21 is connected to the twenty-second pin of the metering chip U1, and the second end of the twenty-first resistor R21 is connected to the seventh pin of the isolation chip U2; the first end of the sixth capacitor C6 is connected to the first end of the seventeenth resistor R17, the first end of the seventh capacitor C7 is connected to the first end of the eighteenth resistor R18, the first end of the eighth capacitor C8 is connected to the first end of the nineteenth resistor R19, and the second ends of the sixth capacitor C6, the seventh capacitor C7, and the eighth capacitor C8 are connected together and then grounded.

[0073] The first end of the ninth capacitor C9 is connected to the sixth pin of the isolation chip U2, and the second end of the ninth capacitor C9 is used for grounding.

[0074] The first ends of the tenth capacitor C10, the twenty-second resistor R22, the twenty-third resistor R23, and the twenty-fourth resistor R24 are respectively connected to the sixteenth pin of the isolation chip U2. The second end of the tenth capacitor C10 is connected to the ninth pin of the isolation chip U2 and then grounded. The second end of the twenty-second resistor R22 is connected to the fifteenth pin of the isolation chip U2, the second end of the twenty-third resistor R23 is connected to the fourteenth pin of the isolation chip U2, and the second end of the twenty-fourth resistor R24 is connected to the thirteenth pin of the isolation chip U2.

[0075] The first end of the twenty-fifth resistor R25 is connected to the fifteenth pin of the isolation chip U2, and the second end of the twenty-fifth resistor R25 is used for connection to the main output slave input end of the main control device.

[0076] The first end of the twenty-sixth resistor R26 is connected to the fourteenth pin of the isolation chip U2, and the second end of the twenty-sixth resistor R26 is used for connection to the selection signal end of the main control device.

[0077] The first end of the twenty-seventh resistor R27 is connected to the twelfth pin of the isolation chip U2, and the second end of the twenty-seventh resistor R27 is used for connection to the clock signal end of the main control device.

[0078] The first end of the twenty-eighth resistor R28 is connected to the eleventh pin of the isolation chip U2, and the second end of the twenty-eighth resistor R28 is used for connection to the main input slave output end of the main control device.

[0079] The first end of the twenty-ninth resistor R29 is connected to the tenth pin of the isolation chip U2, and the second end of the twenty-ninth resistor R29 is used to be connected to the interrupt output end of the main control device.

[0080] The first end of the eleventh capacitor C11 is connected to the fifteenth pin of the isolation chip U2, the first end of the twelfth capacitor C12 is connected to the fourteenth pin of the isolation chip U2, the first end of the thirteenth capacitor C13 is connected to the thirteenth pin of the isolation chip U2. The second ends of the eleventh capacitor C11, the above-mentioned twelfth capacitor C12 and the thirteenth capacitor C13 are connected together and then grounded. The first end of the fourteenth capacitor C14 is connected to the eleventh pin of the isolation chip U2, and the second end of the fourteenth capacitor C14 is used to be grounded.

[0081] The above-mentioned isolation chip includes multiple pins. The specific description for each pin is as follows: the first pin (INA), the second pin (INB), the third pin (VDDI), the fourth pin (GNDI), the fifth pin (DIS), the sixth pin (DT), the seventh pin (NC), the eighth pin (VDDI), the ninth pin (GNDB), the tenth pin (OUTB), the eleventh pin (VDDB), the twelfth pin (NC), the thirteenth pin (NC), the fourteenth pin (GNDA), the fifteenth pin (OUTA) and the sixteenth pin (VDDA).

[0082] In the embodiment of the present application, through the isolation chip U2 and its peripheral circuits, the electrical isolation and signal transmission between the metering module and the main control device are realized. The isolation unit adopts an isolation circuit constructed by a precision resistor network (R16 to R29), multiple capacitors (C5 to C14) and the isolation chip U2, which can protect the main control device from the influence of high voltage or surges, and at the same time ensure the accuracy and real-time performance of data transmission.

[0083] As the core component, the isolation chip U2 provides an electrical isolation barrier of up to thousands of volts, effectively isolating the electrical connection between the high-voltage side and the low-voltage control side, and protecting the main control device from the damage of abnormal power grid fluctuations.

[0084] Through fine resistor voltage division, capacitor filtering and signal conversion of the isolation chip, the measurement signal output by the metering chip U1 is converted into a form suitable for the main control device to receive. At the same time, the signal quality is maintained, interference and distortion are reduced, and the accuracy of the data is ensured.

[0085] The isolation unit not only transmits measurement data, but also provides multiple control and feedback channels such as master output / slave input, selection signal, clock signal, interrupt output, etc., providing flexibility for system expansion and integration with other devices.

[0086] The capacitors used play a filtering role, effectively suppressing high-frequency interference and noise, and maintaining the cleanliness of the signal, which is crucial for stable operation in a complex electromagnetic environment.

[0087] Each signal channel has a corresponding resistor and capacitor configuration, ensuring the integrity and independence of each signal path and avoiding cross-interference.

[0088] As an alternative embodiment, the above metering module further includes a reset unit connected to the metering chip U1. Figure 7 The following is a schematic diagram of the circuit topology of a reset unit provided by an embodiment of the present application. As Figure 7 shown, the reset unit includes a thirtieth resistor R30, a thirty-first resistor R31, a thirty-second resistor R32, a thirty-third resistor R33, a fifteenth capacitor C15, a sixteenth capacitor C16, and a reset chip U3; where:

[0089] The first end of the thirtieth resistor R30, the first end of the thirty-first resistor R31, and the first end of the fifteenth capacitor C15 are respectively connected to the twentieth pin of the metering chip U1. The second end of the thirtieth resistor R30 is used to connect to the thirty-first pin of the metering chip U1. The second end of the thirty-first resistor R31 and the first end of the thirty-second resistor R32 are respectively connected to the first pin of the reset chip U3. The second end of the thirty-second resistor R32 is connected to the first end of the thirty-third resistor R33. The second end of the thirty-third resistor R33, the second end of the fifteenth capacitor C15, the second pin of the reset chip U3, and the first end of the sixteenth capacitor C16 are connected and then grounded. The second pin of the reset chip U3 is connected to the second end of the sixteenth capacitor C16 and then used to connect to the twenty-first pin of the metering chip U1.

[0090] In the embodiment of the present application, through the reset chip U3 and related components (R30 to R33, C15, C16), a reliable reset function is provided for the metering chip U1, ensuring that it can be restored to the initial state in a timely manner under abnormal conditions, and improving the overall stability and self-recovery ability. The reset unit realizes the steady-state control and debounce processing of the reset signal through a carefully configured resistor-capacitor network, ensuring the accurate execution of the reset operation.

[0091] The reset unit can actively trigger a reset when the metering chip encounters errors or abnormal states, such as power fluctuations, overloads, or software failures, causing the metering chip to be re-initialized and restored to the normal working state, improving the robustness and usability of the entire system.

[0092] The RC filter network composed of the thirty-second resistor R32, the thirty-third resistor R33, and the capacitors C15 and C16 performs debouncing processing on the reset signal, effectively filtering out instantaneous pulse interference, preventing mis-triggering of the reset, and ensuring the accuracy of the reset operation.

[0093] The hardware-level reset mechanism provides an additional layer of protection compared to pure software reset, reducing the risk of the system becoming uncontrollable due to software errors and improving the safety factor of the entire metering system.

[0094] As an optional embodiment, the above metering module further includes a crystal oscillator unit connected to the metering chip U1. Figure 8 Schematic diagram of the circuit topology of a crystal oscillator unit provided by an embodiment of the present application, as Figure 8 shown, the crystal oscillator unit includes a thirty-fourth resistor R34, a seventeenth capacitor C17, an eighteenth capacitor C18, and a crystal oscillator Y; where:

[0095] The first end of the thirty-fourth resistor R34, the first end of the seventeenth capacitor C17, and the first end of the crystal oscillator Y are respectively connected to the twenty-eighth pin of the metering chip U1. The second end of the thirty-fourth resistor R34, the first end of the eighteenth capacitor C18, and the first end of the crystal oscillator Y are respectively connected to the twenty-seventh pin of the metering chip U1. The second end of the seventeenth capacitor C17 is connected to the second end of the eighteenth capacitor C18 and then grounded.

[0096] In the embodiment of the present application, the introduction of the crystal oscillator unit provides a stable and accurate clock source for the metering chip U1 through the crystal oscillator Y and the surrounding resistors R34, capacitors C17 and C18, ensuring the timing control and data processing accuracy of the metering operation. The crystal oscillator unit optimizes the start-up characteristics of the crystal oscillator through a carefully matched resistor-capacitor network, improving the stability of the system time reference, and is a key component to ensure the reliable operation of the metering module.

[0097] The crystal oscillator Y, as the clock source of the metering chip U1, directly improves the accuracy and time synchronization performance of metering and data processing.

[0098] The thirty-fourth resistor R34 and the capacitors C17 and C18 together constitute the load matching and frequency fine-tuning network of the crystal oscillator circuit, optimizing the start-up characteristics and working stability of the crystal oscillator, and reducing the influence of external factors (such as temperature changes, power supply fluctuations) on the clock frequency.

[0099] The crystal oscillator unit is directly connected to the metering chip U1, and through a standardized interface, simplifies the complexity of system integration and reduces the additional clock distribution circuit.

[0100] As an alternative embodiment, the above metering module further includes a filtering unit, which is connected to the metering chip U1. Figure 9 The following is a schematic diagram of the circuit topology of a filtering unit provided by an embodiment of the present application. As Figure 9 shown, the filtering unit includes the nineteenth capacitor C19, the twentieth capacitor C20, the twenty-first capacitor C21, the twenty-second capacitor C22, the twenty-third capacitor C23, the twenty-fourth capacitor C24, the twenty-fifth capacitor C25, the twenty-sixth capacitor C26, the twenty-seventh capacitor C27, and the twenty-eighth capacitor C28; among them:

[0101] One end after the parallel connection of the nineteenth capacitor C19 and the twentieth capacitor C20 is used to connect to the thirty-second pin of the metering chip U1, and the other end after the parallel connection is used to ground.

[0102] One end after the parallel connection of the twenty-first capacitor C21, the twenty-second capacitor C22, the twenty-third capacitor C23, the twenty-fourth capacitor C24, the twenty-fifth capacitor C25, and the twenty-sixth capacitor C26 is used to connect to the thirty-first pin of the metering chip U1, and the other end after the parallel connection is used to ground.

[0103] One end after the parallel connection of the twenty-seventh capacitor C27 and the twenty-eighth capacitor C28 is used to connect to the twenty-ninth pin of the metering chip U1, and the other end after the parallel connection is used to ground.

[0104] In the embodiment of the present application, the filtering unit provides necessary power supply filtering and signal denoising functions for the key pins of the metering chip U1 through a group of capacitors (C19 to C28), ensuring the purity of the metering data and the stability of the system operation. The filtering unit forms a low-pass filter network by connecting multiple capacitors in parallel, effectively suppressing high-frequency interference and improving the anti-interference ability of the metering module.

[0105] The parallel connection of the nineteenth capacitor C19 and the twentieth capacitor C20 provides filtering for the power supply line of the thirty-second pin of the metering chip U1, removing high-frequency noise and ripple on the power supply line, ensuring the purity of the chip power supply, and reducing measurement errors caused by power supply interference.

[0106] The twenty-first to twenty-sixth capacitors are connected in parallel to the thirty-first pin, and the twenty-seventh and twenty-eighth capacitors are connected in parallel to the twenty-ninth pin. These filtering networks respectively filter different signal lines, effectively filtering out stray signals and interference, improving signal integrity, and making the data processed by the chip more accurate and reliable.

[0107] As an alternative embodiment, the above metering module further includes a thirty-fifth resistor R35, and the thirty-fifth resistor R35 is disposed on the line between the twenty-first pin of the metering chip U1 and the first pin of the isolation chip U2.

[0108] According to one aspect of the embodiments of the present application, a system including an inverter and a metering device is provided. The system includes the metering device described above. Therefore, the system includes all the technical effects of the above metering device. Since the technical effects of the metering device have been described in detail above, they will not be repeated here.

[0109] The above system includes, but is not limited to, adding a sub-monitoring device (Energy Control Center–PLC, abbreviated as ECC-PLC) including a metering device in a micro-inverter grid-connected system.

[0110] For ease of description, spatial relative terms such as "above", "over", "on the upper surface", "above" etc. may be used here to describe the spatial positional relationship of one device or feature to other devices or features as shown in the figures. It should be understood that the spatial relative terms are intended to encompass different orientations in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figure is inverted, the device described as "above" or "over" other devices or structures will then be positioned "below" or "beneath" other devices or structures. Thus, the exemplary term "above" can include both the orientations of "above" and "below". The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and the corresponding explanations for the spatial relative descriptions used here will be made accordingly.

[0111] In addition, it should be noted that using words such as "first", "second" etc. to define components is only for the convenience of differentiating the corresponding components. Without additional statements, the above words have no special meanings, and thus cannot be construed as limiting the protection scope of the present application.

[0112] The above are only the preferred embodiments of the present application and are not used to limit the present application. For those skilled in the art, various changes and modifications can be made to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.

Claims

1. A metering device, characterized in that: include: Two independent metering modules, and the circuit topology of the two metering modules is the same, the metering modules are integrated with a current sampling unit, a voltage sampling unit and a metering chip, and the current sampling unit and the voltage sampling unit are respectively connected to the metering chip; one of the metering modules is used to connect to the A-phase line, the B-phase line, the C-phase line and the neutral line on the inverter side, and the other metering module is used to connect to the A-phase line, the B-phase line, the C-phase line and the neutral line on the grid side.

2. The metering device according to claim 1, characterized in that The metering module further includes a current mutual induction unit, which includes a plurality of current mutual induction units; the current sampling unit includes a current sampling circuit for phase A, a current sampling circuit for phase B, and a current sampling circuit for phase C; the voltage sampling unit includes a voltage sampling circuit for phase A, a voltage sampling circuit for phase B, and a voltage sampling circuit for phase C; wherein: The multiple current transformers are respectively connected in series to the A-phase line, the B-phase line and the C-phase line, the input ends of the A-phase current sampling circuit, the B-phase current sampling circuit and the C-phase current sampling circuit are respectively connected to the corresponding current transformers, and the output ends of the A-phase current sampling circuit, the B-phase current sampling circuit and the C-phase current sampling circuit are respectively connected to the corresponding pins of the metering chip; The input ends of the A-phase voltage sampling circuit, the B-phase voltage sampling circuit and the C-phase voltage sampling circuit are respectively connected to the A-phase line, the B-phase line and the C-phase line, and the output ends of the A-phase voltage sampling circuit, the B-phase voltage sampling circuit and the C-phase voltage sampling circuit are respectively connected to the corresponding pins of the metering chip.

3. The metering device according to claim 2, characterized in that: The circuit topology structures of the three-phase current sampling circuits in the current sampling unit are all the same, and each phase current sampling circuit includes a symmetrical differential amplifier circuit composed of a plurality of TVS tubes, a plurality of resistors and a plurality of capacitors.

4. The metering device according to claim 3, characterized in that The current sampling circuit includes a first TVS tube, a second TVS tube, a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor and a second capacitor; wherein: The first end of the first TVS tube, the first end of the first resistor and the first end of the second resistor are connected as the first input end of the current sampling circuit, and the second end of the first resistor and the first end of the first capacitor are connected as the first output end of the current sampling circuit; The first end of the second TVS tube, the first end of the third resistor and the first end of the fourth resistor are connected as the second input end of the current sampling circuit, and the second end of the fourth resistor and the first end of the second capacitor are connected as the second output end of the current sampling circuit; The second end of the first TVS tube is connected to the second end of the second TVS tube and then grounded, the second end of the second resistor is connected to the second end of the third resistor and then grounded, and the second end of the first capacitor is connected to the second end of the second capacitor and then grounded.

5. The metering device according to claim 2, characterized in that: The topological structures of the three-phase voltage sampling circuits in the voltage sampling unit are the same. The voltage sampling circuit of each phase includes a voltage divider circuit composed of multiple resistors connected in series and a filter circuit composed of multiple resistors and multiple capacitors.

6. The metering device according to claim 5, characterized in that The voltage sampling circuit includes a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a third capacitor and a fourth capacitor; wherein: The fifth resistor, the sixth resistor, the seventh resistor, the eighth resistor, the ninth resistor, the tenth resistor and the eleventh resistor are sequentially connected in series to form a voltage divider circuit; The first end of the voltage divider circuit serves as the input end of the voltage sampling circuit, the second end of the voltage divider circuit is connected to the first end of the twelfth resistor and the first end of the thirteenth resistor, and the second end of the twelfth resistor is connected to the first end of the third capacitor and serves as the first output end of the voltage sampling circuit; The second end of the fourteenth resistor is connected to the first end of the fifteenth resistor, and the second end of the fifteenth resistor is connected to the first end of the fourth capacitor to serve as the second output end of the voltage sampling circuit; The second end of the thirteenth resistor is connected to the first end of the fourteenth resistor and then grounded, and the second end of the third capacitor is connected to the second end of the fourth capacitor and then grounded.

7. The metering device according to claim 2, characterized in that: The metering module further includes an isolation unit connected to the metering chip, wherein the isolation unit includes an isolation circuit composed of a plurality of resistors, a plurality of capacitors and an isolation chip.

8. The metering device according to claim 2, characterized in that The metering module further includes a reset unit connected to the metering chip, wherein the reset unit includes a reset circuit composed of a plurality of resistors, a plurality of capacitors and a reset chip.

9. The metering device according to claim 2, characterized in that: The metering module further comprises a crystal oscillator unit connected to the metering chip, wherein the crystal oscillator unit comprises a crystal oscillator circuit composed of a resistor, a plurality of capacitors and a crystal oscillator.

10. A system comprising an inverter and a metering device, characterized in that: The system comprises the metering device according to any one of claims 1 to 9.

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