Bare chip of DDoF receiving chip and DDoF module

Abstract

The utility model discloses a DDoF receiving chip bare chip and a DDoF module, and the chip comprises two VCSEL control PADs, two VCSEL power supply PADs, a VCSEL external drive PAD, a digital ground PAD, and at least one interruption PAD, which are all located at the right side of the DDoF receiving chip. Two analog power supply PADs, two SPAD power supply PADs, two clock PADs connected with each other, two data PADs connected with each other, two GPIO port PADs connected with each other, and two enabling PADs connected with each other, the DDoF receiving chip can be compatible with various packaging forms through the design that the clock PADs, the data PADs, the GPIO port PADs and the enabling PADs of the DDoF receiving chip are divided into two parts, and the bare chip substrate is interconnected through PCB routing, so that the DDoF receiving chip is compatible with various packaging forms, and the packaging efficiency is improved. The chip research and development cost, such as smaller bare chip area cost, packaging shell cost, substrate hardware cost and the like, is greatly saved, and due to high packaging compatibility, a manufacturer only needs one bare chip during stock preparation, so that the stock category, stock preparation pressure, stock preparation cost and storage and maintenance cost are greatly reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of optoelectronic detection, and particularly relates to a die of a DToF receiving chip and a DToF module. Background Art

[0002] A DToF (Direct Time-of-Flight) module is a module that directly measures the time of flight and is widely used in laser ranging technology and 3D imaging technology, and is widely used in the fields of intelligent mobile terminals, robots, aerospace, and automotive driving. The core components of a DToF module include a VCSEL (Vertical-Cavity Surface-Emitting Laser), a SPAD (Single-Photon Avalanche Diode), and a TDC (Time-to-Digital Converter), and these three modules are generally directly packaged in the DToF module.

[0003] The existing packaging methods of DToF modules generally include A packaging and S packaging. Among them, the pin layout of A packaging (as Figure 1 shown) is that two rows of pins are respectively arranged on both sides of the chip, and the pin layout of S packaging (as Figure 2 shown) is that the pins are arranged around the chip for one week. Since the pin layouts of these two packaging methods are different, the wire bonding PADs of the die of the DToF receiving chip in the DToF module also need to be set according to the external pin layout structure, and it is currently impossible to be compatible with both packaging methods at the same time, which not only increases the R & D cost but also increases the complexity of inventory management and maintenance. Content of the Utility Model

[0004] In view of the deficiencies of the above-mentioned prior art, the purpose of the utility model is to provide a die of a DToF receiving chip and a DToF module, which can improve the packaging compatibility of the die of the DToF receiving chip.

[0005] To solve the above technical problems, the utility model adopts the following technical solutions:

[0006] A die of a DToF receiving chip, which includes:

[0007] Two VCSEL control PADs, two VCSEL power supply PADs, one VCSEL external drive PAD, one digital ground PAD, and at least one interrupt PAD, all of which are located on the right side of the DToF receiving chip;

[0008] Two analog power supply PADs and two SPAD power supply PADs. The analog power supply PAD of the analog power supply PAD and the SPAD power supply of the SPAD power supply PAD are respectively located on the upper side and the lower side of the DToF chip; the analog ground PAD of the analog power supply PAD and the SPAD ground of the SPAD power supply PAD are both located on the left side of the DToF chip;

[0009] Two interconnected clock PADs of the I2C communication bus, two interconnected data PADs of the I2C communication bus, two interconnected GPIO port PADs, and two interconnected enable PADs; wherein: one clock PAD, one data PAD, one GPIO port PAD, and one enable PAD are located on the left side of the DToF chip; the other clock PAD, the other data PAD, the other GPIO port PAD are located on the upper side of the DToF chip, and the other enable PAD is located on the lower side of the DToF chip.

[0010] In the die of the DToF receiving chip, an SPAD module is provided at a position near the center of the die on the left side of the DToF receiving chip.

[0011] In the die of the DToF receiving chip, a digital logic module is provided in the middle and near the right side; an analog module is provided below the SPAD module.

[0012] In the die of the DToF receiving chip, the VLD PAD and the VCOM PAD in the two VCSEL control PADs are located in the middle of the right side of the die of the DToF receiving chip.

[0013] In the die of the DToF receiving chip, the VCSEL power PAD in the VCSEL power supply PAD is located below the right side of the DToF receiving chip, and the VCSEL ground PAD in the VCSEL power supply PAD is located above the right side of the DToF receiving chip; the VCSEL external drive PAD is located at the bottommost of the right side of the DToF receiving chip, and the digital ground PAD and the interrupt PAD are both located above the right side of the DToF receiving chip.

[0014] In the die of the DToF receiving chip, the die also includes 2 test PADs, both of which are provided on the lower side of the die.

[0015] The present utility model also provides a DToF module, which includes a substrate, and the front surface of the substrate is provided

[0016] The die of the DToF receiving chip and the VCSEL device as described above, and a plurality of pads are further provided on the front surface of the substrate, and the plurality of pads are located on the left and right sides, or the upper and lower sides and the right side of the die of the DToF receiving chip, a total of three sides.

[0017] In the DToF module, when the first packaging form is adopted, the multiple pads are located on the left and right sides of the die of the DToF receiving chip; the VCSEL power supply PAD is wire-bonded to the pad, the VCSEL external drive PAD is wire-bonded to the pad, the digital ground PAD is wire-bonded to the pad, the interrupt PAD is wire-bonded to the pad, the analog power supply PAD is wire-bonded to the pad, the SPAD power supply PAD is wire-bonded to the pad, a clock line PAD is wire-bonded to the pad, a data line PAD is wire-bonded to the pad, a GPIO port PAD is wire-bonded to the pad, and an enable PAD is wire-bonded to the pad.

[0018] In the DToF module, the two VCSEL control PADs are electrically connected to the VCSEL device.

[0019] In the DToF module, when the second packaging form is adopted, the multiple pads are located on the upper and lower sides and the right side of the die of the DToF receiving chip; the VCSEL power supply PAD is wire-bonded to the pad, the digital ground PAD is wire-bonded to the pad, the interrupt PAD is wire-bonded to the pad, the analog power supply PAD is wire-bonded to the pad, the SPAD power supply PAD is wire-bonded to the pad, a clock line PAD is wire-bonded to the pad, a data line PAD is wire-bonded to the pad, a GPIO port PAD is wire-bonded to the pad, and an enable PAD is wire-bonded to the pad.

[0020] The DToF module further includes a package body, and a plurality of pins are arranged on the package body. The pads are arranged in the package body, and the pads are connected to the pins in one-to-one correspondence.

[0021] Compared with the prior art, a die of a DToF receiving chip and a DToF module provided by the present utility model have double the number of clock PADs, data PADs, GPIO port PADs and enable PADs of the DToF receiving chip, and the design of interconnection through PCB traces on the die substrate enables it to be compatible with multiple packaging forms, extremely saving the chip R & D cost, such as the cost of a smaller die area, the cost of the package shell, the cost of the substrate hardware, etc. And due to the high packaging compatibility, manufacturers only need one type of chip die when stocking, greatly reducing the inventory categories, stocking pressure, stocking cost, and warehousing and maintenance cost. Description of the Drawings

[0022] Figure 1 It is a schematic diagram of the pin layout of a DToF module using Package A in the prior art.

[0023] Figure 2Schematic diagram of the pin layout of a DToF module using S packaging in the prior art.

[0024] Figure 3 Schematic diagram of the PAD layout of the die of the DToF receiving chip provided by the present invention.

[0025] Figure 4 Schematic diagram of the structure of the die of the DToF receiving chip provided by the present invention.

[0026] Figure 5 Schematic diagram of the PAD used when the die of the DToF receiving chip provided by the present invention adopts the first packaging form.

[0027] Figure 6 Wire bonding schematic diagram when the die of the DToF receiving chip provided by the present invention adopts the first packaging form.

[0028] Figure 7 Schematic diagram of the PAD used when the die of the DToF receiving chip provided by the present invention adopts the second packaging form.

[0029] Figure 8 Wire bonding schematic diagram when the die of the DToF receiving chip provided by the present invention adopts the second packaging form.

[0030] Figure 9 Schematic diagram of the structure of the DToF module formed when the die of the DToF receiving chip provided by the present invention adopts the first packaging form. Detailed implementation manners

[0031] In order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0032] Existing DToF module packaging methods (such as A packaging and S packaging) have different pin layouts, resulting in the need to set the wire bonding PADs of the DToF receiving chip die according to different external pin layout structures, and it is impossible to achieve simultaneous compatibility of the two packaging methods. After Figure 1 and Figure 2By comparing the two packaging methods, it can be seen that both the A packaging and S packaging methods have 12 pins. Among them, the pins of the A packaging form include: 3 VDD pins, 3 GND pins, 1 SDA pin, 1 SACL pin, 1 INT pin, 1 EN pin, 1 GPIO pin, 1 Trigo pin. The pins of the S packaging form include: 2 VDD pins, 5 GND pins, 1 SDA pin, 1 SACL pin, 1 GPIO pin, 1 XSHUT (XSHUTDOWN, indicating the shutdown signal pin) pin, 1 DNC ("DoNotConnect", indicating that no external component needs to be connected) pin. After comparison, most of the pin functions of the two packaging methods are the same, and only a few pin functions are different.

[0033] Please refer to Figure 3 and Figure 4 , the size of the die 500 of the DToF receiving chip provided by the present utility model can be 2×1.3 mm, which can be compatible with different packaging forms and VCSEL models. It includes two VCSEL control PADs 7, 8, two VCSEL power supply PADs 6, 9, one VCSEL external drive PAD 5, one digital ground PAD 10, at least one interrupt PAD 11, two analog power supply PADs 15, 16, two SPAD power supply PADs 1, 21, clock PADs 14, 17, data PADs 13, 18, two interconnected GPIO port PADs 12, 19, two interconnected enable PADs 2, 20, and two test PADs 3, 4.

[0034] Among them, when the VCSEL is packaged, it is generally set on the right side of the DToF receiving chip. The VCSEL control PADs 7, 8 need to control the VCSEL and need to be close to the VCSEL. The VCSEL power supply PADs 6, 9 need to supply power to the VCSEL and need to be close to the VCSEL. Moreover, the VCSEL power supply PADs 6, 9 only need to be connected to the VCSEL and do not need to be connected to the DToF module packaging pins. The VCSEL external drive PAD 5 needs to provide an external drive to the vscel and needs to be close to the VCSEL. Therefore, the VCSEL control PADs 7, 8, the VCSEL power supply PADs 6, 9, and the VCSEL external drive PAD 5 are all located on the right side of the DToF receiving chip.

[0035] Please refer to Figures 6 to 8 together, a SPAD module 100 is provided at a position close to the chip center on the left side of the die 500 of the DToF receiving chip, a digital logic module 200 is provided in the middle and at a position close to the right side of the die 500 of the DToF receiving chip, and an analog module 300 is provided below the SPAD module 100.

[0036] The digital ground PAD10 needs to provide ground for the digital logic module 200 inside the DToF module. Considering the internal circuit layout of the DToF receiving chip, it also needs to be placed on the right side of the die 500. The interrupt PAD11 is used to output the interrupt signal of the digital logic module 200 and needs to be close to the digital logic module 200, so it also needs to be placed on the right side of the die 500.

[0037] Since both of the two analog power supply PADs 15 and 16 supply power to the analog module 300 and the voltage is 3.3V, and both of the two SPAD power supply PADs 1 and 21 supply power to the SPAD module 100, they are located on the left side of the DToF receiving chip. Among them, the analog power supply PAD 15 in the analog power supply PAD and the SPAD power supply 1 in the SPAD power supply PAD are respectively located on the upper side and the lower side of the DToF chip; the analog ground PAD 16 in the analog power supply PAD and the SPAD ground 21 in the SPAD power supply PAD are both located on the left side of the DToF chip.

[0038] As Figure 3 、 Figure 4 shown, the analog power supply PAD 15 in the analog power supply PAD is located on the upper side of the DToF chip and is used to supply power to the analog module 300, and the SPAD power supply 1 in the SPAD power supply PAD is located on the lower side of the DToF chip and is used to supply power to the SPAD module 100; the analog ground PAD 16 in the analog power supply PAD is located in the upper part of the left side of the DToF chip and is used to supply power to the analog module 300, and the SPAD ground 21 in the SPAD power supply PAD is located in the lower part of the left side of the DToF chip and is used to supply power to the SPAD module 100.

[0039] The clock PADs 14 and 17 and the data PADs 13 and 18 are respectively the clock PADs and data PADs used by the I2C communication bus. Since the clock signal, data transmission signal, interrupt signal and enable signal are low-frequency signals with strong anti-interference ability and long wiring does not affect signal transmission, the present invention adopts a redundant design for the clock PAD, data PAD, GPIO port PAD and enable PAD, sets them in two copies, and connects the two identical PADs to each other. One PAD is distributed on the left side of the DToF receiving chip, and the other PAD is distributed on the upper side and the lower side of the DToF receiving chip to match various package forms, such as the A package form and the S package form.

[0040] Specifically, the two clock PADs 14 and 17, the two data PADs 13 and 18, the two GPIO PADs 12 and 19, and the two enable PADs 2 and 20 are respectively interconnected by PCB traces. Among them: one clock PAD 17, one data PAD 18, one GPIO PAD 19, and one enable PAD 20 are located on the left side of the DToF chip; the other clock PAD 14, the other data PAD 13, and the other GPIO PAD 12 are located on the upper side of the DToF chip, and the other enable PAD 2 is located on the lower side of the DToF chip.

[0041] The utility model designs the clock PAD, data PAD, GPIO PAD, and enable PAD of the DToF receiving chip in duplicate and interconnects them through PCB traces on the die substrate, enabling it to be compatible with multiple package forms. By improving the package compatibility, it extremely saves the chip R & D cost, such as the area cost of the smaller die 500, the package shell cost, the substrate 400 hardware cost, etc. Moreover, due to the high package compatibility, manufacturers only need one type of chip die 500 when stocking, greatly reducing the inventory categories, stocking pressure, stocking cost, and warehousing and maintenance cost.

[0042] Please continue to refer to Figure 3 and Figure 4 , the VLD PAD 7 and VCOM PAD 8 in the two VCSEL control PADs are located in the middle of the right side of the die 500 of the DToF receiving chip, making the distance from the die 500 to the external VCSEL device the closest, minimizing the wire bonding between the PAD and the VCSEL device, and minimizing the signal interference caused by the PCB traces, so as to better control the VCSEL device and have a fast control response speed.

[0043] Furthermore, the VCSEL power supply PAD, the VCSEL power PAD 6, is located below the right side of the DToF receiving chip, preferably below the VLD PAD 7, and the VCSEL ground PAD 9 in the VCSEL power supply PAD is located above the right side of the DToF receiving chip, preferably above the VCOM PAD 8, making it close to the middle of the right side of the die 500 and minimizing the distance from the VCSEL device, so as to reliably supply power to the VCSEL device.

[0044] The external drive PAD 5 of the VCSEL is used to provide external drive for the VCSEL device and needs to be as close as possible to the VCSEL device. Based on the control requirements, it is lower than the VCSEL control PAD and the VCSEL power supply PAD. Therefore, it is located at the lowermost right side of the DToF receiving chip. The digital ground PAD 10 and the interrupt PAD 11 are respectively used to provide digital ground for the digital logic module 200 and output the interrupt signal of the digital logic module 200. They need to be closer to the digital logic module 200, but the priority of their control requirements is also lower than that of the VCSEL control PAD and the VCSEL power supply PAD. Therefore, they are both located above the right side of the DToF receiving chip.

[0045] Further, the die 500 further includes two test PADs 3 and 4, which are used for connection during test packaging. During mass production, they do not need to be connected to the package pins of the DToF module. Therefore, they are both arranged on the lower side of the die 500 or other positions.

[0046] By doubling the number of the clock PAD, data PAD, GPIO port PAD and enable PAD of the DToF receiving chip and the design of interconnecting through PCB traces on the substrate 400 of the die 500, the utility model can be compatible with various packaging forms, thereby achieving lower costs for the die 500 area, package shell, substrate 400 hardware, etc. And due to the high packaging compatibility, manufacturers only need one type of chip die 500 when stocking, which greatly reduces the inventory categories, stocking pressure, stocking cost, and warehousing and maintenance cost, realizes the ultimate saving of chip R & D cost, and simplifies the supply chain management at the same time.

[0047] The utility model also provides a DToF module including a substrate 400. The front side of the substrate 400 is provided with the die 500 of the DToF receiving chip and the VCSEL device. The front side of the substrate 400 is also provided with a plurality of pads (not labeled in the figure). The plurality of pads are located on the left and right sides, or the upper and lower sides and the right side of the die 500 of the DToF receiving chip, and the positions of the pads can be specifically set according to the packaging form of the DToF module.

[0048] Please refer to Figure 5 and Figure 6 together in Figure 5Among them, the PADs represented by the dashed boxes (i.e., SDA, SCL, EN, GPIO0 PADs on the upper and lower sides of the chip) are redundant PADs and are not used in the first packaging form (such as the A packaging form). The boxes filled with slashes represent the PADs that need to be used and wire-bonded in the A packaging. Among them, the digital ground PAD 10 and the analog ground PAD 16 are electrically connected through the PCB traces on the chip substrate 400 (so there are 13 boxes filled with slashes, and the actual PADs that need external wire-bonding are 12). The two boxes with crosses are not wire-bonded during packaging. The boxes filled with squares are internal wire-bonding PADs for controlling the VCSEL device.

[0049] When the first packaging form is adopted, the packaging size is 3.6×2.2×1.0 mm. For example, in the A packaging form, the multiple pads are located on the left and right sides of the die 500 of the DToF receiving chip. The PADs of the die 500 are electrically connected to the pads on the package body through wire-bonding on the left and right, so as to ensure that the module height meets the packaging requirement of 2.2 mm in the A packaging form. Through the redundant design of the relevant PADs on the die 500, wire-bonding in the left and right directions is adopted to achieve electrical connection with the substrate 400.

[0050] During ASM packaging, the GPIO0 pin of the DToF module is configured to connect to the VPP PAD (i.e., PAD19) of the chip, and can output 7V voltage to provide power for OTP (high-voltage programming). GPIO1 is configured to connect to the trigo PAD (i.e., PAD5) of the chip, which is the pin for the external drive of vscel. It can enable the chip to have two options: internal drive and external drive. The external drive usually has a large power and can match the applications of long-distance ranging, improving the reliability of DToF.

[0051] Among them, the VCSEL power supply PADs 6 and 9 are wire-bonded to the pads 12’ and 11’, the VCSEL external drive PAD 5 is wire-bonded to the pad 10’, the digital ground PAD 10 is wire-bonded to the pad 2’, the interrupt PAD 11 is wire-bonded to the pad 4’, the analog power supply PADs 15 and 16 are wire-bonded to the pads 1’ and 2’, the SPAD power supply PADs 1 and 21 are wire-bonded to the pads 7’ and 8’, a clock line PAD 17 is wire-bonded to the pad 5’, a data line PAD 18 is wire-bonded to the pad 6’, a GPIO port PAD 19 is wire-bonded to the pad 3’, and an enable PAD 20 is wire-bonded to the pad 9’.

[0052] In a specific embodiment, on the substrate 400, the digital ground PAD 10 is connected to the analog ground PAD 16 through PCB traces. The VCSEL power supply PADs 6 and 9 are respectively connected to the VDDV pad 12' and the GNDV pad 11' through wire bonding. The external drive PAD 5 of the VCSEL is connected to the GIOP1 pad 10' through wire bonding. The digital ground PAD 10 is connected to the AVSSVCSEL pad 2 through wire bonding. The interrupt PAD 11 is connected to the INT pad 4' through wire bonding. The analog power supply PADs 15 and 16 are respectively connected to the VDDC pad 1' and the GNDC pad 2' through wire bonding. The SPAD power supply PADs 1 and 21 are respectively connected to the VDD pad 7' and the GND pad 8' through wire bonding. A clock line PAD 17 is connected to the SCL pad 5' through wire bonding. A data line PAD 18 is connected to the SDA pad 6' through wire bonding. A GPIO port PAD 19 is connected to the GPIO0 pad 3' through wire bonding. An enable PAD 20 is connected to the EN pad 9' through wire bonding.

[0053] After wire bonding the PADs on the die 500 to the pads, it is also necessary to electrically connect the two VCSEL control PADs 7 and 8 to the VCSEL device, which is also connected to the VCSEL device through wire bonding.

[0054] Please refer to Figure 7 and Figure 8 , in Figure 7 , the PADs represented by the dashed boxes (i.e., the SDA, SCL, EN, GPIO0 PADs on the left side of the chip) are redundant PADs and are not used in the second packaging form (such as the S packaging form). The boxes filled with diagonal lines represent the PADs that need to be used and wire bonded in the S packaging. Among them, the analog power supply PAD 15 and the VCSEL power supply PAD 6 are electrically connected through PCB traces on the chip substrate 400 (so there are 13 boxes filled with diagonal lines). The two crossed boxes are not wire bonded during packaging. The boxes filled with squares are internal wire bonding PADs for controlling the VCSEL device.

[0055] In the S packaging, the DNC pin of the DToF module is left unconnected. The present invention configures it to be connected to the vpp PAD (i.e., PAD19) of the chip, which can output 7V voltage to provide power for OTP (high-voltage programming).

[0056] When the second packaging form is adopted, the packaging size is 4.4×2.4×1.0 mm. In the S packaging form, the SPAD (single-photon avalanche diode) is close to the left side of the die 500, and there is no wire bonding space at the chip receiving end. Moreover, the distance between the SPAD and the VSCEL device is relatively far (generally 3 mm). Therefore, the wire bonding method of the upper and lower sides and the right side is adopted. Through the relevant pads of the present utility model (such as SDA, SCL, EN, GPIO0), redundant design is adopted, and the wire bonding in the up and down directions (utilizing the SDA, SCL, EN, GPIO0 pads on the upper and lower sides of the chip) and the wire bonding method on the right side are used to realize the electrical connection with the substrate 400. Moreover, the wire bonding between the pads of the chip and the pads of the package is made as short as possible, improving the anti-interference performance and having a fast signal transmission speed.

[0057] Among them, the multiple pads are located on the upper and lower sides and the right side of the die 500 of the DToF receiving chip; the VCSEL power supply pads 6, 9 are wire-bonded to the pads 1', 2', the digital ground pad 10 is wire-bonded to the pad 4', the interrupt pad 11 is wire-bonded to the pad 7', the analog power supply pads 15, 16 are wire-bonded to the pads 12', 6', the SPAD power supply pads 1, 21 are wire-bonded to the pads 11', 3', a clock line pad 14 is wire-bonded to the pad 10', a data line pad 13 is wire-bonded to the pad 9', a GPIO port pad 12 is wire-bonded to the pad 8', and another enable pad 2 is wire-bonded to the pad 5'.

[0058] In a specific embodiment, on the substrate 400, the analog power supply pad 15 is connected to the VCSEL external drive pad 5 through PCB traces. The VCSEL external drive pad 5 does not need to be connected to the pins of the DToF module. The VCSEL power supply pads 6, 9 are wire-bonded to the AVDDVCSEL pad 1' and the AVSSVCSEL pad 2' respectively, the digital ground pad 10 is wire-bonded to the GND2 pad 4', the interrupt pad 11 is wire-bonded to the GPIO1 pad 7', the analog power supply pads 15, 16 are wire-bonded to the GND4 pad 12' and the GND3 pad 6' respectively, the SPAD power supply pads 1, 21 are wire-bonded to the AVDD pad 11' and the GND pad 3' respectively, a clock line pad 14 is wire-bonded to the SCL pad 10', another data line pad 13 is wire-bonded to the SDA pad 9', a GPIO port pad 12 is wire-bonded to the DNC pad 8', and another enable pad 2 is wire-bonded to the XSHUT pad 5'.

[0059] The DToF module further includes a package body 600, such as Figure 9As shown, a number of pins 700 are provided on the package 600, and pads are provided in the package 600. The pads are connected to the pins 700 in a one-to-one correspondence. For example, the DNC pad 8’ corresponds to the 8th pin 700DNC, so that the positions and sizes of the pins 700 of the DToF module correspond to the PCB board that needs to be actually mounted.

[0060] In summary, the present invention solves the compatibility problem of the DToF receiving chip die under different packaging methods, provides a cost-effective and flexible solution for manufacturers, and helps to promote the application and development of DToF technology in various fields. Through the design of doubling the number of clock PAD, data PAD, GPIO port PAD, and enable PAD of the DToF receiving chip, and interconnecting them through PCB traces on the die substrate, it can be compatible with a variety of packaging forms, extremely saving the chip R & D cost, such as the cost of a smaller die area, the cost of the package shell, the cost of the substrate hardware, etc. And due to the high packaging compatibility, manufacturers only need one type of chip die when stocking, greatly reducing the inventory category, stocking pressure, stocking cost, and warehousing and maintenance cost.

[0061] At the same time, the present invention reduces the OTP power supply module inside the chip. The power supply pins are connected to an external power supply to achieve this, reducing unnecessary functions, reducing the chip area and simplifying the chip design, and can also reduce the power consumption of the chip. Moreover, by obtaining power from the outside through the module pins, it is possible to avoid integrating a power management circuit on the chip, thereby reducing the area.

[0062] It can be understood that for those of ordinary skill in the art, equivalent substitutions or changes can be made according to the technical solution and the inventive concept of the present invention, and all such changes or substitutions should fall within the protection scope of the appended claims of the present invention.

Claims

1. A bare chip of a DToF receiving chip, characterized in that: include: Two VCSEL control PADs, two VCSEL power supply PADs, a VCSEL external drive PAD, a digital ground PAD, and at least one interrupt PAD, all of which are located on the right side of the DToF receiving chip; Two analog power supply PADs and two SPAD power supply PADs, the analog power supply PAD in the analog power supply PAD and the SPAD power supply of the SPAD power supply PAD are respectively located on the upper side and the lower side of the DToF chip; the analog ground PAD in the analog power supply PAD and the SPAD ground of the SPAD power supply PAD are both located on the left side of the DToF chip; Two interconnected clock PADs of the I2C communication bus, two interconnected data PADs of the I2C communication bus, two interconnected GPIO port PADs, and two interconnected enable PADs; wherein: one clock PAD, one data PAD, one GPIO port PAD, and one enable PAD are located on the left side of the DToF chip; another clock PAD, another data PAD, and another GPIO port PAD are located on the upper side of the DToF chip, and another enable PAD is located on the lower side of the DToF chip.

2. The bare chip of the DToF receiving chip according to claim 1, characterized in that: A SPAD module is provided on the left side of the bare die of the DToF receiving chip near the center of the chip; A digital logic module is arranged in the middle of the bare die of the DToF receiving chip and near the right side; an analog module is arranged below the SPAD module.

3. The bare chip of the DToF receiving chip according to claim 1, characterized in that: The VLD PAD and the VCOM PAD in the two VCSEL control PADs are located in the middle of the right side of the bare die of the DToF receiving chip.

4. The bare chip of the DToF receiving chip according to claim 1, characterized in that: The VCSEL power PAD in the VCSEL power supply PAD is located at the lower right side of the DToF receiving chip, and the VCSEL ground PAD in the VCSEL power supply PAD is located above the right side of the DToF receiving chip; the VCSEL external drive PAD is located at the bottom of the right side of the DToF receiving chip, and the digital ground PAD and the interrupt PAD are both located above the right side of the DToF receiving chip.

5. The bare chip of the DToF receiving chip according to claim 1, characterized in that: The die also includes two test PADs, both disposed on the lower side of the die.

6. A DToF module, characterized in that: It includes a substrate, the front side of which is provided with a bare chip and a VCSEL device of a DToF receiving chip as described in any one of claims 1 to 5, and the front side of the substrate is also provided with a plurality of solder pads, and the plurality of solder pads are located on the left and right sides or the upper and lower sides and the right side of the bare chip of the DToF receiving chip.

7. The DToF module according to claim 6, characterized in that: When the first packaging form is adopted, the multiple pads are located on the left and right sides of the bare die of the DToF receiving chip; the two VCSEL power supply PADs are connected to the VDDV pad and the GNDV pad by wiring, the VCSEL external drive PAD is connected to the GIOP1 pad by wiring, the digital ground PAD is connected to the AVSSVCSEL pad by wiring, the interrupt PAD is connected to the INT pad by wiring, the two analog power supply PADs are connected to the VDDC pad and the GNDC pad by wiring, the SPAD power supply PAD is connected to the VDD pad and the GND pad by wiring, a clock line PAD is connected to the SCL pad by wiring, a data line PAD is connected to the SDA pad by wiring, a GPIO port PAD is connected to the GPIO0 pad by wiring, and an enable PAD is connected to the EN pad by wiring.

8. The DToF module according to claim 7, characterized in that: The two VCSEL control PADs are electrically connected to the VCSEL device.

9. The DToF module according to claim 6, characterized in that: When the second packaging form is adopted, the multiple pads are located on the upper and lower sides and right side of the bare die of the DToF receiving chip; the VCSEL power supply PAD is connected to the AVDDVCSEL pad and the AVSSVCSEL pad by wiring, the digital ground PAD is connected to the GND2 pad by wiring, the interrupt PAD is connected to the GPIO1 pad by wiring, the analog power supply PAD is connected to the GND4 pad and the GND pad by wiring, the SPAD power supply PAD is connected to the AVDD pad and the GND pad by wiring, a clock line PAD is connected to the SCL pad by wiring, another data line PAD is connected to the SDA pad by wiring, another GPIO port PAD is connected to the DNC pad by wiring, and another enable PAD is connected to the XSHUT pad by wiring.

10. The DToF module according to claim 6, characterized in that: It also includes a package body, on which a plurality of pins are arranged, and in which the pads are arranged, and the pads are connected with the pins in a one-to-one correspondence.

Images